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Íç³ ! ôi2cpclkdefault!okayë€pmic@20rockchip,rk809¡ &Í rk808-clkout1rk808-clkout2default9GS_kwƒ�›§Å`regulatorsDCDC_REG1 ³vdd_npu_vepuÂÖèÿ ë~ð/qregulator-state-memDDCDC_REG2³vdd_armÂÖèÿ ™p/qÅregulator-state-memDDCDC_REG3³vcc_ddrÂÖèregulator-state-mem]DCDC_REG4 ³vcc3v3_sysÂÖèÿ2Z 2Z Åregulator-state-mem]u2Z DCDC_REG5 ³vcc_buck5ÂÖÿ!‘À!‘ÀÅregulator-state-mem]u!‘ÀLDO_REG1³vcc_0v8ÂÖÿ 5 5regulator-state-memDLDO_REG2 ³vcc1v8_pmuÂÖÿw@w@regulator-state-mem]uw@LDO_REG3 ³vcc0v8_pmuÂÖÿ 5 5regulator-state-mem]u 5LDO_REG4³vcc_1v8ÂÖÿw@w@Åregulator-state-mem]uw@LDO_REG5 ³vcc_dovddÂÖÿw@w@regulator-state-memDLDO_REG6 ³vcc_dvddÿO€O€regulator-state-memDLDO_REG7 ³vcc_avddÿ*¹€*¹€regulator-state-memDLDO_REG8 ³vccio_sdÂÖÿw@2Z Å regulator-state-memDLDO_REG9 ³vcc3v3_sdÂÖÿ2Z 2Z Å regulator-state-memDSWITCH_REG1³vcc_5v0SWITCH_REG2³vcc_3v3ÂÖÅ i2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿ@ Íç³ " ôi2cpclkdefault!okayë€rtc@51 nxp,pcf8563¡Q&Íxin32kserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿA Í ën6³  ôbaudclkapb_pclk‘–txrxdefault ª !disabledpwm@ff430000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC ôpwmpclk³#default· !disabledpwm@ff430010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC ôpwmpclk³#default· !disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC  ôpwmpclk³#default · !disabledpwm@ff430030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC0 ôpwmpclk³#default!· !disabledpwm@ff440000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD ôpwmpclk³$default"· !disabledpwm@ff440010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD ôpwmpclk³$default#· !disabledpwm@ff440020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD  ôpwmpclk³$default$· !disabledpwm@ff440030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD0 ôpwmpclk³$default%· !disabledclock-controller@ff480000rockchip,rv1126-pmucru¡ÿHç&ÂÅclock-controller@ff490000rockchip,rv1126-cru¡ÿI³'ôxin24mç&ÂÅdma-controller@ff4e0000arm,pl330arm,primecell¡ÿN@ÍÏÚ³¡ ôapb_pclkÅi2c@ff520000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿR ͳ" ôi2cpclkdefault(ç !disabledpwm@ff550000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU ôpwmpclk³')default· !disabledpwm@ff550010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU ôpwmpclk³'*default· !disabledpwm@ff550020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU  ôpwmpclk³'+default· !disabledpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU0 ôpwmpclk³',default· !disabledserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿV Í ën6³úôbaudclkapb_pclk‘–txrxdefault -./ ª!okayñbluetoothrealtek,rtl8723ds-bt 0 0  00„€default 123serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿW Íën6³ûôbaudclkapb_pclk‘ –txrxdefault4 ª!okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿX Íën6³üôbaudclkapb_pclk‘  –txrxdefault5 ª!okayserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿY Íën6³ýôbaudclkapb_pclk‘  –txrxdefault6 ª!okayserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿZ Íën6³ þôbaudclkapb_pclk‘–txrxdefault7 ª !disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc¡ÿ^ Í(:³, ôsaradcapb_pclkL; Ssaradc-apb!okay_timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timer¡ÿf  ͳ - ôpclktimerwatchdog@ff680000 rockchip,rv1126-wdtsnps,dw-wdt¡ÿh Í ³ø !disabledi2s@ff800000rockchip,rv1126-i2s-tdm¡ÿ€ Í.³=AÍômclk_txmclk_rxhclk‘–txrxdefault(89:;<=>?@ALcd Stx-mrx-mç&k !disabledvop@ffb00000rockchip,rv1126-vop¡ÿ°ÿ°  Í;ôaclk_vopdclk_vophclk_vop³¯šÚ SaxiahbdclkL†‡ˆ|BƒC  !disabledportÅendpoint@0¡endpoint@1¡iommu@ffb00f00rockchip,iommu¡ÿ° Í; ôaclkiface³¯Ú‘ƒC  !disabledÅBethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a¡ÿÄ@Í_`žmacirqeth_wake_irqç&@³~ˆˆ¿ˆ‰Tôstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_refL¾ Sstmmaceth®¿ÈDØEëF!okayþ}~ˆ|}‡%úð€:outputGGRrmii[ defaultHIJKmdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-ieee802.3-c22¡defaultLfwÃP‡' ™MÅGstmmac-axi-config¥µÅÅDrx-queues-configÏÅEqueue0tx-queues-configåÅFqueue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÅ@ ÍN ³èrstôbiuciuciu-driveciu-sampleû ëƒC!okay0?defaultNOPQMZk wmmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÆ@ ÍL ³älmnôbiuciuciu-driveciu-sampleû ëÂ!okay„•ÈdefaultRSTUMZ§´Áw mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÇ@ ÍM ³æopqôbiuciuciu-driveciu-sampleû}x@ƒC!okayÏÜòV?default WXYMZk wspi@ffc90000 rockchip,sfc¡ÿÉ@ ÍPþv%Ä´ôclk_sfchclk_sfc³vêƒC !disabledpinctrlrockchip,rv1126-pinctrlç&ý gpio@ff460000rockchip,gpio-bank¡ÿF Í"³&!¦»Ågpio@ff620000rockchip,gpio-bank¡ÿb Í#³(!¦»Å0gpio@ff630000rockchip,gpio-bank¡ÿc Í$³)!¦»ÅMgpio@ff640000rockchip,gpio-bank¡ÿd Í%³*!¦»gpio@ff650000rockchip,gpio-bank¡ÿe Í&³ +!¦»pcfg-pull-up-Å]pcfg-pull-down:Å\pcfg-pull-noneIÅZpcfg-pull-none-drv-level-3IVÅ_pcfg-pull-up-drv-level-2-VÅ[pcfg-pull-none-drv-level-0-smtIVeÅ^clk_out_ethernetemmcemmc-rstnoutzZÅQemmc-bus8€z[[[[[[[[ÅNemmc-clkz[ÅPemmc-cmdz[ÅOfspii2c0i2c0-xfer z ^ ^Åi2c2i2c2-xfer z^^Åi2c3i2c3m0-xfer zZZÅ(i2s0i2s0m0-lrck-txzZÅ;i2s0m0-lrck-rxzZÅ<i2s0m0-mclkzZÅ:i2s0m0-sclk-rxzZÅ9i2s0m0-sclk-txzZÅ8i2s0m0-sdi0zZÅ=i2s0m0-sdo0zZÅ>i2s0m0-sdo1-sdi3zZÅ?i2s0m0-sdo2-sdi2zZÅ@i2s0m0-sdo3-sdi1zZÅAi2s0m1-lrck-txzZi2s0m1-lrck-rxz Zi2s0m1-mclkzZi2s0m1-sclk-rxz Zi2s0m1-sclk-txzZi2s0m1-sdi0zZi2s0m1-sdo0zZi2s0m1-sdo1-sdi3z Zi2s0m1-sdo2-sdi2z Zi2s0m1-sdo3-sdi1z Zpwm0pwm0m0-pinszZÅpwm1pwm1m0-pinszZÅpwm2pwm2m0-pinszZÅ pwm3pwm3m0-pinszZÅ!pwm4pwm4m0-pinszZÅ"pwm5pwm5m0-pinszZÅ#pwm6pwm6m0-pinsz ZÅ$pwm7pwm7m0-pinsz ZÅ%pwm8pwm8m0-pinszZÅ)pwm9pwm9m0-pinszZÅ*pwm10pwm10m0-pinszZÅ+pwm11pwm11m0-pinszZÅ,rgmiirgmiim1-miim zZZÅHrgmiim1-rxerzZÅIrgmiim1-bus2`z ZZ Z___ÅJrgmiim1-mclkinoutzZÅKsdmmc0sdmmc0-bus4@z[[[[ÅTsdmmc0-clkz[ÅRsdmmc0-cmdz [ÅSsdmmc0-detzZÅUsdmmc1sdmmc1-bus4@z [ [[[ÅYsdmmc1-clkz [ÅWsdmmc1-cmdz [ÅXuart0uart0-xfer z]]Å-uart0-ctsnzZÅ.uart0-rtsnzZÅ/uart1uart1m0-xfer z]]Åuart2uart2m1-xfer z]]Å4uart3uart3m2-xfer z]]Å5uart4uart4m2-xfer z]]Å6uart5uart5m0-xfer z]]Å7etherneteth-phy-rstz\ÅLbtbt-enablezZÅ1bt-wake-devzZÅ2bt-wake-hostzZÅ3pmicpmic-int-lz ]Åwifiwifi-enable-hzZÅachosenˆserial2:1500000n8regulator-vcc5v0-sysregulator-fixed ³vcc5v0_sysÂÖÿLK@LK@Åpwrseq-sdiommc-pwrseq-simple³` ôext_clockdefaulta ™0ÅV #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2i2c3serial0serial1serial2serial3serial4serial5ethernet0mmc0mmc1mmc2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosmax-speed#io-channel-cellsresetsreset-namesvref-supply#sound-dai-cellsiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplyreset-active-lowreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path