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endpoint@0!\qiendpoint@1!]qgendpoint@2!^qaendpoint@3!_qdiommu@ff940300rockchip,iommuÿ” ÒEÆÒ aclkiface U äSokayq[dsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsiÿ–@ ÒE~d refpclk U ß1 Sdisabledportsport@0endpoint@0!`qYendpoint@1!aq^port@1lvds@ff96c000rockchip,rk3288-lvdsÿ–À@Eg pclk_lvds¤lcdc²b U ß1 Sdisabledportsport@0endpoint@0!cqZendpoint@1!dq_port@1dp@ff970000rockchip,rk3288-dpÿ—@ Òb¡h± EicdppclkÚeßdp U oGdpß1 Sdisabledportsport@0endpoint@0!fqXendpoint@1!gq]port@1hdmi@ff980000rockchip,rk3288-dw-hdmiÿ˜  ÒgEhmniahbisfrcec U ß1žSokayportsport@0endpoint@0!hqWendpoint@1!iq\port@1video-codec@ff9a0000rockchip,rk3288-vpuÿšÒ   5vepuvdpuEÐÜ aclkhclkj U iommu@ff9a0800rockchip,iommuÿš Ò EÐÜ aclkifaceä U qjvideo-codec@ff9c0000rockchip,rk3288-vdecÿœ@ Ò  EÏÛopaxiahbcabaccore ¡ÏÛop~ׄõáá£á£k U iommu@ff9c0440rockchip,iommu ÿœ@@ÿœ€@ ÒoEÏÛ aclkifaceä U qkgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760ÿ£$Ò 5jobmmugpuEÀ"l6 U  Sdisabledq.opp-table-1operating-points-v2qlopp-100000000„õá‹~ðopp-200000000„ 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supply#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplysystem-power-controller#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervalenable-active-highstartup-delay-us