Ð þíeÉ8_˜(1_`$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/pinctrl/gpio@11110000C/pinctrl/gpio@11120000I/pinctrl/gpio@11130000O/pinctrl/gpio@11140000U/serial@11010000]/serial@11020000e/serial@11030000m/spi@11090000r/mmc@30020000cpuscpu@f00wcpu,arm,cortex-a7ƒ‡Ž¢±¸psciÆÑcpu@f01wcpu,arm,cortex-a7ƒ‡Ž¢¸psciÆÑcpu@f02wcpu,arm,cortex-a7ƒ‡Ž¢¸psciÆÑcpu@f03wcpu,arm,cortex-a7ƒ‡Ž¢¸psciÆÑopp-table-0,operating-points-v2ÙÑopp-408000000äQ–ë~ðùœ@ opp-600000000ä#ÃFëà˜opp-816000000ä0£,ëB@opp-1008000000ä<ÜëíØopp-1200000000äG†Œëtxopp-1296000000äM?dë7Èopp-1392000000äRø<ëûopp-1464000000äWBÞë\Àarm-pmu,arm,cortex-a7-pmu0LMNO!psci,arm,psci-1.0arm,psci-0.2¿smctimer,arm,armv7-timer40   Xn6oscillator ,fixed-clockXn6hxin24m{Ñ+display-subsystem,rockchip,display-subsystemˆ i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sƒ @ Ži2s_clki2s_hclk±Q»š  Ÿtxrx©default·  Ádisabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sƒ @ Ži2s_clki2s_hclk±Pºš Ÿtxrx Ádisabledspdif@100d0000,rockchip,rk3228-spdifƒ  ±S½ Žmclkhclkš Ÿtx©default·  Ádisabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sƒ@ Ži2s_clki2s_hclk±R¼š Ÿtxrx Ádisabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdƒÑ,io-domains",rockchip,rk3228-io-voltage-domainÁokayÈ Öä power-controller!,rockchip,rk3228-power-controlleròÑ2power-domain@4ƒ8±ÎˆÌÔÍÓ‡òpower-domain@5ƒ±Ó¾Äòpower-domain@6ƒ±ÊÐòpower-domain@7ƒ ±ËÑ…†òpower-domain@8ƒ±Õòusb2phy@760,rockchip,rk3228-usb2phyƒ` ±ŽŽphyclk husb480m_phy0{ÁokayÑFotg-port$;<= otg-bvalidotg-idlinestateÁokayÑEhost-port >  linestateÁokay(ÑGusb2phy@800,rockchip,rk3228-usb2phyƒ ±�Žphyclk husb480m_phy1{ÁokayÑHotg-port D  linestateÁokay(ÑIhost-port E  linestateÁokay(ÑJserial@11010000,snps,dw-apb-uartƒ 7Xn6±MUŽbaudclkapb_pclk©default ·3= Ádisabledserial@11020000,snps,dw-apb-uartƒ 8Xn6±NVŽbaudclkapb_pclk©default·3= Ádisabledserial@11030000,snps,dw-apb-uartƒ 9Xn6±OWŽbaudclkapb_pclk©default·3=Áokayefuse@11040000,rockchip,rk3228-efuseƒ ±G Žpclk_efuseid@7ƒcpu_leakage@17ƒi2c@11050000,rockchip,rk3228-i2cƒ $Ži2c±L©default· Ádisabledi2c@11060000,rockchip,rk3228-i2cƒ %Ži2c±M©default· Ádisabledi2c@11070000,rockchip,rk3228-i2cƒ &Ži2c±N©default·  Ádisabledi2c@11080000,rockchip,rk3228-i2cƒ 'Ži2c±O©default·! Ádisabledspi@11090000,rockchip,rk3228-spiƒ  1±ARŽspiclkapb_pclk©default·"#$%& Ádisabledwatchdog@110a0000 ,rockchip,rk3228-wdtsnps,dw-wdtƒ  (±b Ádisabledpwm@110b0000,rockchip,rk3288-pwmƒ J±^©default·' Ádisabledpwm@110b0010,rockchip,rk3288-pwmƒ J±^©default·(ÁokayÑWpwm@110b0020,rockchip,rk3288-pwmƒ J±^©default·)ÁokayÑXpwm@110b0030,rockchip,rk3288-pwmƒ 0J±^©default·* Ádisabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerƒ  + ±a+ Žpclktimerclock-controller@110e0000,rockchip,rk3228-cruƒ±+Žxin24mU,{bHoÒÞkÃÌb$#g¸€0£,ÍeðÑ€ðÑ€xhÀðÑ€ðÑ€xhÀÑdma-controller@110f0000,arm,pl330arm,primecellƒ@”Ÿ±Â Žapb_pclkÑ thermal-zonescpu-thermal¶d̈Ú-tripscpu_alert0êpöÐ~passiveÑ.cpu_alert1ê$øöÐ~passiveÑ/cpu_critê_�öÐ ~criticalcooling-mapsmap0.0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1/0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@11150000,rockchip,rk3228-tsadcƒ :±HXŽtsadcapb_pclkoH€‡W tsadc-apb©initdefaultsleep·0!1+05KsÁokaybÑ-hdmi-phy@12030000,rockchip,rk3228-hdmi-phyƒ±m+¿Žsysclkrefoclkrefpclk{ hhdmiphy_phy ÁdisabledÑ7gpu@20000000",rockchip,rk3228-maliarm,mali-400ƒ H gpgpmmupp0ppmmu0pp1ppmmu1±ÕÕ Žbuscorey2‡~ Ádisabledvideo-codec@20020000(,rockchip,rk3228-vpurockchip,rk3399-vpuƒ     vepuvdpu±ÊÐ Žaclkhclk‡3y2iommu@20020800,rockchip,iommuƒ   ±ÊÐ Žaclkifacey2ŽÑ3video-codec@20030000*,rockchip,rk3228-vdecrockchip,rk3399-vdecƒ €  ±ËÑ…†Žaxiahbcabaccoreo…†á£á£‡4y2iommu@20030480,rockchip,iommuƒ €@ À@ ±ËÑ Žaclkifacey2ŽÑ4vop@20050000,rockchip,rk3228-vopƒ ü  ±Ó¾ÄŽaclk_vopdclk_vophclk_vop‡def axiahbdclk‡5y2 ÁdisabledportÑ endpoint@0ƒ›6Ñ;iommu@20053f00,rockchip,iommuƒ ?  ±ÓÄ Žaclkifacey2Ž ÁdisabledÑ5rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgaƒ  !±ÍÓ‡Žaclkhclksclky2‡kmn coreaxiahbiommu@20070800,rockchip,iommuƒ  ±ÌÔ Žaclkifacey2Ž Ádisabledhdmi@200a0000,rockchip,rk3228-dw-hdmiƒ = #o�«7±l{‰Žiahbisfrcec©default ·89:‡`hdmiÂ7ÇhdmiU, Ádisabledportsport@0ƒendpoint›;Ñ6port@1ƒmmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcƒ0@   ±ÈDrvŽbiuciuciu-driveciu-sampleÑ©default ·<=> Ádisabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcƒ0@   ±ÉEswŽbiuciuciu-driveciu-sampleÑ©default ·?@A Ádisabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcƒ0@ X<4`Ü<4` ±ËGuyŽbiuciuciu-driveciu-sampleêôžÑ©default ·BCD‡SresetÁokay$usb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2ƒ0 ±ÚŽotg2otg:L[€€@ ÂE Çusb2-phyÁokayusb@30080000 ,generic-ehciƒ0  ±×FÂGÇusbÁokayusb@300a0000 ,generic-ohciƒ0   ±×FÂGÇusbÁokayusb@300c0000 ,generic-ehciƒ0   ±ØHÂIÇusbÁokayusb@300e0000 ,generic-ohciƒ0  ±ØHÂIÇusbÁokayusb@30100000 ,generic-ehciƒ0 B ±ÙHÂJÇusbÁokayusb@30120000 ,generic-ohciƒ0 C ±ÙHÂJÇusbÁokayethernet@30200000,rockchip,rk3228-gmacƒ0   macirq8±~�‚€ÔoMŽstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac‡8 stmmacethU,Áokayo}~ «K}jinput(Lwrgmii©default·M €N� ¦'B@»0Äqos@31030080,rockchip,rk3228-qossysconƒ1€ Ñqos@31030100,rockchip,rk3228-qossysconƒ1 Ñqos@31030180,rockchip,rk3228-qossysconƒ1€ Ñqos@31030200,rockchip,rk3228-qossysconƒ1 Ñqos@31040000,rockchip,rk3228-qossysconƒ1 Ñqos@31050000,rockchip,rk3228-qossysconƒ1 Ñqos@31060000,rockchip,rk3228-qossysconƒ1 Ñqos@31070000,rockchip,rk3228-qossysconƒ1 Ñqos@31070080,rockchip,rk3228-qossysconƒ1€ Ñinterrupt-controller@32010000 ,arm,gic-400Íâ ƒ22 2@ 2`   Ñpinctrl,rockchip,rk3228-pinctrlU,ógpio@11110000,rockchip,gpio-bankƒ 3±@ú Íâgpio@11120000,rockchip,gpio-bankƒ 4±Aú Íâgpio@11130000,rockchip,gpio-bankƒ 5±Bú ÍâÑNgpio@11140000,rockchip,gpio-bankƒ 6±Cú ÍâÑSpcfg-pull-upÑRpcfg-pull-down#ÑQpcfg-pull-none2ÑPpcfg-pull-none-drv-12ma? ÑOsdmmcsdmmc-clkNOÑ<sdmmc-cmdNOÑ=sdmmc-bus4@NOOOOÑ>sdiosdio-clkNOÑ?sdio-cmdNOÑ@sdio-bus4@NOOOOÑAemmcemmc-clkNPÑBemmc-cmdNPÑCemmc-bus8€NPPPPPPPPÑDgmacrgmii-pinsðNP PPOOOO O OPPPP PPÑMrmii-pins NP PPOO OPPPPphy-pins NPPhdmihdmi-hpdNQÑ9hdmii2c-xfer NPPÑ8hdmi-cecNPÑ:i2c0i2c0-xfer NPPÑi2c1i2c1-xfer NPPÑi2c2i2c2-xfer NPPÑ i2c3i2c3-xfer NPPÑ!spi0spi0-clkN RÑ"spi0-cs0NRÑ%spi0-txN RÑ#spi0-rxN RÑ$spi0-cs1N RÑ&spi1spi1-clkNRspi1-cs0NRspi1-rxNRspi1-txNRspi1-cs1NRi2s1i2s1-bus�NP P P P PPPPPÑ pwm0pwm0-pinNPÑ'pwm1pwm1-pinNPÑ(pwm2pwm2-pinN PÑ)pwm3pwm3-pinN PÑ*spdifspdif-txNPÑ tsadcotp-pinNPÑ0otp-outNPÑ1uart0uart0-xfer NPPÑuart0-ctsNPÑuart0-rtsNPÑuart1uart1-xfer N P PÑuart1-ctsNPuart1-rtsN Puart2uart2-xfer NRPÑuart21-xfer N R Puart2-ctsNPuart2-rtsNPkeyspwr-keyNRÑYusbhost-vbus-drvNPÑTmemory@60000000wmemoryƒ`@regulator-dc-12v,regulator-fixed\dc_12vk‘·©·ÑVext_gmac ,fixed-clockXsY@ hext_gmac{ÑKregulator-vcc-host,regulator-fixedÁ ‹S©default·T \vcc_hostkÔUÑregulator-vcc-phy,regulator-fixedÁ\vcc_phy‘w@©w@kÔÑLregulator-vcc-sys,regulator-fixed\vcc_sysk‘LK@©LK@ÔVÑUregulator-vccio-1v8,regulator-fixed \vccio_1v8‘w@©w@kÔUÑregulator-vccio-3v3,regulator-fixed \vccio_3v3‘2Z ©2Z kÔUÑ regulator-vdd-arm,pwm-regulatorßWa¨äU\vdd_arm‘~ð©\ÀkÑregulator-vdd-log,pwm-regulatorßXa¨äU\vdd_log‘B@©Ö kgpio-keys ,gpio-keysï©default·Ypower-keyúGPIO Key Power Std# #address-cells#size-cellsinterrupt-parentcompatiblemodelgpio0gpio1gpio2gpio3serial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supply#power-domain-cellspm_qosinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modepower-domainsiommus#iommu-cellsremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source