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Íp!-!.!, € ëÂn6 ëÂ(0!,!*!+!-!.•corebusaxiblocktimerm 랟 ¡¢default(ç!!!!!ácorebusaxiblocktimer×üokay{äó ¨ ¾£ʤrng@fe378000rockchip,rk3588-rng þ7€ �0 ç¥0i2s@fe470000rockchip,rk3588-i2s-tdm þG ´0!+!/!(•mclk_txmclk_rxhclkp!)!-�!!ã33ètxrx¡"&ç!*!+ átx-mrx-m !default¦§¨©ª¤üokayøEi2s@fe480000rockchip,rk3588-i2s-tdm þH µ0!y!}!u•mclk_txmclk_rxhclkã33ètxrxç!^!_ átx-mrx-m !default(«¬­®¯°±²³´¤ üdisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2s þI ¶0!!•i2s_clki2s_hclkp!�!ã~~ètxrx¡"&defaultµ¶·¸¤ üdisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2s þJ ·0!%!•i2s_clki2s_hclkp!"�!ã~~ètxrx¡"&default¹º»¼¤ üdisabledspdif-tx@fe4e0000,rockchip,rk3588-spdifrockchip,rk3568-spdif þN�!p!7 •mclkhclk0!9!6ètxã3 Á½default¡"&¤ üdisabledspdif-tx@fe4f0000,rockchip,rk3588-spdifrockchip,rk3568-spdif þO�!p!= •mclkhclk0!?!<ètxã~ ¾default¡"&¤ üdisabledinterrupt-controller@fe600000 arm,gic-v3  þ`þh  Y < Lþa V¨8 aKÏ+ømsi-controller@fe640000arm,gic-v3-its þd < a pøŠmsi-controller@fe660000arm,gic-v3-its þf < a pø*ppi-partitionsinterrupt-partition-0 {øinterrupt-partition-1 { ø dma-controller@fea10000arm,pl330arm,primecell þ¡@  VW „0!n •apb_pclk ›ø3dma-controller@fea30000arm,pl330arm,primecell þ£@  XY „0!o •apb_pclk ›ø~i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c þ©0!ƒ!{ •i2cpclk >¿default+ üdisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c þª0!„!| •i2cpclk ?Àdefault+üokayregulator@42rockchip,rk8602 B( Evdd_npu_s0hzdp’~ðªü¿2ø9regulator-state-memÊi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ«0!…!} •i2cpclk @Ádefault+ üdisabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ¬0!†!~ •i2cpclk AÂdefault+ üdisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ­0!‡! •i2cpclk BÃdefault+ üdisabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer þ®  !0!T!W •pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt þ¯0!d!c •tclkpclk ;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spi þ° F0!—!’•spiclkapb_pclkã33ètxrx ¦ÄÅdefault+ üdisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spi þ± G0!˜!“•spiclkapb_pclkã33ètxrx ¦ ÆÇÈdefault+ üdisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spi þ² H0!™!”•spiclkapb_pclkã~~ètxrx ¦ÉÊdefault+üokayp!™€ ëÂpmic@0rockchip,rk806  Ë defaultÌÍÎÏ ­B@ ¿ ×2 ã2 ï2 û2 2 2 2 +2 72 C2 PÐ ]2 jÑ wÑ „2 �  dvs1-null-pins ¬gpio_pwrctrl1 ±pin_fun0øÍdvs2-null-pins ¬gpio_pwrctrl2 ±pin_fun0øÎdvs3-null-pins ¬gpio_pwrctrl3 ±pin_fun0øÏregulatorsdcdc-reg1hzdp’~ðª0Ô Evdd_gpu_s0 º�ø$regulator-state-memÊdcdc-reg2Thzdp’~ðª0ÔEvdd_cpu_lit_s0øregulator-state-memÊdcdc-reg3Thz L¸’ q°ª0Ô Evdd_log_s0regulator-state-memÊ Ö q°dcdc-reg4Thzdp’~ðª0Ô Evdd_vdenc_s0regulator-state-memÊdcdc-reg5Thz L¸’ » ª0Ô Evdd_ddr_s0regulator-state-memÊ Ö øPdcdc-reg6Th Evdd2_ddr_s3regulator-state-mem òdcdc-reg7Thz„€’„€ª0ÔEvdd_2v0_pldo_s3øÐregulator-state-mem ò Ö„€dcdc-reg8Thz2Z ’2Z  Evcc_3v3_s3ø£regulator-state-mem ò Ö2Z dcdc-reg9Th Evddq_ddr_s0regulator-state-memÊdcdc-reg10Thzw@’w@ Evcc_1v8_s3ø¤regulator-state-mem ò Öw@pldo-reg1Thzw@’w@ Eavcc_1v8_s0øòregulator-state-memÊpldo-reg2Thzw@’w@ Evcc_1v8_s0regulator-state-memÊ Öw@pldo-reg3ThzO€’O€ Eavdd_1v2_s0regulator-state-memÊpldo-reg4Thz2Z ’2Z ª0Ô Evcc_3v3_s0regulator-state-memÊpldo-reg5Thzw@’2Z ª0Ô Evccio_sd_s0øœregulator-state-memÊpldo-reg6Thzw@’w@ Epldo6_s3regulator-state-mem ò Öw@nldo-reg1Thz q°’ q° Evdd_0v75_s3regulator-state-mem ò Ö q°nldo-reg2Thz øP’ øPEvdd_ddr_pll_s0regulator-state-memÊ Ö øPnldo-reg3Thz q°’ q° Eavdd_0v75_s0regulator-state-memÊnldo-reg4Thz øP’ øP Evdd_0v85_s0regulator-state-memÊnldo-reg5Thz q°’ q° Evdd_0v75_s0regulator-state-memÊspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spi þ³ I0!š!••spiclkapb_pclkã~~ètxrx ¦ ÒÓÔdefault+ üdisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uart þ´ L0!«!Ÿ•baudclkapb_pclkã33 ètxrxÕdefaultüò üdisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uart þµ M0!¯! •baudclkapb_pclkã3 3 ètxrxÖdefaultüòüokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uart þ¶ N0!³!¡•baudclkapb_pclkã3 3 ètxrx×defaultüò üdisabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uart þ· O0!·!¢•baudclkapb_pclkã~ ~ ètxrxØdefaultüò üdisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uart þ¸ P0!»!£•baudclkapb_pclkã~ ~ ètxrxÙdefaultüò üdisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uart þ¹ Q0!¿!¤•baudclkapb_pclkã~ ~ètxrxÚdefaultüòüokayserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uart þº R0!Ã!¥•baudclkapb_pclkãètxrxÛdefaultüò üdisabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uart þ» S0!Ç!¦•baudclkapb_pclkã  ètxrxÜdefaultüò üdisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uart þ¼ T0!Ë!§•baudclkapb_pclkã  ètxrxÝdefaultüò üdisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½0!L!K •pwmpclkÞdefault  üdisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½0!L!K •pwmpclkßdefault üokaypwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½ 0!L!K •pwmpclkàdefault  üdisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½00!L!K •pwmpclkádefault  üdisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾0!O!N •pwmpclkâdefault üokayøHpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾0!O!N •pwmpclkãdefault üokaypwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾ 0!O!N •pwmpclkädefault  üdisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾00!O!N •pwmpclkådefault  üdisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿0!R!Q •pwmpclkædefault  üdisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿0!R!Q •pwmpclkçdefault  üdisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿ 0!R!Q •pwmpclkèdefault üokaypwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿00!R!Q •pwmpclkédefault  üdisabledthermal-zonespackage-thermal   .êtripspackage-crit >Á8 J criticalbigcore0-thermal d  .êtripsbigcore0-alert >L JÐpassiveøëbigcore0-crit >Á8 J criticalcooling-mapsmap0 Uë Zÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal d  .êtripsbigcore2-alert >L JÐpassiveøìbigcore2-crit >Á8 J criticalcooling-mapsmap0 Uì Zÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal d  .êtripslittlecore-alert >L JÐpassiveøílittlecore-crit >Á8 J criticalcooling-mapsmap0 Uí0 Zÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal   .êtripscenter-crit >Á8 J criticalgpu-thermal d  .êtripsgpu-alert >L JÐpassiveøîgpu-crit >Á8 J criticalcooling-mapsmap0 Uî Zïÿÿÿÿÿÿÿÿnpu-thermal   .êtripsnpu-crit >Á8 J criticaltsadc@fec00000rockchip,rk3588-tsadc þÀ �0!ž!�•tsadcapb_pclkp!ž€„€ç!V!Wátsadc-apbtsadc iÔÀ € —ð ²ñdefaultsleep ¼üokayøêadc@fec10000rockchip,rk3588-saradc þÁ Ž Ò0!‘!�•saradcapb_pclkç!U ásaradc-apbüokay äòøCi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c þÈ0!ˆ!€ •i2cpclk Códefault+üokay @rtc@51haoyu,hym8563 Q˜(hym8563 Ë defaultô ðtypec-portc@22 fcs,fusb302 " Ë defaultõ þ-connectorusb-c-connector dual USB-C source %�È 1source þ-ports+port@0 endpointªöøport@1 endpointª÷ø'port@2 endpointªøøi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c þÉ0!‰!� •i2cpclk Dùdefault+üokay @audio-codec@1brealtek,rt5616 ¤p!1€»€0!1•mclkøFi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c þÊ0!Š!‚ •i2cpclk Eúdefault+üokayspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spi þË J0!›!–•spiclkapb_pclkã ètxrx ¦ûüdefault+ üdisabledefuse@fecc0000rockchip,rk3588-otp þÌ 0!Œ!‹!�!�•otpapb_pclkphyarbç!§!¦!¨ áotpapbarb+cpu-code@2 id@7 cpu-leakage@17 cpu-leakage@18 cpu-leakage@19 log-leakage@1a gpu-leakage@1b cpu-version@1c  @npu-leakage@28 (codec-leakage@29 )dma-controller@fed10000arm,pl330arm,primecell þÑ@  Z[ „0!p •apb_pclk ›øphy@fed60000rockchip,rk3588-hdptx-phy þÖ 0! !T•refapb˜í8ç!#!!c!d!e!!!""áphyapbinitcmnlaneroplllcpllýüokayøuphy@fed80000rockchip,rk3588-usbdp-phy þØí0!¡!l!Vþ•refclkimmortalpclkutmi(ç! ! ! !!áinitcmnlanepcs_apbpma_apb Eÿ X iµüokay  ‹ žŽ ¬Žø&port+endpoint@0 ªøöendpoint@1 ªøøphy@feda0000rockchip,rk3588-mipi-dcphy þÚ0!ü!¡ •pclkref ç!i!!!jám_phyapbgrfs_phyí üdisabledø€phy@fedb0000rockchip,rk3588-mipi-dcphy þÛ0!ý!¡ •pclkref ç!k!!!lám_phyapbgrfs_phyí üdisabledø�phy@fedc0000rockchip,rk3588-csi-dphy þÜ€0!þ•pclkíç!!áapbphy üdisabledphy@fedc8000rockchip,rk3588-csi-dphy þÜ€€0!ÿ•pclkíç!!áapbphy üdisabledphy@fee00000rockchip,rk3588-naneng-combphy þà0!¨!v!W •refapbpipep!¨€õáíç!<!Cáphyapb º0 Ì üokayø‘phy@fee20000rockchip,rk3588-naneng-combphy þâ0!ª!x!W •refapbpipep!ª€õáíç!>!Eáphyapb º0 Ì üokayø,sram@ff001000 mmio-sram ÿðKÿð+codec-sram@0 € âørcodec-sram@78000 €p âøtpinctrlrockchip,rk3588-pinctrlK +ø gpio@fd8a0000rockchip,gpio-bank ýŠ 0!q!r � ç Y  Ïµ óMicroSD detect [SDMMC_DET_L]Pin 10 [UART0_RX_M0]Pin 08 [UART0_TX_M0/PWM4_M0]Pin 32 [PWM5_M1]USB3 Type-C [CC_INT_L]IR receiver [PWM3_IR_M0]User ButtonøËgpio@fec20000rockchip,gpio-bank þ 0!s!t � ç Y  Ï­ óPin 27 [UART6_RX_M1]Pin 28 [UART6_TX_M1]USB2 Type-A [USB2_PWREN]Pin 15Pin 26Pin 21 [SPI0_MISO_M2]Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]Pin 23 [SPI0_CLK_M2/UART4_TX_M2]Pin 24 [SPI0_CS0_M2/UART7_RX_M2]Pin 22 [SPI0_CS1_M0/UART7_TX_M2]CSI-Pin 14 [MIPI_CAM2_CLKOUT]Headphone detect [HP_DET_L]USB3 Type-C [TYPEC5V_PWREN_H]5V Fan [PWM1_M1]HDMI-in detect [HDMIIRX_DET_L]Pin 05 [I2C8_SCL_M2]Pin 03 [I2C8_SDA_M2]ø?gpio@fec30000rockchip,gpio-bank þà 0!u!v � ç @ Y  Ïù óSPI NOR Flash [FSPI_D0_M1]SPI NOR Flash [FSPI_D1_M1]SPI NOR Flash [FSPI_D2_M1]SPI NOR Flash [FSPI_D3_M1]SPI NOR Flash [FSPI_CLK_M1]SPI NOR Flash [FSPI_CSN0_M1]CSI-Pin 11 [MIPI_CAM2_RESET_L]CSI-Pin 12 [MIPI_CAM2_PDN_L]ø=gpio@fec40000rockchip,gpio-bank þÄ 0!w!x � ç ` Y  Ïå óPin 35 [SPI4_MISO_M1/PWM10_M0]Pin 38 [SPI4_MOSI_M1]Pin 40 [SPI4_CLK_M1/UART8_TX_M1]Pin 36 [SPI4_CS0_M1/UART8_RX_M1]Pin 37 [SPI4_CS1_M1]USB3-A #2 [USB3_2_PWREN]DSI-Pin 12 [LCD_RST]Buzzer [PWM8_M0]Pin 33 [PWM9_M0]DSI-Pin 10 [PWM2_M1/LCD_BL]Pin 07Pin 16Pin 18Pin 29 [UART3_TX_M1/PWM12_M0]Pin 31 [UART3_RX_M1/PWM13_M0]Pin 12DSI-Pin 08 [TP_INT_L]DSI-Pin 14 [TP_RST_L]Pin 11 [PWM14_M0]Pin 13 [PWM15_IR_M0]DSI-Pin 06 [I2C5_SCL_M0_TP]DSI-Pin 05 [I2C5_SDA_M0_TP]ø#gpio@fec50000rockchip,gpio-bank þÅ 0!y!z � ç € Y  ÏÔ óM.2 M-Key Slot4 [M2_D_PERST_L]USB3-A #1 [USB3_TYPEC1_PWREN]M.2 M-Key Slot3 [M2_C_PERST_L]M.2 M-Key Slot2 [M2_B_PERST_L]M.2 M-Key Slot1 [M2_A_CLKREQ_L]M.2 M-Key Slot1 [M2_A_PERST_L]øŽpcfg-pull-up øpcfg-pull-down øpcfg-pull-none ø pcfg-pull-none-drv-level-2  ,øpcfg-pull-up-drv-level-1  ,øpcfg-pull-up-drv-level-2  ,øpcfg-pull-none-smt  ;øpcfg-pull-none-drv-level-1-smt  , ;øpcfg-pull-none-drv-level-3-smt  , ;øpcfg-pull-none-drv-level-5-smt  , ;øauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout P øžemmc-bus8€ PøŸemmc-clk Pø emmc-cmd Pø¡emmc-data-strobe Pø¢eth1fspigmac1gpuhdmihdmim0-tx0-cec P ø‚hdmim0-tx0-hpd P øƒhdmim0-tx0-scl Pø„hdmim0-tx0-sda Pø…hdmim0-tx1-hpd P øhdmim1-rx-cec P ø$hdmim1-rx-hpdin P ø%hdmim1-rx-scl P ø&hdmim1-rx-sda P ø'hdmim1-tx1-scl Pøhdmim1-tx1-sda Pøhdmim2-tx1-cec P øi2c0i2c0m2-xfer Pø1i2c1i2c1m0-xfer P  ø¿i2c2i2c2m0-xfer P  øÀi2c3i2c3m0-xfer P  øÁi2c4i2c4m0-xfer P  øÂi2c5i2c5m0-xfer P  øÃi2c6i2c6m0-xfer P  øói2c7i2c7m0-xfer P  øùi2c8i2c8m2-xfer P  øúi2s0i2s0-lrck P ø¦i2s0-mclk P ø§i2s0-sclk P ø¨i2s0-sdi0 P ø©i2s0-sdo0 P øªi2s1i2s1m0-lrck P ø«i2s1m0-sclk P ø¬i2s1m0-sdi0 P ø­i2s1m0-sdi1 P ø®i2s1m0-sdi2 P ø¯i2s1m0-sdi3 P ø°i2s1m0-sdo0 P  ø±i2s1m0-sdo1 P  ø²i2s1m0-sdo2 P  ø³i2s1m0-sdo3 P  ø´i2s2i2s2m1-lrck P øµi2s2m1-sclk P  ø¶i2s2m1-sdi P  ø·i2s2m1-sdo P  ø¸i2s3i2s3-lrck P ø¹i2s3-sclk P øºi2s3-sdi P ø»i2s3-sdo P ø¼jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp P      øÌpmupwm0pwm0m0-pins P ø5pwm1pwm1m1-pins P  ø6pwm2pwm2m1-pins P  ø7pwm3pwm3m0-pins P ø8pwm4pwm4m1-pins P  øÞpwm5pwm5m1-pins P  øßpwm6pwm6m0-pins P  øàpwm7pwm7m0-pins P  øápwm8pwm8m0-pins P  øâpwm9pwm9m0-pins P  øãpwm10pwm10m0-pins P  øäpwm11pwm11m0-pins P  øåpwm12pwm12m0-pins P  øæpwm13pwm13m0-pins P  øçpwm14pwm14m0-pins P  øèpwm15pwm15m0-pins P  øérefclksatasata0sata1sata2sdiosdiom1-pins` P ø�sdmmcsdmmc-bus4@ Pøšsdmmc-clk Pø—sdmmc-cmd Pø˜sdmmc-det Pø™sd-s0-pwr PøBspdif0spdif0m0-tx P ø½spdif1spdif1m0-tx P ø¾spi0spi0m2-pins0 P   øÅspi0m2-cs0 P øÄspi1spi1m1-pins0 PøÈspi1m1-cs0 PøÆspi1m1-cs1 PøÇspi2spi2m2-pins0 P øÊspi2m2-cs0 P øÉspi3spi3m1-pins0 P øÔspi3m1-cs0 PøÒspi3m1-cs1 PøÓspi4spi4m1-pins0 Pøüspi4m1-cs0 Pøûtsadctsadc-shut-org P øðuart0uart0m0-xfer Pø4uart1uart1m1-xfer P  øÕuart2uart2m0-xfer P  øÖuart3uart3m1-xfer P  ø×uart4uart4m2-xfer P  øØuart5uart5m1-xfer P  øÙuart6uart6m1-xfer P  øÚuart7uart7m2-xfer P  øÛuart8uart8m1-xfer P  øÜuart9uart9m1-xfer P  øÝvopbt656gpio-functsadc-gpio-func P øñeth0gmac0gpio-ledsled-sys-pin P ø>led-usr-pin P ø@hym8563rtc-int Pøôpciepcie2-2-rst P ø’pcie2-0-rst P  ø1pcie2-1-rst P ø�pcie3x2-rst P  ø.pcie3x4-rst P ø+audioheadphone-detect P øDgpio-keykey1-pin PøJhdmirxhdmirx-5v-detection Pø(usbvcc-5v0-host20-en P øMvcc-5v0-host30p1-en P øNvcc-5v0-host30p2-en P øOusb-typecusbc0-int Pøõtypec-5v-pwr-en P øPhdmi1-soundsimple-audio-card²i2sË€åhdmi1 üdisabledsimple-audio-card,codecsimple-audio-card,cpuusb@fc400000rockchip,rk3588-dwc3snps,dwc3 ü@@ Ý0!—!–!••ref_clksuspend_clkbus_clkÇhost ÏÔusb2-phyusb3-phy Þutmi_wide¡"ç!Sî6Wxüokaysyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon ý[€ø<syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon ý\ø;syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon ý\À@ø:syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ý]@@+ø9usb2phy@4000rockchip,rk3588-usb2phy @˜0! •phyclk (usb480m_phy1 Šç!n!áphyapbüokayø8otg-portíüokayøøsyscon@fd5e4000$rockchip,rk3588-hdptxphy-grfsyscon ý^@ø7spdif-tx@fddb8000,rockchip,rk3588-spdifrockchip,rk3568-spdif ýÛ€�!p!ú •mclkhclk0!þ!ùètxã~ Æ¡"¤ üdisabledi2s@fddc8000rockchip,rk3588-i2s-tdm ýÜ€ ¼0!ñ!ñ!î•mclk_txmclk_rxhclkp!ï�!ãètx¡"ç!ºátx-m¤ üdisabledspdif-tx@fdde8000,rockchip,rk3588-spdifrockchip,rk3568-spdif ýÞ€�!p!F •mclkhclk0!I!Eètxã~ Å¡"¤ üdisabledi2s@fddf4000rockchip,rk3588-i2s-tdm ýß@ º0!9!9!?•mclk_txmclk_rxhclkp!6�!ãètx¡"ç!Úátx-m¤üokayøi2s@fddf8000rockchip,rk3588-i2s-tdm ý߀ »0!+!+!'•mclk_txmclk_rxhclkp!(�!ãèrx¡"ç!Çárx-m¤üokayi2s@fde00000rockchip,rk3588-i2s-tdm ýà ¾0!&!&!"•mclk_txmclk_rxhclkp!#�!ãèrx¡"ç!îárx-m¤ üdisableddp@fde60000rockchip,rk3588-dp ýæ@ ¢p!¸€ô$(0!Ø!¸!Ü!ñ!ü•apbauxhdcpi2sspdifÏ¡"ç!¶¤ üdisabledports+port@0 port@1 hdmi@fdea0000rockchip,rk3588-dw-hdmi-qp ýê00!!!!9!S!Í•pclkearcrefaudhdphclk_vo1P ­®¯°i;avpcecearcmainhpdÏvdefault¡"ç!Ð!1árefhdpxµz¤üokayøports+port@0 endpointª ø}port@1 endpointª!øLedp@fded0000rockchip,rk3588-edp ýí0!!•dppclk ¤ÏvÔdp¡"ç!×!Öádpapbz üdisabledports+port@0 port@1 hdmi_receiver@fdee0000.rockchip,rk3588-hdmirx-ctrlersnps,dw-hdmi-rx ýî`0 ±²³ ;cechdmidma80! !!Ÿ! ! !!!Í3•aclkaudiocr_parapclkrefhclk_s_hdmirxhclk_vo1 ^"¡" ç!Ñ!Ò!Ó!”áaxiapbrefbiuxozüokay l#$%&'(defaultpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+Å00!@!E!;!J!O!t)•aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP ;syspmcmsglegacyerrÏà`ó))))!*)‹3ÏŒ Ôpcie-phy¡""TKððð ð à @0 @@þð=dbiapbconfigç!&!+ ápwrpipeüokaydefault+ =ŽI,legacy-interrupt-controllerYÏ  ø)pcie-ep@fe150000rockchip,rk3588-pcie-epP @ @þ @ @0=dbidbi2apbaddr_spaceatu00!@!E!;!J!O!t)•aclk_mstaclk_slvaclk_dbipclkauxpipe�  +;syspmcmsglegacyerrdma0dma1dma2dma33ÏŒ Ôpcie-phy¡""ç!&!+ ápwrpipe üdisabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+Å00!A!F!<!K!P!u)•aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP ÿþ;syspmcmsglegacyerrÏà`ó----!*)‹3ÏŒ Ôpcie-phy¡""TKñññ ñ à @ @@0 @@@þñ=dbiapbconfigç!'!, ápwrpipeüokaydefault. =Ž I/legacy-interrupt-controllerYÏ  ÿø-pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcieÅ /00!B!G!=!L!Q!¯)•aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP óòñðï;syspmcmsglegacyerrÏà`ó0000! Š ) ‹ 3ÏŒ Ôpcie-phy¡""TKòòò ò à € €@0 @€@þò=dbiapbconfigç!(!- ápwrpipe+üokaydefault1 =Ž I2legacy-interrupt-controllerYÏ  ðø0ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a þ  ãâ;macirqeth_wake_irq(0!6!7!X!]!40•stmmacethclk_mac_refpclk_macaclk_macptp_ref¡"!ç!# ástmmacethxn03� 4³5Æ üdisabledmdiosnps,dwmac-mdio+stmmac-axi-configÏÙéø3rx-queues-configùø4queue0queue1tx-queues-configø5queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci þ" (0!c!`!f!U!p•satapmaliverxoobrefasic%+ üdisabledsata-port@0 7@Ï6 Ôsata-phyD S phy@fed70000rockchip,rk3588-hdptx-phy þ× 0! !U•refapb˜í8ç!&!!f!g!h!$!%"áphyapbinitcmnlaneroplllcpll7üokayøvphy@fed90000rockchip,rk3588-usbdp-phy þÙí0!¡!m!W8•refclkimmortalpclkutmi(ç!!!!!áinitcmnlanepcs_apbpma_apb E9 X i:µüokayøphy@fee10000rockchip,rk3588-naneng-combphy þá0!©!w!W •refapbpipep!©€õáíç!=!Dáphyapb º0 Ì;üokayø6phy@fee80000rockchip,rk3588-pcie3-phy þèí0!y•pclkç!Háphy º0 v<üokay ‡øŒopp-table-cluster0operating-points-v2 ’ø opp-1008000000 �<Ü ¤ L¸ L¸~𠲜@opp-1200000000 �G†Œ ¤ ß4 ß4~𠲜@opp-1416000000 �Tfr ¤ ¢„ ¢„~𠲜@ Ãopp-1608000000 �_Ø" ¤ øP øP~𠲜@opp-1800000000 �kIÒ ¤~ð~ð~𠲜@opp-table-cluster1operating-points-v2 ’øopp-1200000000 �G†Œ ¤ L¸ L¸B@ ²œ@opp-1416000000 �Tfr ¤  B@ ²œ@opp-1608000000 �_Ø" ¤ ¢„ ¢„B@ ²œ@opp-1800000000 �kIÒ ¤ øP øPB@ ²œ@opp-2016000000 �x)¸ ¤HHB@ ²œ@opp-2208000000 �ƒ›h ¤llB@ ²œ@opp-2400000000 ��  ¤B@B@B@ ²œ@opp-table-cluster2operating-points-v2 ’øopp-1200000000 �G†Œ ¤ L¸ L¸B@ ²œ@opp-1416000000 �Tfr ¤  B@ ²œ@opp-1608000000 �_Ø" ¤ ¢„ ¢„B@ ²œ@opp-1800000000 �kIÒ ¤ øP øPB@ ²œ@opp-2016000000 �x)¸ ¤HHB@ ²œ@opp-2208000000 �ƒ›h ¤llB@ ²œ@opp-2400000000 ��  ¤B@B@B@ ²œ@opp-table-gpuoperating-points-v2ø#opp-300000000 �ᣠ¤ L¸ L¸ øPopp-400000000 �ׄ ¤ L¸ L¸ øPopp-500000000 �Íe ¤ L¸ L¸ øPopp-600000000 �#ÃF ¤ L¸ L¸ øPopp-700000000 �)¹' ¤ ®` ®` øPopp-800000000 �/¯ ¤ q° q° øPopp-900000000 �5¤é ¤ 5 5 øPopp-1000000000 �;šÊ ¤ øP øP øPchosen Ïserial2:1500000n8leds gpio-ledsled-0 Û ±heartbeat C= áheartbeatdefault>led-1 Û ±indicator C?default@regulator-vcc-4v0-sysregulator-fixed Evcc_4v0_sysThz= ’= ¿Aø2regulator-vcc-3v3-pcie20regulator-fixedEvcc_3v3_pcie20Thz2Z ’2Z ¿£ø“regulator-vcc-3v3-sd-s0regulator-fixed CŽdefaultBh’2Z z2Z Evcc_3v3_sd_s0¿£ø›regulator-vcc-1v1-nldo-s3regulator-fixedEvcc-1v1-nldo-s3ThzÈà’Èà¿2øÑadc-key-recovery adc-keys ÷Cbuttonsw@.dbutton-recovery Recovery<hGBhanalog-soundsimple-audio-carddefaultD²i2s a?Ëårealtek,rt5616-codecN€HeadphonesHPOLHeadphonesHPORMIC1Microphone JackMicrophone Jackmicbias10šHeadphoneHeadphonesMicrophoneMicrophone Jacksimple-audio-card,cpuEsimple-audio-card,codecFpwm-beeper pwm-beeper´G¿ôÉH¡ pwm-fanpwm-fanÊÎ2Px ÜÝGÉIÃPgpio-keys gpio-keysdefaultJbutton-userè2 CË User Button< ðhdmi0-conhdmi-connectoraportendpointªKø‡hdmi1-conhdmi-connectoraportendpointªLø!ir-receivergpio-ir-receiver CËregulator-vcc-12v-dcinregulator-fixed Evcc_12v_dcinThz·’·øAregulator-vcc-3v3-m2-aregulator-fixed Evcc_3v3_m2_aThz2Z ’2Z ¿Aø,regulator-vcc-3v3-m2-bregulator-fixed Evcc_3v3_m2_bThz2Z ’2Z ¿Aø2regulator-vcc-3v3-m2-cregulator-fixed Evcc_3v3_m2_cThz2Z ’2Z ¿Aø/regulator-vcc-3v3-m2-dregulator-fixed Evcc_3v3_m2_dThz2Z ’2Z ¿Aø�regulator-vcc-5v0-sysregulator-fixed Evcc_5v0_sysThzLK@’LK@¿AøGregulator-vcc-5v0-host-20regulator-fixedú C?defaultMEvcc_5v0_host_20zLK@’LK@¿Gø.regulator-vcc-5v0-host-30-p1regulator-fixedú CŽdefaultNEvcc_5v0_host_30_p1zLK@’LK@¿Gøregulator-vcc-5v0-host-30-p2regulator-fixedú C#defaultOEvcc_5v0_host_30_p2zLK@’LK@¿Gø/regulator-vbus-5v0-typecregulator-fixedú C?defaultPEvbus_5v0_typeczLK@’LK@¿Gø- compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclockscpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesno-mapalloc-rangesalignmentassigned-clocksassigned-clock-ratesclock-namespower-domainsmali-supplysram-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkusb-role-switchremote-endpointsnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellsdomain-supplypm_qosreg-namesiommusnpu-supplysramrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsrockchip,vo-grfbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapiommu-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplysupports-cqemmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdnon-removablerockchip,trcm-sync-tx-onlydma-noncoherentmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplywakeup-sourcevbus-supplydata-rolelabelpower-rolesource-pdostry-power-rolebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfmode-switchorientation-switchsbu1-dc-gpiossbu2-dc-gpiosrockchip,pipe-grfrockchip,pipe-phy-grfpoolgpio-rangesgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsmemory-regionhpd-gpiosrockchip,phy-grfdata-lanesopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolorlinux,default-triggerio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codepress-threshold-microvoltsimple-audio-card,hp-det-gpiossimple-audio-card,routingsimple-audio-card,widgetsamp-supplybeeper-hzpwmscooling-levelsfan-supplydebounce-intervalenable-active-high