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gpu-leakage@219!log-leakage@229"bigcore-tsadc-trim@249$ | ½Õlitcore-tsadc-trim@269& | ½Öddr-tsadc-trim@289( | ½×npu-tsadc-trim@2a9* | ½Øgpu-tsadc-trim@2c9, | ½Ùsoc-tsadc-trim@649d | ½Ôsai@2a600000rockchip,rk3576-sai9*`  »^@A )mclkhclk·114txrx×% åìmhødefault(Ž��‘’“”•–—TeSAI0 Êdisabledsai@2a610000rockchip,rk3576-sai9*a  ¼^GH )mclkhclk·114txrx×% åìmhødefault˜™š›œ�žTeSAI1 Êdisabledsai@2a620000rockchip,rk3576-sai9*b  ½^JK )mclkhclk·ii4txrx×% åìmhødefaultŸ ¡¢TeSAI2 Êdisabledsai@2a630000rockchip,rk3576-sai9*c  ¾^MN )mclkhclk·ii4txrx×% åìmhødefault£¤¥¦TeSAI3 Êdisabledsai@2a640000rockchip,rk3576-sai9*d  ¿^PQ )mclkhclk·aa4txrx×% åìmhødefault§¨©ªTeSAI4 Êdisabledinterrupt-controller@2a701000 arm,gic-400@9*p*p *p@*p`   ÿ7+½dma-controller@2ab90000arm,pl330arm,primecell9*¹@ �^à )apb_pclk ! ˜½1dma-controller@2abb0000arm,pl330arm,primecell9*»@ �^Ä )apb_pclk "# ˜½idma-controller@2abd0000arm,pl330arm,primecell9*½@ �^Å )apb_pclk $% ˜½ai2c@2ac40000(rockchip,rk3576-i2crockchip,rk3399-i2c9*Ä^th )i2cpclk  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ïvdd_gpu_s0 þ0Ô½Yregulator-state-mem  , øPdcdc-reg6 } ‘ ïvddq_ddr_s0regulator-state-mem dcdc-reg7 } ‘ ¿dp × 5 ïvdd_logic_s0regulator-state-mem dcdc-reg8 } ‘ ¿w@ ×w@ ïvcc_1v8_s3½�regulator-state-mem H ,w@dcdc-reg9 } ‘ ïvdd2_ddr_s3regulator-state-mem Hdcdc-reg10 } ‘ ¿dp ×O€ ïvdd_ddr_s0regulator-state-mem pldo-reg1 } ‘ ¿w@ ×w@ ïvcca_1v8_s0regulator-state-mem pldo-reg2 } ‘ ¿w@ ×w@ ïvcca1v8_pldo2_s0regulator-state-mem pldo-reg3 } ‘ ¿O€ ×O€ ïvdda_1v2_s0regulator-state-mem pldo-reg4 } ‘ ¿2Z  ×2Z  ïvcca_3v3_s0regulator-state-mem pldo-reg5 } ‘ ¿w@ ×2Z  ïvccio_sd_s0½‚regulator-state-mem pldo-reg6 } ‘ ¿w@ ×w@ ïvcca1v8_pldo6_s3regulator-state-mem H ,w@nldo-reg1 } ‘ ¿ q° × q° ïvdd_0v75_s3regulator-state-mem H , q°nldo-reg2 } ‘ ¿ øP × øP ïvdda_ddr_pll_s0regulator-state-mem nldo-reg3 } ‘ ¿ Ç| × Ç| ïvdda0v75_hdmi_s0regulator-state-mem nldo-reg4 } ‘ ¿ øP × øP ïvdda_0v85_s0regulator-state-mem nldo-reg5 } ‘ ¿ q° × q° ïvdda_0v75_s0regulator-state-mem i2c@2ac50000(rockchip,rk3576-i2crockchip,rk3399-i2c9*Å^ui )i2cpclk  Zødefault´+Êokayrtc@51haoyu,hym85639Q hym8563 ¬ ødefaultµ `i2c@2ac60000(rockchip,rk3576-i2crockchip,rk3399-i2c9*Æ^vj )i2cpclk  [ødefault¶+ Êdisabledi2c@2ac70000(rockchip,rk3576-i2crockchip,rk3399-i2c9*Ç^wk )i2cpclk  \ødefault·+ Êdisabledi2c@2ac80000(rockchip,rk3576-i2crockchip,rk3399-i2c9*È^xl )i2cpclk  ]ødefault¸+ Êdisabledi2c@2ac90000(rockchip,rk3576-i2crockchip,rk3399-i2c9*É^ym )i2cpclk  ^ødefault¹+Êokayeeprom@50belling,bl24c16fatmel,24c169P n w q�i2c@2aca0000(rockchip,rk3576-i2crockchip,rk3399-i2c9*Ê^zn )i2cpclk  _ødefaultº+ Êdisabledi2c@2acb0000(rockchip,rk3576-i2crockchip,rk3399-i2c9*Ë^{o )i2cpclk  `ødefault»+ Êdisabledtimer@2acc0000,rockchip,rk3576-timerrockchip,rk3288-timer9*Ì ^§ª )pclktimer  -watchdog@2ace0000 rockchip,rk3576-wdtsnps,dw-wdt9*Î^¢¡ )tclkpclk  (spi@2acf0000(rockchip,rk3576-spirockchip,rk3066-spi9*Ï^œ—)spiclkapb_pclk·114txrx  t �ødefault ¼½¾+ Êdisabledspi@2ad00000(rockchip,rk3576-spirockchip,rk3066-spi9*Ð^�˜)spiclkapb_pclk·114txrx  u �ødefault ¿ÀÁ+ Êdisabledspi@2ad10000(rockchip,rk3576-spirockchip,rk3066-spi9*Ñ^ž™)spiclkapb_pclk·ii4txrx  v �ødefault ÂÃÄ+ Êdisabledspi@2ad20000(rockchip,rk3576-spirockchip,rk3066-spi9*Ò^Ÿš)spiclkapb_pclk·ii4txrx  w �ødefault ÅÆÇ+ Êdisabledspi@2ad30000(rockchip,rk3576-spirockchip,rk3066-spi9*Ó^ ›)spiclkapb_pclk·a a 4txrx  x �ødefault ÈÉÊ+ Êdisabledserial@2ad40000&rockchip,rk3576-uartsnps,dw-apb-uart9*Ô ª^Œ�)baudclkapb_pclk·114txrx  LËødefaultÊokayserial@2ad50000&rockchip,rk3576-uartsnps,dw-apb-uart9*Õ ª^�‚)baudclkapb_pclk·1 1 4txrx  NødefaultÌ Êdisabledserial@2ad60000&rockchip,rk3576-uartsnps,dw-apb-uart9*Ö ª^Žƒ)baudclkapb_pclk·1 1 4txrx  OÍødefault Êdisabledserial@2ad70000&rockchip,rk3576-uartsnps,dw-apb-uart9*× ª^�„)baudclkapb_pclk·i i 4txrx  PÎødefault Êdisabledserial@2ad80000&rockchip,rk3576-uartsnps,dw-apb-uart9*Ø ª^�…)baudclkapb_pclk·i i 4txrx  QÏødefault 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9serial10serial11spi0spi1spi2spi3spi4ethernet0mmc0clock-frequencyclock-output-names#clock-cellscpudevice_typeregenable-methodcapacity-dmips-mhzclocksoperating-points-v2dynamic-power-coefficientcpu-idle-states#cooling-cellscpu-supplyphandleentry-methodarm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stopopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmemsimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-dairockchip,grfrangesgpio-controllergpio-rangesinterruptsinterrupt-controller#gpio-cells#interrupt-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsinterrupt-affinitypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereg-namesbus-rangeclock-namesdma-coherentinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-ib-windowsnum-viewportnum-ob-windowsnum-lanesphysphy-namespower-domainsresetsreset-namespinctrl-namespinctrl-0reset-gpiosvpcie3v3-supplydr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,parkmode-disable-hs-quirksnps,parkmode-disable-ss-quirksnps,dis_rxdet_inp3_quirk#phy-cellsphy-supply#reset-cellsassigned-clocksassigned-clock-parentsassigned-clock-ratesreg-shiftreg-io-widthdmas#power-domain-cellspm_qosmali-supplyiommussramrockchip,disable-mmu-reset#iommu-cellsrockchip,pmuremote-endpointdma-namesrockchip,sai-rx-route#sound-dai-cellssound-name-prefixrockchip,sai-tx-routerockchip,vo-grfrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-deassert-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplysupports-cqespi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthvcc-supplybitsarm,pl330-periph-burst#dma-cellssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplyfunctionregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendwakeup-sourcepagesizeread-onlynum-cs#io-channel-cells#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritynvmem-cellsnvmem-cell-namesrockchip,pipe-grfrockchip,pipe-phy-grfrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfpoolstdout-pathradio-typeshutdown-gpioscolordefault-statelinux,default-triggervin-supplyenable-active-highstartup-delay-us