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Ådisabledsata@2a250000'rockchip,rk3576-dwc-ahcisnps,dwc-ahci4*%Y$satapmaliverxoob Ò% Ã' Èsata-phy�0 Ådisabledufshc@2a2d0000rockchip,rk3576-ufshcP4*-+&ð&À*."hcimphyhci_grfmphy_grfhci_apb YIC×Ù$corepclkpclk_mphyref_out Ø0; iÒ%jtu\default(à!"$Æçbiusysufsgrfmphy  v Ådisabledspi@2a300000 rockchip,sfc4*0@ ÿY*+$clk_sfchclk_sfcÒ%+ Ådisabledmmc@2a310000rockchip,rk3576-dw-mshc4*1@Y)($biuciu“ ûž ëÂ\defaultjwxyz{Ò%à çresetÅokay¬´»Å×èó |mmc@2a320000rockchip,rk3576-dw-mshc4*2@Y#"$biuciu“ üž ë j}~\defaultÒ%à çreset Ådisabledmmc@2a3300000rockchip,rk3576-dwcmshcrockchip,rk3588-dwcmshc4*3 üýù G ëÂn6 ëÂ(Yùúûüý$corebusaxiblocktimer ýž ëÂj€�‚ƒ„\defaultÒ%(àéêëìíçcorebusaxiblocktimer Åokay»¬  ! / > Xspi@2a340000 rockchip,sfc4*4@ þY÷ø$clk_sfchclk_sfcÒ%+ Ådisabledrng@2a410000rockchip,rk3576-rng4*AY µà¨otp@2a580000rockchip,rk3576-otp4*X+Y1$otpapb_pclkphy઩çotpapbcpu-code@24cpu-version@54 rid@a4 cpub-leakage@1e4cpul-leakage@1f4npu-leakage@204 gpu-leakage@214!log-leakage@224"bigcore-tsadc-trim@244$ r ¸Îlitcore-tsadc-trim@264& r ¸Ïddr-tsadc-trim@284( r ¸Ðnpu-tsadc-trim@2a4* r ¸Ñgpu-tsadc-trim@2c4, r ¸Òsoc-tsadc-trim@644d r ¸Ísai@2a600000rockchip,rk3576-sai4*` »Y@A $mclkhclk‹,,txrxÒ% àçmh\default(j…†‡ˆ‰Š‹Œ�Ž(9SAI0 Ådisabledsai@2a610000rockchip,rk3576-sai4*a ¼YGH $mclkhclk‹,,txrxÒ% àçmh\defaultj��‘’“”•(9SAI1 Ådisabledsai@2a620000rockchip,rk3576-sai4*b ½YJK $mclkhclk‹ddtxrxÒ% àçmh\defaultj–—˜™(9SAI2 Ådisabledsai@2a630000rockchip,rk3576-sai4*c ¾YMN $mclkhclk‹ddtxrxÒ% àçmh\defaultjš›œ�(9SAI3 Ådisabledsai@2a640000rockchip,rk3576-sai4*d ¿YPQ $mclkhclk‹\\txrxÒ% àçmh\defaultjžŸ ¡(9SAI4 Ådisabledinterrupt-controller@2a701000 arm,gic-400@4*p*p *p@*p`  ÿ2+¸dma-controller@2ab90000arm,pl330arm,primecell4*¹@ wYà $apb_pclk ! ޏ,dma-controller@2abb0000arm,pl330arm,primecell4*»@ wYÄ $apb_pclk"# ޏddma-controller@2abd0000arm,pl330arm,primecell4*½@ wYÅ $apb_pclk$% ޏ\i2c@2ac40000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÄYth $i2cpclk Y\defaultj¢+Åokaypmic@23rockchip,rk8064# £ê&\defaultj¤¥¦§ ™ ±¨ ½¨ ɨ Õ¨ á¨ í¨ ù¨ ¨ ¨ ¨ *© 7¨ Dª Qª ^¨dvs1-null-pins™gpio_pwrctrl1 jpin_fun0¸¥dvs2-null-pins™gpio_pwrctrl2 jpin_fun0¸¦dvs3-null-pins™gpio_pwrctrl3 jpin_fun0¸§dvs1-slp-pins™gpio_pwrctrl1 jpin_fun1dvs1-pwrdn-pins™gpio_pwrctrl1 jpin_fun2dvs1-rst-pins™gpio_pwrctrl1 jpin_fun3dvs2-slp-pins™gpio_pwrctrl2 jpin_fun1dvs2-pwrdn-pins™gpio_pwrctrl2 jpin_fun2dvs2-rst-pins™gpio_pwrctrl2 jpin_fun3dvs2-dvs-pins™gpio_pwrctrl2 jpin_fun4dvs2-gpio-pins™gpio_pwrctrl2 jpin_fun5dvs3-slp-pins™gpio_pwrctrl3 jpin_fun1dvs3-pwrdn-pins™gpio_pwrctrl3 jpin_fun2dvs3-rst-pins™gpio_pwrctrl3 jpin_fun3dvs3-dvs-pins™gpio_pwrctrl3 jpin_fun4dvs3-gpio-pins™gpio_pwrctrl3 jpin_fun5regulatorsdcdc-reg1 s ‡ ™dp ±~ð É0Ô Þvdd_cpu_big_s0 í�¸regulator-state-mem dcdc-reg2 ‡ ™dp ±~ð É0Ô Þvdd_npu_s0 í�regulator-state-mem dcdc-reg3 s ‡ ™dp ±~ð É0Ô Þvdd_cpu_lit_s0¸ regulator-state-mem  " q°dcdc-reg4 s ‡ ™2Z  ±2Z  Þvcc_3v3_s3¸æregulator-state-mem > "2Z dcdc-reg5 ‡ ™dp ± »  É0Ô Þvdd_gpu_s0 í�¸Tregulator-state-mem  " øPdcdc-reg6 s ‡ Þvddq_ddr_s0regulator-state-mem dcdc-reg7 s ‡ ™dp ± 5 Þvdd_logic_s0regulator-state-mem dcdc-reg8 s ‡ ™w@ ±w@ Þvcc_1v8_s3¸äregulator-state-mem > "w@dcdc-reg9 s ‡ Þvdd2_ddr_s3regulator-state-mem >dcdc-reg10 s ‡ ™dp ±O€ Þvdd_ddr_s0regulator-state-mem pldo-reg1 s ‡ ™w@ ±w@ Þvcca_1v8_s0¸Ìregulator-state-mem pldo-reg2 s ‡ ™w@ ±w@ Þvcca1v8_pldo2_s0regulator-state-mem pldo-reg3 s ‡ ™O€ ±O€ Þvdda_1v2_s0regulator-state-mem pldo-reg4 s ‡ ™2Z  ±2Z  Þvcca_3v3_s0regulator-state-mem pldo-reg5 s ‡ ™w@ ±2Z  Þvccio_sd_s0¸|regulator-state-mem pldo-reg6 s ‡ ™w@ ±w@ Þvcca1v8_pldo6_s3regulator-state-mem > "w@nldo-reg1 s ‡ ™ q° ± q° Þvdd_0v75_s3regulator-state-mem > " q°nldo-reg2 s ‡ ™ øP ± øP Þvdda_ddr_pll_s0regulator-state-mem nldo-reg3 s ‡ ™ Ç| ± Ç| Þvdda0v75_hdmi_s0regulator-state-mem nldo-reg4 s ‡ ™ øP ± øP Þvdda_0v85_s0regulator-state-mem nldo-reg5 s ‡ ™ q° ± q° Þvdda_0v75_s0regulator-state-mem i2c@2ac50000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÅYui $i2cpclk Z\defaultj«+Åokayrtc@51haoyu,hym85634Qhym8563\defaultj¬ £ Vi2c@2ac60000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÆYvj $i2cpclk [\defaultj­+ Ådisabledi2c@2ac70000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÇYwk $i2cpclk \\defaultj®+ Ådisabledi2c@2ac80000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÈYxl $i2cpclk ]\defaultj¯+ Ådisabledi2c@2ac90000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÉYym $i2cpclk ^\defaultj°+ Ådisabledi2c@2aca0000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ÊYzn $i2cpclk _\defaultj±+ Ådisabledi2c@2acb0000(rockchip,rk3576-i2crockchip,rk3399-i2c4*ËY{o $i2cpclk `\defaultj²+ Ådisabledtimer@2acc0000,rockchip,rk3576-timerrockchip,rk3288-timer4*Ì Y§ª $pclktimer -watchdog@2ace0000 rockchip,rk3576-wdtsnps,dw-wdt4*ÎY¢¡ $tclkpclk (spi@2acf0000(rockchip,rk3576-spirockchip,rk3066-spi4*ÏYœ—$spiclkapb_pclk‹,,txrx t d\default j³´µ+ Ådisabledspi@2ad00000(rockchip,rk3576-spirockchip,rk3066-spi4*ÐY�˜$spiclkapb_pclk‹,,txrx u d\default j¶·¸+ Ådisabledspi@2ad10000(rockchip,rk3576-spirockchip,rk3066-spi4*ÑYž™$spiclkapb_pclk‹ddtxrx v d\default j¹º»+ Ådisabledspi@2ad20000(rockchip,rk3576-spirockchip,rk3066-spi4*ÒYŸš$spiclkapb_pclk‹ddtxrx w d\default j¼½¾+ Ådisabledspi@2ad30000(rockchip,rk3576-spirockchip,rk3066-spi4*ÓY ›$spiclkapb_pclk‹\ \ txrx x d\default j¿ÀÁ+ Ådisabledserial@2ad40000&rockchip,rk3576-uartsnps,dw-apb-uart4*Ôt~YŒ�$baudclkapb_pclk‹,,txrx LjÂ\defaultÅokayserial@2ad50000&rockchip,rk3576-uartsnps,dw-apb-uart4*Õt~Y�‚$baudclkapb_pclk‹, , txrx N\defaultjà Ådisabledserial@2ad60000&rockchip,rk3576-uartsnps,dw-apb-uart4*Öt~YŽƒ$baudclkapb_pclk‹, , txrx OjÄ\default Ådisabledserial@2ad70000&rockchip,rk3576-uartsnps,dw-apb-uart4*×t~Y�„$baudclkapb_pclk‹d d txrx PjÅÆ\defaultÅokayserial@2ad80000&rockchip,rk3576-uartsnps,dw-apb-uart4*Øt~Y�…$baudclkapb_pclk‹d d txrx QjÇ\default Ådisabledserial@2ad90000&rockchip,rk3576-uartsnps,dw-apb-uart4*Ùt~Y‘†$baudclkapb_pclk‹d dtxrx RjÈ\defaultÅokayserial@2ada0000&rockchip,rk3576-uartsnps,dw-apb-uart4*Út~Y’‡$baudclkapb_pclk‹\\txrx SjÉ\default Ådisabledserial@2adb0000&rockchip,rk3576-uartsnps,dw-apb-uart4*Ût~Y“ˆ$baudclkapb_pclk‹\\ txrx TjÊ\default Ådisabledserial@2adc0000&rockchip,rk3576-uartsnps,dw-apb-uart4*Üt~Y”‰$baudclkapb_pclk‹\ \ txrx UjË\default Ådisabledadc@2ae00000.rockchip,rk3576-saradcrockchip,rk3588-saradc4*àY~}$saradcapb_pclk |àH çsaradc-apb kÅokay }̸àtsadc@2ae70000rockchip,rk3576-tsadc4*ç {Y€$tsadcapb_pclk €G„€àJKçtsadc-apbtsadc ‰ ŸÔÀ ¶ Í+¸sensor@04 èÍ ôtrimsensor@14 èÎ ôtrimsensor@24 èÏ ôtrimsensor@34 èÐ ôtrimsensor@44 èÑ ôtrimsensor@54 èÒ ôtrimi2c@2ae80000(rockchip,rk3576-i2crockchip,rk3399-i2c4*èY|p $i2cpclk a\defaultjÓ+ Ådisabledserial@2afc0000&rockchip,rk3576-uartsnps,dw-apb-uart4*üt~Y•Š$baudclkapb_pclk‹\\ V\defaultjÔ Ådisabledserial@2afd0000&rockchip,rk3576-uartsnps,dw-apb-uart4*ýt~Y–‹$baudclkapb_pclk‹\\ W\defaultjÕ Ådisabledphy@2b020000rockchip,rk3576-mipi-dcphy4+YÐ $pclkref ༭®½çm_phyapbgrfs_phyÖÖ Ådisabled¸]phy@2b050000rockchip,rk3576-naneng-combphy4+Y95 $refapbpipe 9Gõáॡçphyapb × Ø Ådisabled¸$phy@2b060000rockchip,rk3576-naneng-combphy4+Y:6  $refapbpipe :Gõáণçphyapb × Ù Ådisabled¸'phy@2b010000rockchip,rk3576-usbdp-phy4+YÕÓÚ$refclkimmortalpclkutmi(ูº»·çinitcmnlanepcs_apbpma_apb -Û @Ü QÝaÞ Ådisabled¸)hdmiphy@2b0000004rockchip,rk3576-hdptx-phyrockchip,rk3588-hdptx-phy4+ Y!$refapb à¬ÂÃÄçapbinitcmnlaneÖßÅokay¸Wsram@3ff88000 mmio-sram4?ø€€ã?ø€€+rkvdec-sram@04€ g¸Vscmi-shmem@4010f000arm,scmi-shmem4@ð¸chosen lserial0:1500000n8adc-keys-0 adc-keys xà „buttons •w@ ¯dbutton-maskrom ½Maskrom Ã� ÎBhadc-keys-1 adc-keys xà „buttons •w@ ¯dbutton-recovery ½Recovery Ãh ÎBhhdmi-conhdmi-connector/aportendpointøá¸cregulator-vbus5v0-typecregulator-fixed è û£\defaultjâ Þvbus5v0_typec ™LK@ ±LK@ ãregulator-vcc12v-dcinregulator-fixed Þvcc12v_dcin s ‡ ™· ±·¸èregulator-vcc1v2-ufs-vccq-s0regulator-fixed Þvcc1v2_ufs_vccq_s0 ‡ s ™O€ ±O€ ¨regulator-vcc1v8-ufs-vccq2-s0regulator-fixed Þvcc1v8_ufs_vccq2_s0 ‡ s ™w@ ±w@ äregulator-vcc3v3-lcd-s0regulator-fixed è £\defaultjå Þvcc3v3-lcd-s0 ™2Z  ±2Z  æregulator-vcc3v3-pcieregulator-fixed è ûp \defaultjç Þvcc3v3_pcie ™2Z  ±2Z  ˆ èregulator-vcc3v3-rtc-s5regulator-fixed Þvcc3v3_rtc_s5 ‡ s ™2Z  ±2Z  ¨regulator-vcc5v0-device-s0regulator-fixed è ûp\defaultjé Þvcc5v0_device s ‡ ™LK@ ±LK@ è¸ãregulator-vcc5v0-sys-s5regulator-fixed Þvcc_sys s ‡ ™LK@ ±LK@ 踨regulator-vcc5v0-usb20-host1regulator-fixed è û£\defaultjê Þvcc5v0_host1 ™LK@ ±LK@ ãregulator-vcc-1v1-nldo-s3regulator-fixed Þvcc_1v1_nldo_s3 ‡ s ™Èà ±Èà ¨¸ªregulator-vcc-1v8-s0regulator-fixed Þvcc_1v8_s0 ‡ s ™w@ ±w@ äregulator-vcc-2v0-pldo-s3regulator-fixed Þvcc_2v0_pldo_s3 ‡ s ™„€ ±„€ ¨¸©regulator-vcc-3v3-s0regulator-fixed Þvcc_3v3_s0 ‡ s ™2Z  ±2Z  æregulator-vcc-ufs-s0regulator-fixed Þvcc_ufs_s0 ‡ s ™2Z  ±2Z  ¨ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9serial10serial11spi0spi1spi2spi3spi4mmc0mmc1clock-frequencyclock-output-names#clock-cellscpudevice_typeregenable-methodcapacity-dmips-mhzclocksoperating-points-v2dynamic-power-coefficientcpu-idle-states#cooling-cellscpu-supplyphandleentry-methodarm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stopopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmemsimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-dairockchip,grfrangesgpio-controllergpio-rangesinterruptsinterrupt-controller#gpio-cells#interrupt-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsinterrupt-affinitypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereg-namesbus-rangeclock-namesdma-coherentinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-ib-windowsnum-viewportnum-ob-windowsnum-lanesphysphy-namespower-domainsresetsreset-namesdr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,parkmode-disable-hs-quirksnps,parkmode-disable-ss-quirksnps,dis_rxdet_inp3_quirk#phy-cells#reset-cellsassigned-clocksassigned-clock-parentsassigned-clock-ratespinctrl-namespinctrl-0reg-shiftreg-io-widthdmas#power-domain-cellspm_qosmali-supplyiommussramrockchip,disable-mmu-reset#iommu-cellsrockchip,pmuremote-endpointdma-namesrockchip,sai-rx-route#sound-dai-cellssound-name-prefixrockchip,sai-tx-routerockchip,vo-grfrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-handletx_delayreset-delay-usreset-gpiosreset-post-delay-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedfifo-depthmax-frequencyno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vqmmc-supplysupports-cqeno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-strobefull-pwr-cycle-in-suspendbitsarm,pl330-periph-burst#dma-cellssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplyfunctionregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-nameregulator-enable-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendwakeup-sourcenum-cs#io-channel-cellsvref-supply#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritynvmem-cellsnvmem-cell-namesrockchip,pipe-grfrockchip,pipe-phy-grfrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfpoolstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltenable-active-highgpiovin-supplystartup-delay-us