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D”÷ÝÞ Âaclkiface‰ï  Ëdisabled£Ndsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsióþ DDÂpclk÷èÓdphyÎOï –apba  Ëdisabledports port@0óport@1ódsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsióþ DEÂpclk÷éÓdphyÎPï –apba  Ëdisabledports port@0óport@1óhdmi@fe0a0000,rockchip,rk3568-dw-hdmióþ  D-(÷æç“(ÚÂiahbisfrcecref´default ªQRSï )a † Ëdisabled£ports port@0óport@1óqos@fe128000,rockchip,rk3568-qossysconóþ€ £,qos@fe138080,rockchip,rk3568-qossysconóþ€€ £;qos@fe138100,rockchip,rk3568-qossysconóþ� £<qos@fe138180,rockchip,rk3568-qossysconóþ�€ £=qos@fe148000,rockchip,rk3568-qossysconóþ€ £-qos@fe148080,rockchip,rk3568-qossysconóþ€€ £.qos@fe148100,rockchip,rk3568-qossysconóþ� £/qos@fe150000,rockchip,rk3568-qossysconóþ £9qos@fe158000,rockchip,rk3568-qossysconóþ€ £3qos@fe158100,rockchip,rk3568-qossysconóþ� £4qos@fe158180,rockchip,rk3568-qossysconóþ�€ £5qos@fe158200,rockchip,rk3568-qossysconóþ‚ £6qos@fe158280,rockchip,rk3568-qossysconóþ‚€ £7qos@fe158300,rockchip,rk3568-qossysconóþƒ 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Âapb_pclkÀ£ci2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþZ D/÷HG Âi2cpclkª{´default  Ëdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ[ D0÷JI Âi2cpclkª|´default  Ëdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ\ D1÷LK Âi2cpclkª}´default  Ëdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ] D2÷NM Âi2cpclkª~´default  Ëdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ^ D3÷PO Âi2cpclkª´default  Ëdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtóþ` D•÷ Âtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spióþa Dg÷RQÂspiclkapb_pclk$&&Ÿtxrx´default ª€�‚  Ëdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spióþb Dh÷TSÂspiclkapb_pclk$&&Ÿtxrx´default ªƒ„…  Ëdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spióþc Di÷VUÂspiclkapb_pclk$&&Ÿtxrx´default ª†‡ˆ  Ëdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spióþd Dj÷XWÂspiclkapb_pclk$&&Ÿtxrx´default ª‰Š‹  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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsstatusarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltpagesizeread-onlyvcc-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsphy-supplyrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesstdout-pathfunctioncolorlinux,default-triggermax-brightnesspwmsenable-active-highgpio