Ð þíô„8éÀ( Äéˆ ,qnap,ts433rockchip,rk3568 7Qnap TS-433-4G NAS System 4-Bayaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe310000â/i2c@fe5a0000/rtc@51ç/ethernet@fe2a0000cpus cpu@0ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ cpu@100ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ cpu@200ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ cpu@300ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ l3-cache,cacheµÁ'4@F­display-subsystem,rockchip,display-subsystemÏfirmwarescmi ,arm,scmi-smcÕ‚à protocol@14ýæ­hdmi-sound,simple-audio-cardóHDMI i2s# =disabledsimple-audio-card,codecDsimple-audio-card,cpuD pmu,arm,cortex-a55-pmu0NäåæçY psci ,arm,psci-1.0smcreserved-memory lshmem@10f000,arm,scmi-shmemýðs­timer,arm,armv8-timer0N   zxin24m ,fixed-clock‘n6¡xin24mæ­xin32k ,fixed-clock‘€¡xin32k´¾defaultæsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciýü@›œ�Ìsatapmaliverxoob N_Ø Ýsata-phyçù=okaysata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciýü€ ¡¢Ìsatapmaliverxoob N`Ø Ýsata-phyçù=okayusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3ýüÀ@ N©¦§¥Ìref_clksuspend_clkbus_clkhost utmi_wideù”=okay ØÝusb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ýý@ Nª©ª¨Ìref_clksuspend_clkbus_clkhost ØÝusb2-phyusb3-phy utmi_wideù• =disabledinterrupt-controller@fd400000 ,arm,gic-v3 ýý@ýF N 8M^ýAh(sl ‚­msi-controller@fd440000,arm,gic-v3-itsýýD‚s’­Qusb@fd800000 ,generic-ehciýý€ N‚½¾¼ØÝusb=okayusb@fd840000 ,generic-ohciýý„ Nƒ½¾¼ØÝusb=okayusb@fd880000 ,generic-ehciýýˆ N…¿À¼ØÝusb=okayusb@fd8c0000 ,generic-ohciýýŒ N†¿À¼ØÝusb=okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýý­Oio-domains&,rockchip,rk3568-pmu-io-voltage-domain=okay�«syscon@fdc50000ýýÅ ,rockchip,rk3568-pipe-grfsyscon­Ÿsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýýÆ­syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýýÈ­ syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýýÉ­¡syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýýÊ€­¢syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýýÊ€€­¤clock-controller@fdd00000,rockchip,rk3568-pmucruýýÐæ¹­clock-controller@fdd20000,rockchip,rk3568-cruýýÒÌxin24mæ¹Æ Ö€G†Œ ëÂë­i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýýÔ N.- Ìi2cpclk´¾default =okaypmic@20,rockchip,rk809ý Næ¾default´'3?KWco{‡“regulatorsDCDC_REG1 ¡vdd_logic°ÄÖí¡ ™pqregulator-state-mem2DCDC_REG2¡vdd_gpu°Öí¡ ™pq­Bregulator-state-mem2DCDC_REG3¡vcc_ddr°ÄÖregulator-state-memKDCDC_REG4¡vdd_npuÖí¡ ™pqregulator-state-mem2DCDC_REG5¡vcc_1v8°Äíw@w@­regulator-state-mem2LDO_REG1¡vdda0v9_image°í »  » regulator-state-mem2LDO_REG2 ¡vdda_0v9°Äí »  » regulator-state-mem2LDO_REG3 ¡vdda0v9_pmu°Äí »  » regulator-state-memKc » LDO_REG4 ¡vccio_acodec°Äí2Z 2Z regulator-state-mem2LDO_REG5 ¡vccio_sdíw@2Z regulator-state-mem2LDO_REG6 ¡vcc3v3_pmu°Äí2Z 2Z regulator-state-memKc2Z LDO_REG7 ¡vcca_1v8°Äíw@w@regulator-state-mem2LDO_REG8 ¡vcca1v8_pmu°Äíw@w@regulator-state-memKcw@LDO_REG9¡vcca1v8_image°íw@w@regulator-state-mem2SWITCH_REG1¡vcc_3v3°Äregulator-state-mem2SWITCH_REG2 ¡vcc3v3_sd°Äregulator-state-mem2regulator@40,silergy,syr827ý@¡vdd_cpu°Äí ß45°üœ ­serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýýÕ Nt ,Ìbaudclkapb_pclk§!!´"¾default¬¹=okaymcu,qnap,ts433-mcufan-0 Ã@Y€¦ÌÝî­‹nvmem-layout ,fixed-layout serial-number@0ýext-port@22ý"mac@24 ,mac-baseý$Òmac@35 ,mac-baseý5Òmac@46 ,mac-baseýFÒmac@57 ,mac-baseýWÒmac@68 ,mac-baseýhÒmac@79 ,mac-baseýyÒmac@8a ,mac-baseýŠÒmac@9b ,mac-baseý›Òpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 Ìpwmpclk´#¾defaultä =disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 Ìpwmpclk´$¾defaultä =disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý×  0 Ìpwmpclk´%¾defaultä =disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý×0 0 Ìpwmpclk´&¾defaultä =disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýýÙpower-controller!,rockchip,rk3568-power-controllerï ­power-domain@7ý'ïpower-domain@8ýÌÍ ()*ïpower-domain@9ý ÚÛÜ +,-ïpower-domain@10ý ñò./0123ïpower-domain@11ý í4ïpower-domain@13ý 5ïpower-domain@14ý 678ïpower-domain@15ý 9:;<=>?@ïgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýýæ@$N()'  jobmmugpuÌgpubusù=okayŽAB­�video-codec@fdea0400,rockchip,rk3568-vpuýýê N‹ vdpuîï Ìaclkhclk&Cù iommu@fdea0800,rockchip,rk3568-iommuýýê@ NŠ Ìaclkifaceîïù -­Crga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýýë€ NZóôõÌaclkhclksclk&$% :coreaxiahbù video-codec@fdee0000,rockchip,rk3568-vepuýýî N@ýþ Ìaclkhclk&Dù iommu@fdee0800,rockchip,rk3568-iommuýýî@ N?ýþ Ìaclkifaceù -­Dvideo-capture@fdfe0000,rockchip,rk3568-vicapýýþ N’ÆÐÖᣠÎÏÐÑÌaclkhclkdclkiclk&Eù(÷øùûú:arsthrstdrstprstirst =disabledports port@0ýport@1ýiommu@fdfe0800,rockchip,rk3568-iommuýýþ N’ÎÏ Ìaclkiface-ùF =disabled­Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ@ Nd ÁÂŽ�Ìbiuciuciu-driveciu-samplealðÑ€ë:reset =disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aýþN  macirqeth_wake_irq@†‰‰ÇÃĉÈWÌstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refì :stmmacethzFŠ›G®HÁ =disabledmdio,snps,dwmac-mdio stmmac-axi-configÊÔä­Frx-queues-configô­Gqueue0tx-queues-config ­Hqueue0vop@fe040000 ýþ0þ@ vopgamma-lut N”(ÝÞßàá%Ìaclkhclkdclk_vp0dclk_vp1dclk_vp2&Iù  =disabled,rockchip,rk3568-vopports ­port@0ý port@1ý port@2ý iommu@fe043e00,rockchip,rk3568-iommu ýþ>þ? N”ÝÞ Ìaclkiface-ù  =disabled­Idsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiýþ NDÌpclkèÝdphyØJù :apb =disabledports port@0ýport@1ýdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiýþ NEÌpclkéÝdphyØKù :apb =disabledports port@0ýport@1ýhdmi@fe0a0000,rockchip,rk3568-dw-hdmiýþ  N-(æç“(ÚÌiahbisfrcecref¾default ´LMNù ¬* =disabled­ports port@0ýport@1ýqos@fe128000,rockchip,rk3568-qossysconýþ€ ­'qos@fe138080,rockchip,rk3568-qossysconýþ€€ ­6qos@fe138100,rockchip,rk3568-qossysconýþ� ­7qos@fe138180,rockchip,rk3568-qossysconýþ�€ ­8qos@fe148000,rockchip,rk3568-qossysconýþ€ ­(qos@fe148080,rockchip,rk3568-qossysconýþ€€ ­)qos@fe148100,rockchip,rk3568-qossysconýþ� ­*qos@fe150000,rockchip,rk3568-qossysconýþ ­4qos@fe158000,rockchip,rk3568-qossysconýþ€ ­.qos@fe158100,rockchip,rk3568-qossysconýþ� ­/qos@fe158180,rockchip,rk3568-qossysconýþ�€ ­0qos@fe158200,rockchip,rk3568-qossysconýþ‚ ­1qos@fe158280,rockchip,rk3568-qossysconýþ‚€ ­2qos@fe158300,rockchip,rk3568-qossysconýþƒ ­3qos@fe180000,rockchip,rk3568-qossysconýþ qos@fe190000,rockchip,rk3568-qossysconýþ ­9qos@fe190280,rockchip,rk3568-qossysconýþ€ ­=qos@fe190300,rockchip,rk3568-qossysconýþ ­>qos@fe190380,rockchip,rk3568-qossysconýþ€ ­?qos@fe190400,rockchip,rk3568-qossysconýþ ­@qos@fe198000,rockchip,rk3568-qossysconýþ€ ­5qos@fe1a8000,rockchip,rk3568-qossysconýþ€ ­+qos@fe1a8080,rockchip,rk3568-qossysconýþ€€ ­,qos@fe1a8100,rockchip,rk3568-qossysconýþ� ­-dfi@fe230000,rockchip,rk3568-dfiýþ# N ;Opcie@fe260000,rockchip,rk3568-pcie0ýÀ@þ&ô dbiapbconfig<NKJIHG syspmcmsglegacyerrH(�‚ƒ„…$Ìaclk_mstaclk_slvaclk_dbipclkauxñpciMR`ePPPPs„“¢±Q¹Ø Ýpcie-phyùTlôôô ô à@¡:pipe  =disabledlegacy-interrupt-controllerM8 NH­Pmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ+@ Nb °±Š‹Ìbiuciuciu-driveciu-samplealðÑ€Ô:reset =disabledmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ,@ Nc ²³Œ�Ìbiuciuciu-driveciu-samplealðÑ€Ö:reset =disabledspi@fe300000 ,rockchip,sfcýþ0@ NexvÌclk_sfchclk_sfc´R¾default =disabledmmc@fe310000,rockchip,rk3568-dwcmshcýþ1 NÆ{}Ö ëÂn6(|zy{}Ìcorebusaxiblocktimer=okayÃl ëÂ;default´STUVrng@fe388000,rockchip,rk3568-rngýþ8€@po Ìcoreahbm=okayi2s@fe400000,rockchip,rk3568-i2s-tdmýþ@ N4Æ=AÖFÏqFÏq?C9Ìmclk_txmclk_rxhclk§WÛtxPQ :tx-mrx-m* =disabled­ i2s@fe410000,rockchip,rk3568-i2s-tdmýþA N5ÆEIÖFÏqFÏqGK:Ìmclk_txmclk_rxhclk§WWÛrxtxRS :tx-mrx-m¾default0´XYZ[\]^_`abc* =disabledi2s@fe420000,rockchip,rk3568-i2s-tdmýþB N6ÆMÖFÏqOO;Ìmclk_txmclk_rxhclk§WWÛtxrxT:tx-m¾default´defg* =disabledi2s@fe430000,rockchip,rk3568-i2s-tdmýþC N7SW<Ìmclk_txmclk_rxhclk§WWÛtxrxUV :tx-mrx-m* =disabledpdm@fe440000,rockchip,rk3568-pdmýþD NLZYÌpdm_clkpdm_hclk§W Ûrx´hijklm¾defaultX:pdm-m* =disabledspdif@fe460000,rockchip,rk3568-spdifýþF Nf Ìmclkhclk_\§WÛtx¾default´n* =disableddma-controller@fe530000,arm,pl330arm,primecellýþS@N å  Ìapb_pclkü­!dma-controller@fe550000,arm,pl330arm,primecellýþU@Nå  Ìapb_pclkü­Wi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþZ N/HG Ìi2cpclk´o¾default =okayrtc@51,microcrystal,rv8263ýQ“eeprom@54,giantec,gt24c04aatmel,24c04ýTVPD_MB $eeprom@56,giantec,gt24c04aatmel,24c04ýVVPD_BP $i2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ[ N0JI Ìi2cpclk´p¾default  =disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ\ N1LK Ìi2cpclk´q¾default  =disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ] N2NM Ìi2cpclk´r¾default  =disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ^ N3PO Ìi2cpclk´s¾default  =disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtýþ` N• Ìtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiýþa NgRQÌspiclkapb_pclk§!!Ûtxrx¾default ´tuv  =disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiýþb NhTSÌspiclkapb_pclk§!!Ûtxrx¾default ´wxy  =disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiýþc NiVUÌspiclkapb_pclk§!!Ûtxrx¾default ´z{|  =disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiýþd NjXWÌspiclkapb_pclk§!!Ûtxrx¾default ´}~  =disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartýþe NuÌbaudclkapb_pclk§!!´€¾default¬¹ =disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartýþf Nv# Ìbaudclkapb_pclk§!!´�¾default¬¹=okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartýþg Nw'$Ìbaudclkapb_pclk§!!´‚¾default¬¹ =disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartýþh Nx+(Ìbaudclkapb_pclk§!! ´ƒ¾default¬¹ =disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartýþi Ny/,Ìbaudclkapb_pclk§! ! ´„¾default¬¹ =disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþj Nz30Ìbaudclkapb_pclk§! ! ´…¾default¬¹ =disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþk N{74Ìbaudclkapb_pclk§!!´†¾default¬¹ =disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþl N|;8Ìbaudclkapb_pclk§!!´‡¾default¬¹ =disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþm N}?<Ìbaudclkapb_pclk§!!´ˆ¾default¬¹ =disabledthermal-zonescpu-thermal.dDèR‰tripscpu_alert0bpnÐøpassive­Šcpu_alert1b$ønÐøpassivecpu_critbsnÐ øcriticalcase-fan0nÐbˆ¸øactive­Œcase-fan1nÐb¯Èøactive­�case-fan2nÐbýèøactive­Žcooling-mapsmap0yŠ0~ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿmap1 ~‹ÿÿÿÿyŒmap2 ~‹y�map3 ~‹ÿÿÿÿyŽgpu-thermal.DèR‰tripsgpu-thresholdbpnÐøpassivegpu-targetb$ønÐøpassive­�gpu-critbsnÐ øcriticalcooling-mapsmap0y� ~�ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcýþq NsÆÖf@ ®`Ìtsadcapb_pclk�‚×�s¾defaultsleep´‘¤’®=okayÄÛ­‰saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcýþr N]Ìsaradcapb_pclk€ :saradc-apbö =disabledpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþnZY Ìpwmpclk´“¾defaultä =disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþnZY Ìpwmpclk´”¾defaultä =disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþn ZY Ìpwmpclk´•¾defaultä =disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþn0ZY Ìpwmpclk´–¾defaultä =disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo]\ Ìpwmpclk´—¾defaultä =disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo]\ Ìpwmpclk´˜¾defaultä =disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo ]\ Ìpwmpclk´™¾defaultä =disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo0]\ Ìpwmpclk´š¾defaultä =disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp`_ Ìpwmpclk´›¾defaultä =disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp`_ Ìpwmpclk´œ¾defaultä =disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp `_ Ìpwmpclk´�¾defaultä =disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp0`_ Ìpwmpclk´ž¾defaultä =disabledphy@fe830000,rockchip,rk3568-naneng-combphyýþƒ"} ÌrefapbpipeÆ"ÖõáÇ:phy Ÿ   0=okay­phy@fe840000,rockchip,rk3568-naneng-combphyýþ„%~ ÌrefapbpipeÆ%ÖõáÉ:phy Ÿ ¡ 0=okay­phy@fe870000,rockchip,rk3568-csi-dphyýþ‡yÌpclk 0º:apb =disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyýþ… Ìrefpclkz 0ù :apb» =disabled­Jmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyýþ† Ìrefpclk{ 0ù :apb¼ =disabled­Kusb2phy@fe8a0000,rockchip,rk3568-usb2phyýþŠÌphyclk¡clk_usbphy0_480m N‡ ;¢æ=okayhost-port 0 =disabled­otg-port 0=okay K£­usb2phy@fe8b0000,rockchip,rk3568-usb2phyýþ‹Ìphyclk¡clk_usbphy1_480m Nˆ ;¤æ=okayhost-port 0=okay K¥­otg-port 0=okay K¥­pinctrl,rockchip,rk3568-pinctrl;O l­¦gpio@fdd60000,rockchip,gpio-bankýýÖ N!.  V f¦  r8M­gpio@fe740000,rockchip,gpio-bankýþt N"cd V f¦  r8M­Ågpio@fe750000,rockchip,gpio-bankýþu N#ef V f¦@  r8M­´gpio@fe760000,rockchip,gpio-bankýþv N$gh V f¦`  r8Mgpio@fe770000,rockchip,gpio-bankýþw N%ij V f¦€  r8Mpcfg-pull-up ~­©pcfg-pull-none ‹­§pcfg-pull-none-drv-level-1 ‹ ˜­«pcfg-pull-none-drv-level-2 ‹ ˜­ªpcfg-pull-none-drv-level-3 ‹ ˜­®pcfg-pull-up-drv-level-1 ~ ˜­­pcfg-pull-up-drv-level-2 ~ ˜­¨pcfg-pull-none-smt ‹ §­¬acodecaudiopwmbt656bt1120camcan0can0m0-pins ¼ § §­¿can1can1m0-pins ¼§§­Àcan2can2m0-pins ¼ § §­Ácifclk32kclk32k-out0 ¼§­cpuebcedpdpemmcemmc-bus8€ ¼ ¨ ¨¨¨¨¨¨¨­Semmc-clk ¼¨­Temmc-cmd ¼¨­Uemmc-datastrobe ¼§­Veth0eth1flashfspifspi-pins` ¼§§§§§§­Rgmac0gmac0-miim ¼§§­¹gmac0-rx-bus20 ¼§§§­»gmac0-tx-bus20 ¼ ª ª §­ºgmac0-rgmii-clk ¼§«­¼gmac0-rgmii-bus@ ¼§§ªª­½eth-phy0-reset-pin ¼©­¾gmac1gpuhdmitxhdmitxm0-cec ¼§­Nhdmitx-scl ¼§­Lhdmitx-sda ¼§­Mi2c0i2c0-xfer ¼ ¬ ¬­i2c1i2c1-xfer ¼ ¬ ¬­oi2c2i2c2m0-xfer ¼ ¬¬­pi2c3i2c3m0-xfer ¼¬¬­qi2c4i2c4m0-xfer ¼ ¬ ¬­ri2c5i2c5m0-xfer ¼ ¬ ¬­si2s1i2s1m0-lrckrx ¼§­[i2s1m0-lrcktx ¼§­Zi2s1m0-sclkrx ¼§­Yi2s1m0-sclktx ¼§­Xi2s1m0-sdi0 ¼ §­\i2s1m0-sdi1 ¼ §­]i2s1m0-sdi2 ¼ §­^i2s1m0-sdi3 ¼§­_i2s1m0-sdo0 ¼§­`i2s1m0-sdo1 ¼§­ai2s1m0-sdo2 ¼ §­bi2s1m0-sdo3 ¼ §­ci2s2i2s2m0-lrcktx ¼§­ei2s2m0-sclktx ¼§­di2s2m0-sdi ¼§­fi2s2m0-sdo ¼§­gi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ¼§­hpdmm0-clk1 ¼§­ipdmm0-sdi0 ¼ §­jpdmm0-sdi1 ¼ §­kpdmm0-sdi2 ¼ §­lpdmm0-sdi3 ¼§­mpmicpmic-int-l ¼©­pmupwm0pwm0m0-pins ¼§­#pwm1pwm1m0-pins ¼§­$pwm2pwm2m0-pins ¼§­%pwm3pwm3-pins ¼§­&pwm4pwm4-pins ¼§­“pwm5pwm5-pins ¼§­”pwm6pwm6-pins ¼§­•pwm7pwm7-pins ¼§­–pwm8pwm8m0-pins ¼ §­—pwm9pwm9m0-pins ¼ §­˜pwm10pwm10m0-pins ¼ §­™pwm11pwm11m0-pins ¼§­špwm12pwm12m0-pins ¼§­›pwm13pwm13m0-pins ¼§­œpwm14pwm14m0-pins ¼§­�pwm15pwm15m0-pins ¼§­žrefclksatasata0sata1sata2scrsdmmc0sdmmc1sdmmc2spdifspdifm0-tx ¼§­nspi0spi0m0-pins0 ¼ §§§­vspi0m0-cs0 ¼§­tspi0m0-cs1 ¼§­uspi1spi1m0-pins0 ¼ §§§­yspi1m0-cs0 ¼§­wspi1m0-cs1 ¼§­xspi2spi2m0-pins0 ¼§§§­|spi2m0-cs0 ¼§­zspi2m0-cs1 ¼§­{spi3spi3m0-pins0 ¼ §§ §­spi3m0-cs0 ¼§­}spi3m0-cs1 ¼§­~tsadctsadc-shutorg ¼§­‘tsadc-pin ¼§­’uart0uart0-xfer ¼©©­"uart1uart1m0-xfer ¼ © ©­€uart2uart2m0-xfer ¼©©­�uart3uart3m0-xfer ¼©©­‚uart4uart4m0-xfer ¼©©­ƒuart5uart5m0-xfer ¼©©­„uart6uart6m0-xfer ¼©©­…uart7uart7m0-xfer ¼©©­†uart8uart8m0-xfer ¼©©­‡uart9uart9m0-xfer ¼©©­ˆvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2keyscopy-button-pin ¼©­Ãreset-button-pin ¼ ©­Äledshdd1-led-pin ¼©­Æhdd2-led-pin ¼©­Çhdd3-led-pin ¼©­Èhdd4_led-pin ¼©­Éusbvcc5v0-host-en ¼§­Ëvcc5v0-otg-en ¼§­Íopp-table-0,operating-points-v2 Ê­opp-408000000 ÕQ– Ü øP øPŒ0 êœ@opp-600000000 Õ#ÃF Ü øP øPŒ0 êœ@opp-816000000 Õ0£, Ü øP øPŒ0 êœ@ ûopp-1104000000 ÕAÍ´ Ü »  » Œ0 êœ@opp-1416000000 ÕTfr Ü£è£èŒ0 êœ@opp-1608000000 Õ_Ø" ÜÈàÈàŒ0 êœ@opp-1800000000 ÕkIÒ ÜŒ0Œ0Œ0 êœ@opp-1992000000 Õv»‚ ÜŒ0Œ0Œ0 êœ@opp-table-1,operating-points-v2­Aopp-200000000 Õ ëÂ Ü øP øPB@opp-300000000 Õá£ Ü øP øPB@opp-400000000 Õׄ Ü øP øPB@opp-600000000 Õ#ÃF Ü »  » B@opp-700000000 Õ)¹' Ü~ð~ðB@opp-800000000 Õ/¯ ÜB@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciýü–—˜Ìsatapmaliverxoob N^Ø Ýsata-phyçù =disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconýýÇ­Âqos@fe190080,rockchip,rk3568-qossysconýþ€ ­:qos@fe190100,rockchip,rk3568-qossysconýþ ­;qos@fe190200,rockchip,rk3568-qossysconýþ ­<syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconýýË€­¯phy@fe8c0000,rockchip,rk3568-pcie3-phyýþŒ 0&'wÌrefclk_mrefclk_npclk¾:phy ¯=okay ­±pcie@fe270000,rockchip,rk3568-pcie H(ˆ‰Š‹Œ$Ìaclk_mstaclk_slvaclk_dbipclkauxñpci<N Ÿž�œ syspmcmsglegacyerrMR`e°°°°s„“¢±Q¹ر Ýpcie-phyù0ýÀ@@þ'òTlòòò ò à@@@ dbiapbconfig±:pipe=okay # /²legacy-interrupt-controller8M N�­°pcie@fe280000,rockchip,rk3568-pcie H /(��‘’“$Ìaclk_mstaclk_slvaclk_dbipclkauxñpci<N¥¤£¢¡ syspmcmsglegacyerrMR`e³³³³s„“¢± Q ¹ر Ýpcie-phyù0ýÀ€@þ(ðTlððð ð à€€@ dbiapbconfigÁ:pipe=okay #´ /²legacy-interrupt-controller8M N¢­³ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aýþ*N macirqeth_wake_irq@‚……¸´µ…¹WÌstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref× :stmmacethzµŠ›¶®·Á=okayÆ…‚냶ÖsY@ ?output L¸ Wrgmii-id¾default´¹º»¼½mdio,snps,dwmac-mdio ethernet-phy@3,ethernet-phy-ieee802.3-c22ý´¾¾default `' #­¸stmmac-axi-configÊÔä­µrx-queues-configô­¶queue0tx-queues-config ­·queue0can@fe570000,rockchip,rk3568v2-canfdýþW NA@ ÌbaudpclkUT :coreapb¾default´¿ =disabledcan@fe580000,rockchip,rk3568v2-canfdýþX NCB ÌbaudpclkWV :coreapb¾default´À =disabledcan@fe590000,rockchip,rk3568v2-canfdýþY NED ÌbaudpclkYX :coreapb¾default´Á =disabledphy@fe820000,rockchip,rk3568-naneng-combphyýþ‚| ÌrefapbpipeÆÖõáÅ:phy Ÿ  0=okay­chosen pserial2:115200n8keys ,gpio-keys´Ãľdefaultkey-resetreset )  |˜key-copycopy ) |…leds ,gpio-ledsled-0 ‡ �disk )Åhdd1:green:disk –disk-activity¾default´Æled-1 ‡ �disk )Åhdd2:green:disk –disk-activity¾default´Çled-2 ‡ �disk )Åhdd3:green:disk –disk-activity¾default´Èled-3 ‡ �disk )´hdd4:green:disk –disk-activity¾default´Éregulator-dc-12v,regulator-fixed¡dc_12v°Äí··­Êregulator-vcc3v3-sys,regulator-fixed ¡vcc3v3_sys°Äí2Z 2Z œÊ­regulator-vcc5v0-host,regulator-fixed ¬¾default´Ë ¿ ¡vcc5v0_host°ÄíLK@LK@œÌ­¥regulator-vcc5v0-otg,regulator-fixed ¬ ¿¾default´Í ¡vcc5v0_otg°ÄíLK@LK@œÌ­£regulator-vcc5v0-sys,regulator-fixed ¡vcc5v0_sys°ÄíLK@LK@œÊ­ regulator-vcc5v0-usb,regulator-fixed ¡vcc5v0_usb°ÄíLK@LK@œÊ­Ìregulator-vcc3v3-pcie,regulator-fixed ¡vcc3v3_pcieí2Z 2Z  ¬ )œÊ­² interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0rtc0ethernet0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellsvccio4-supplyvccio6-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shiftcooling-levels#nvmem-cell-cells#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthnon-removabledma-namesarm,pl330-periph-burst#dma-cellslabelnum-addressespagesizeread-onlypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesreset-gpiosvpcie3v3-supplyclock_in_outphy-handlephy-modereset-assert-usstdout-pathlinux,codecolorfunctionlinux,default-triggerenable-active-highgpio