Ð þíöý8ëH( µë ,hinlink,h68krockchip,rk3568 7HINLINK H68Kaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe310000â/mmc@fe2b0000ç/ethernet@fe2a0000ñ/ethernet@fe010000cpus cpu@0ûcpu,arm,cortex-a55 !psci/€<@N€[€h@z€‡˜¬· cpu@100ûcpu,arm,cortex-a55 !psci/€<@N€[€h@z€‡˜¬· cpu@200ûcpu,arm,cortex-a55 !psci/€<@N€[€h@z€‡˜¬· cpu@300ûcpu,arm,cortex-a55 !psci/€<@N€[€h@z€‡˜¬· l3-cache,cache¿Ë1>@P·display-subsystem,rockchip,display-subsystemÙfirmwarescmi ,arm,scmi-smcß‚ê protocol@14ð·hdmi-sound,simple-audio-cardýHDMIi2s-Gokaysimple-audio-card,codecNsimple-audio-card,cpuN pmu,arm,cortex-a55-pmu0Xäåæçc psci ,arm,psci-1.0(smcreserved-memory vshmem@10f000,arm,scmi-shmemð}·timer,arm,armv8-timer0X   „xin24m ,fixed-clock›n6«xin24mð·xin32k ,fixed-clock›€«xin32k¾Èdefaultðsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ ›œ�Ösatapmaliverxoob X_â çsata-phyñ Gdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€  ¡¢Ösatapmaliverxoob X`â çsata-phyñ Gdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ X© ¦§¥Öref_clksuspend_clkbus_clkotg utmi_wide"”) Gdisabled âçusb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ Xª ©ª¨Öref_clksuspend_clkbus_clkhost âçusb2-phyusb3-phy utmi_wide"•)Gokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF X BWhýAr(}v Œ·msi-controller@fd440000,arm,gic-v3-itsýDŒ}œ·busb@fd800000 ,generic-ehciý€ X‚ ½¾¼âçusbGokayusb@fd840000 ,generic-ohciý„ Xƒ ½¾¼âçusbGokayusb@fd880000 ,generic-ehciýˆ X… ¿À¼âçusbGokayusb@fd8c0000 ,generic-ohciýŒ X† ¿À¼âçusbGokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý·`io-domains&,rockchip,rk3568-pmu-io-voltage-domainGokay§µÃÑßíû syscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsyscon·µsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýÆ·syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýÈ·¶syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýÉ··syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€·¸syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€·ºclock-controller@fdd00000,rockchip,rk3568-pmucruýÐð%·clock-controller@fdd20000,rockchip,rk3568-cruýÒ Öxin24mð%2 B€G†Œ ëÂWn·i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ X. - Öi2cpclk¾ Èdefault Gokayregulator@1c ,tcs,tcs4525{˜vdd_cpu§»Í 5åŒ0ýü!·regulator-state-mempmic@20,rockchip,rk809 ð"XÈdefault¾#6N\$h$t$€$Œ$˜$¤$°$¼$regulatorsDCDC_REG1 ˜vdd_logic§»ÈÍ¡ å™pýqregulator-state-memDCDC_REG2˜vdd_gpu§»ÈÍ¡ å™pýq·Fregulator-state-memDCDC_REG3˜vcc_ddr§»Èregulator-state-memßDCDC_REG4˜vdd_npuÈÍ¡ å™pýqregulator-state-memDCDC_REG5˜vcc_1v8§»Íw@åw@·regulator-state-memLDO_REG1˜vdda0v9_imageÍ » å » ·\regulator-state-memLDO_REG2 ˜vdda_0v9§»Í » å » regulator-state-memLDO_REG3 ˜vdda0v9_pmu§»Í » å » regulator-state-memß÷ » LDO_REG4 ˜vccio_acodec§Í2Z å2Z ·regulator-state-memLDO_REG5 ˜vccio_sdÍw@å2Z ·regulator-state-memLDO_REG6 ˜vcc3v3_pmu§»Í2Z å2Z ·regulator-state-memß÷2Z LDO_REG7 ˜vcca_1v8§»Íw@åw@·¨regulator-state-memLDO_REG8 ˜vcca1v8_pmu§»Íw@åw@regulator-state-memß÷w@LDO_REG9˜vcca1v8_imageÍw@åw@·]regulator-state-memSWITCH_REG1˜vcc_3v3§»·regulator-state-memSWITCH_REG2˜vcc3v3§»regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ Xt  ,Öbaudclkapb_pclk%%¾&Èdefault% Gdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Öpwmpclk¾'Èdefault/Gokaypwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Öpwmpclk¾(Èdefault/ Gdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0 Öpwmpclk¾)Èdefault/ Gdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0 Öpwmpclk¾*Èdefault/ Gdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller: ·power-domain@7 N+:power-domain@8 ÌÍ N,-.:power-domain@9  ÚÛÜ N/01:power-domain@10  ñòN234567:power-domain@11  íN8:power-domain@13  N9:power-domain@14  N:;<:power-domain@15  N=>?@ABCD:gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$X()' Ujobmmugpu ÖgpubusGokay˜EeF·¥video-codec@fdea0400,rockchip,rk3568-vpuýê X‹Uvdpu îï ÖaclkhclkqG iommu@fdea0800,rockchip,rk3568-iommuýê@ XŠ Öaclkiface îï x·Grga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ XZ óôõÖaclkhclksclk"&$% …coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepuýî X@ ýþ ÖaclkhclkqH iommu@fdee0800,rockchip,rk3568-iommuýî@ X? ýþ Öaclkiface x·Hvideo-capture@fdfe0000,rockchip,rk3568-vicapýþ X’2ÐBᣠ ÎÏÐÑÖaclkhclkdclkiclkqI("÷øùûú…arsthrstdrstprstirstn Gdisabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommuýþ X’ ÎÏ Öaclkifacex‘ Gdisabled·Immc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ Xd  ÁÂŽ�Öbiuciuciu-driveciu-sample¬·ðÑ€"ë…reset Gdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþX Umacirqeth_wake_irq@ †‰‰ÇÃĉÈWÖstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref"ì …stmmacethnÅJÕæKùL Gokay2‰†W‡BsY@output"M -rgmii-id6$Èdefault¾NOPQRSmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22AN Q†  cT·Mstmmac-axi-configoy‰·Jrx-queues-config™·Kqueue0tx-queues-config¯·Lqueue0vop@fe040000 þ0þ@Åvopgamma-lut X”( ÝÞßàá%Öaclkhclkdclk_vp0dclk_vp1dclk_vp2qU nGokay,rockchip,rk3568-vop2ßàWports ·port@0 endpoint@2ÏV·^port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? X” ÝÞ Öaclkifacex Gokay·Udsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ XDÖpclk èçdphyâW …apb"n Gdisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ XEÖpclk éçdphyâX …apb"n Gdisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  X-( æç“(ÚÖiahbisfrcecrefÈdefault ¾YZ[ nßGokayð\]·ports port@0endpointÏ^·Vport@1endpointÏ_·Ùqos@fe128000,rockchip,rk3568-qossysconþ€ ·+qos@fe138080,rockchip,rk3568-qossysconþ€€ ·:qos@fe138100,rockchip,rk3568-qossysconþ� ·;qos@fe138180,rockchip,rk3568-qossysconþ�€ ·<qos@fe148000,rockchip,rk3568-qossysconþ€ ·,qos@fe148080,rockchip,rk3568-qossysconþ€€ ·-qos@fe148100,rockchip,rk3568-qossysconþ� ·.qos@fe150000,rockchip,rk3568-qossysconþ ·8qos@fe158000,rockchip,rk3568-qossysconþ€ ·2qos@fe158100,rockchip,rk3568-qossysconþ� ·3qos@fe158180,rockchip,rk3568-qossysconþ�€ ·4qos@fe158200,rockchip,rk3568-qossysconþ‚ ·5qos@fe158280,rockchip,rk3568-qossysconþ‚€ ·6qos@fe158300,rockchip,rk3568-qossysconþƒ ·7qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ·=qos@fe190280,rockchip,rk3568-qossysconþ€ ·Aqos@fe190300,rockchip,rk3568-qossysconþ ·Bqos@fe190380,rockchip,rk3568-qossysconþ€ ·Cqos@fe190400,rockchip,rk3568-qossysconþ ·Dqos@fe198000,rockchip,rk3568-qossysconþ€ ·9qos@fe1a8000,rockchip,rk3568-qossysconþ€ ·/qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ·0qos@fe1a8100,rockchip,rk3568-qossysconþ� ·1dfi@fe230000,rockchip,rk3568-dfiþ# X `pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôÅdbiapbconfig<XKJIHGUsyspmcmsglegacyerr( �‚ƒ„…$Öaclk_mstaclk_slvaclk_dbipclkauxûpciW'`:aaaaHYhw†bŽâ çpcie-phyTvôôô ô à@"¡…pipe GokayÈdefault¾c cd˜elegacy-interrupt-controllerWB XH·ammc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ Xb  °±Š‹Öbiuciuciu-driveciu-sample¬·ðÑ€"Ô…resetGokay¨² Ã"ÌÈdefault¾fghi×äjðmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ Xc  ²³Œ�Öbiuciuciu-driveciu-sample¬·ðÑ€"Ö…reset Gdisabledspi@fe300000 ,rockchip,sfcþ0@ Xe xvÖclk_sfchclk_sfc¾kÈdefault Gdisabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 X2{}B ëÂn6( |zy{}ÖcorebusaxiblocktimerGokay¨ý· ë  Èdefault¾lmnoäðrng@fe388000,rockchip,rk3568-rngþ8€@ po Öcoreahb"mGokayi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ X42=ABFÏqFÏq ?C9Ömclk_txmclk_rxhclkp ,tx"PQ …tx-mrx-mnßGokay· i2s@fe410000,rockchip,rk3568-i2s-tdmþA X52EIBFÏqFÏq GK:Ömclk_txmclk_rxhclkpp ,rxtx"RS …tx-mrx-mnÈdefault0¾qrstuvwxyz{|ß Gdisabledi2s@fe420000,rockchip,rk3568-i2s-tdmþB X62MBFÏq OO;Ömclk_txmclk_rxhclkpp ,txrx"T…tx-mnÈdefault¾}~€ß Gdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC X7 SW<Ömclk_txmclk_rxhclkpp ,txrx"UV …tx-mrx-mnß Gdisabledpdm@fe440000,rockchip,rk3568-pdmþD XL ZYÖpdm_clkpdm_hclkp  ,rx¾�‚ƒ„…†Èdefault"X…pdm-mß Gdisabledspdif@fe460000,rockchip,rk3568-spdifþF Xf Ömclkhclk _\p ,txÈdefault¾‡ß Gdisableddma-controller@fe530000,arm,pl330arm,primecellþS@X  6   Öapb_pclk M·%dma-controller@fe550000,arm,pl330arm,primecellþU@X 6   Öapb_pclk M·pi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ X/ HG Öi2cpclk¾ˆÈdefault  Gdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ X0 JI Öi2cpclk¾‰Èdefault Gokayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ X1 LK Öi2cpclk¾ŠÈdefault  Gdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] X2 NM Öi2cpclk¾‹Èdefault  Gdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ X3 PO Öi2cpclk¾ŒÈdefault  Gdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` X•  Ötclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa Xg RQÖspiclkapb_pclk%% ,txrxÈdefault ¾�Ž�  Gdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb Xh TSÖspiclkapb_pclk%% ,txrxÈdefault ¾�‘’  Gdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc Xi VUÖspiclkapb_pclk%% ,txrxÈdefault ¾“”•  Gdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd Xj XWÖspiclkapb_pclk%% ,txrxÈdefault ¾–—˜  Gdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe Xu Öbaudclkapb_pclk%%¾™Èdefault% Gdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf Xv # Öbaudclkapb_pclk%%¾šÈdefault%Gokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg Xw '$Öbaudclkapb_pclk%%¾›Èdefault% Gdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh Xx +(Öbaudclkapb_pclk%% ¾œÈdefault% Gdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi Xy /,Öbaudclkapb_pclk% % ¾�Èdefault% Gdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj Xz 30Öbaudclkapb_pclk% % ¾žÈdefault% Gdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk X{ 74Öbaudclkapb_pclk%%¾ŸÈdefault% Gdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl X| ;8Öbaudclkapb_pclk%%¾ Èdefault% Gdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm X} ?<Öbaudclkapb_pclk%%¾¡Èdefault% Gdisabledthermal-zonescpu-thermal Xd nè |¢tripscpu_alert0 Œp ˜Ðpassive·£cpu_alert1 Œ$ø ˜Ðpassivecpu_crit Œs ˜Ð criticalcooling-mapsmap0 ££0 ¨ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal X nè |¢tripsgpu-threshold Œp ˜Ðpassivegpu-target Œ$ø ˜Ðpassive·¤gpu-crit Œs ˜Ð criticalcooling-mapsmap0 £¤ ¨¥ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq Xs2Bf@ ®` Ötsadcapb_pclk"�‚×n ·sÈdefaultsleep¾¦ Χ ØGokay î ·¢saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr X] Ösaradcapb_pclk"€ …saradc-apb Gokay 2¨pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Öpwmpclk¾©Èdefault/ Gdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Öpwmpclk¾ªÈdefault/ Gdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY Öpwmpclk¾«Èdefault/ Gdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY Öpwmpclk¾¬Èdefault/ Gdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Öpwmpclk¾­Èdefault/ Gdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Öpwmpclk¾®Èdefault/ Gdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\ Öpwmpclk¾¯Èdefault/ Gdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\ Öpwmpclk¾°Èdefault/ Gdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Öpwmpclk¾±Èdefault/ Gdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Öpwmpclk¾²Èdefault/ Gdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_ Öpwmpclk¾³Èdefault/ Gdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_ Öpwmpclk¾´Èdefault/ Gdisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "} Örefapbpipe2"Bõá"Ç…phy >µ P¶ fGokay·phy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~ Örefapbpipe2%Bõá"É…phy >µ P· fGokay·phy@fe870000,rockchip,rk3568-csi-dphyþ‡ yÖpclk f"º…apbn Gdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… Örefpclk z f …apb"» Gdisabled·Wmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† Örefpclk { f …apb"¼ Gdisabled·Xusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ Öphyclk«clk_usbphy0_480m X‡ q¸ðGokayhost-port fGokay6¹·otg-port f Gdisabled·usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹ Öphyclk«clk_usbphy1_480m Xˆ qºðGokayhost-port fGokay6¹·otg-port fGokay6¹·pinctrl,rockchip,rk3568-pinctrln` v·»gpio@fdd60000,rockchip,gpio-bankýÖ X! .  � ‘»  �BW·"gpio@fe740000,rockchip,gpio-bankþt X" cd � ‘»  �BW·Tgpio@fe750000,rockchip,gpio-bankþu X# ef � ‘»@  �BW·dgpio@fe760000,rockchip,gpio-bankþv X$ gh � ‘»`  �BW·Ègpio@fe770000,rockchip,gpio-bankþw X% ij � ‘»€  �BWpcfg-pull-up ©·¾pcfg-pull-none ¶·¼pcfg-pull-none-drv-level-1 ¶ ÷Àpcfg-pull-none-drv-level-2 ¶ ÷¿pcfg-pull-none-drv-level-3 ¶ ÷Ãpcfg-pull-up-drv-level-1 © ÷Âpcfg-pull-up-drv-level-2 © ÷½pcfg-pull-none-smt ¶ Ò·Áacodecaudiopwmbt656bt1120camcan0can0m0-pins ç ¼ ¼·Õcan1can1m0-pins ç¼¼·Öcan2can2m0-pins ç ¼ ¼·×cifclk32kclk32k-out0 ç¼·cpuebcedpdpemmcemmc-bus8€ ç ½ ½½½½½½½·lemmc-clk ç½·memmc-cmd ç½·nemmc-datastrobe ç¼·oeth0eth1flashfspifspi-pins` ç¼¼¼¼¼¼·kgmac0gmac0-miim ç¼¼·Ïgmac0-rx-bus20 ç¼¼¼·Ñgmac0-tx-bus20 ç ¿ ¿ ¼·Ðgmac0-rgmii-clk ç¼À·Ògmac0-rgmii-bus@ ç¼¼¿¿·Ógmac1gmac1m1-miim ç¼¼·Ngmac1m1-rx-bus20 ç¼¼ ¼·Pgmac1m1-tx-bus20 ç¿¿¼·Ogmac1m1-rgmii-clk ç¼À·Qgmac1m1-rgmii-bus@ ç¼¼¿¿·Rgpuhdmitxhdmitxm0-cec ç¼·[hdmitx-scl ç¼·Yhdmitx-sda ç¼·Zi2c0i2c0-xfer ç Á Á· i2c1i2c1-xfer ç Á Á·ˆi2c2i2c2m1-xfer ç Á Á·‰i2c3i2c3m0-xfer çÁÁ·Ši2c4i2c4m0-xfer ç Á Á·‹i2c5i2c5m0-xfer ç Á Á·Œi2s1i2s1m0-lrckrx ç¼·ti2s1m0-lrcktx ç¼·si2s1m0-sclkrx ç¼·ri2s1m0-sclktx ç¼·qi2s1m0-sdi0 ç ¼·ui2s1m0-sdi1 ç ¼·vi2s1m0-sdi2 ç ¼·wi2s1m0-sdi3 ç¼·xi2s1m0-sdo0 ç¼·yi2s1m0-sdo1 ç¼·zi2s1m0-sdo2 ç ¼·{i2s1m0-sdo3 ç ¼·|i2s2i2s2m0-lrcktx ç¼·~i2s2m0-sclktx ç¼·}i2s2m0-sdi ç¼·i2s2m0-sdo ç¼·€i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ç¼·�pdmm0-clk1 ç¼·‚pdmm0-sdi0 ç ¼·ƒpdmm0-sdi1 ç ¼·„pdmm0-sdi2 ç ¼·…pdmm0-sdi3 ç¼·†pmicpmic-int ç¾·#pmupwm0pwm0m0-pins ç¼·'pwm1pwm1m0-pins ç¼·(pwm2pwm2m0-pins ç¼·)pwm3pwm3-pins ç¼·*pwm4pwm4-pins ç¼·©pwm5pwm5-pins ç¼·ªpwm6pwm6-pins ç¼·«pwm7pwm7-pins ç¼·¬pwm8pwm8m0-pins ç ¼·­pwm9pwm9m0-pins ç ¼·®pwm10pwm10m0-pins ç ¼·¯pwm11pwm11m0-pins ç¼·°pwm12pwm12m0-pins ç¼·±pwm13pwm13m0-pins ç¼·²pwm14pwm14m0-pins ç¼·³pwm15pwm15m0-pins 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1ethernet0ethernet1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr50vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vnon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesstdout-pathlabellinux,codedebounce-intervalcolorfunctionlinux,default-triggerenable-active-high