Ð þíæR8Û4( Úü %,lunzn,fastrhino-r66srockchip,rk35687Lunzn FastRhino R66Saliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe2b0000cpus cpu@0âcpu,arm,cortex-a55îòùpsci€#@5€B€O@a€n“ž cpu@100âcpu,arm,cortex-a55îòùpsci€#@5€B€O@a€n“ž cpu@200âcpu,arm,cortex-a55îòùpsci€#@5€B€O@a€n“ž cpu@300âcpu,arm,cortex-a55îòùpsci€#@5€B€O@a€n“ž l3-cache,cache¦²%@7ždisplay-subsystem,rockchip,display-subsystemÀ Ædisabledfirmwarescmi ,arm,scmi-smcÍ‚Ø protocol@14îÞžhdmi-sound,simple-audio-cardëHDMIi2s Ædisabledsimple-audio-card,codec5simple-audio-card,cpu5 pmu,arm,cortex-a55-pmu0?äåæçJ psci ,arm,psci-1.0smcreserved-memory ]shmem@10f000,arm,scmi-shmemîðdžtimer,arm,armv8-timer0?   kxin24m ,fixed-clock‚n6’xin24mÞžxin32k ,fixed-clock‚€’xin32k¥¯defaultÞsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciîü@ò›œ�½satapmaliverxoob ?_É Îsata-phyØê Ædisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciîü€ò ¡¢½satapmaliverxoob ?`É Îsata-phyØê Ædisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3îüÀ@ ?©ò¦§¥½ref_clksuspend_clkbus_clkøhost utmi_wideê ”Æokay ÉÎusb2-phyusb3-phy)usb@fd000000,rockchip,rk3568-dwc3snps,dwc3îý@ ?ªò©ª¨½ref_clksuspend_clkbus_clkøhost ÉÎusb2-phyusb3-phy utmi_wideê •Æokayinterrupt-controller@fd400000 ,arm,gic-v3 îý@ýF ? 0EVýA`(k] zžmsi-controller@fd440000,arm,gic-v3-itsîýDzkŠžUusb@fd800000 ,generic-ehciîý€ ?‚ò½¾¼ÉÎusb Ædisabledusb@fd840000 ,generic-ohciîý„ ?ƒò½¾¼ÉÎusb Ædisabledusb@fd880000 ,generic-ehciîýˆ ?…ò¿À¼ÉÎusb Ædisabledusb@fd8c0000 ,generic-ohciîýŒ ?†ò¿À¼ÉÎusb Ædisabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdîýžSio-domains&,rockchip,rk3568-pmu-io-voltage-domainÆokay•£±¿ÍÛé÷syscon@fdc50000îýÅ ,rockchip,rk3568-pipe-grfsysconž¡syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdîýÆžsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconîýÈž¢syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconîýÉž£syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconîýÊ€ž¤syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconîýÊ€€ž¦clock-controller@fdd00000,rockchip,rk3568-pmucruîýÐÞžclock-controller@fdd20000,rockchip,rk3568-cruîýÒò½xin24mÞ  0€G†Œ ëÂE\ži2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cîýÔ ?.ò- ½i2cpclk¥ ¯default Æokayregulator@1c ,tcs,tcs4525îi†vdd_cpu•©» 5ÓŒ0ëü!žregulator-state-mem pmic@20,rockchip,rk809î "?Þ¯default¥#$<$H$T$`$l$x$„$�$œ$¨regulatorsDCDC_REG1 †vdd_logic•©¶»¡ Ó™pëqregulator-state-mem DCDC_REG2†vdd_gpu•¶»¡ Ó™pëqžFregulator-state-mem DCDC_REG3†vcc_ddr•©¶regulator-state-memÍDCDC_REG4†vdd_npu¶»¡ Ó™pëqregulator-state-mem DCDC_REG5†vcc_1v8•©»w@Ów@žregulator-state-mem LDO_REG1†vdda0v9_image»~ðÓ~ðregulator-state-mem LDO_REG2 †vdda_0v9•©» » Ó » regulator-state-mem LDO_REG3 †vdda0v9_pmu•©» » Ó » regulator-state-memÍå » LDO_REG4 †vccio_acodec•»2Z Ó2Z regulator-state-mem LDO_REG5 †vccio_sd»w@Ó2Z žregulator-state-mem LDO_REG6 †vcc3v3_pmu•©»2Z Ó2Z žregulator-state-memÍå2Z LDO_REG7 †vcca_1v8•©»w@Ów@ž”regulator-state-mem LDO_REG8 †vcca1v8_pmu•©»w@Ów@regulator-state-memÍåw@LDO_REG9†vcca1v8_image»~ðÓw@regulator-state-mem å~ðSWITCH_REG1†vcc_3v3•©žregulator-state-mem SWITCH_REG2 †vcc3v3_sdžZregulator-state-mem serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartîýÕ ?tò ,½baudclkapb_pclk%%¥&¯default Ædisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmîý×ò 0 ½pwmpclk¥'¯default Ædisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmîý×ò 0 ½pwmpclk¥(¯default Ædisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmîý× ò 0 ½pwmpclk¥)¯default Ædisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmîý×0ò 0 ½pwmpclk¥*¯default Ædisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdîýÙpower-controller!,rockchip,rk3568-power-controller( žpower-domain@7îò<+(power-domain@8îòÌÍ <,-.(power-domain@9î òÚÛÜ </01(power-domain@10î òñò<234567(power-domain@11î òí<8(power-domain@13òî <9(power-domain@14îò <:;<(power-domain@15îò <=>?@ABCD(gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostîýæ@$?()' Cjobmmugpuò½gpubusùêÆokayESFž‘video-codec@fdea0400,rockchip,rk3568-vpuîýê ?‹Cvdpuòîï ½aclkhclk_Gê iommu@fdea0800,rockchip,rk3568-iommuîýê@ ?Š ½aclkifaceòîïê fžGrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaîýë€ ?Zòóôõ½aclkhclksclk &$% scoreaxiahbê video-codec@fdee0000,rockchip,rk3568-vepuîýî ?@òýþ ½aclkhclk_Hê iommu@fdee0800,rockchip,rk3568-iommuîýî@ ??òýþ ½aclkifaceê fžHvideo-capture@fdfe0000,rockchip,rk3568-vicapîýþ ?’ Ð0ᣠòÎÏÐѽaclkhclkdclkiclk_Iê( ÷øùûúsarsthrstdrstprstirst\ Ædisabledports port@0îport@1îiommu@fdfe0800,rockchip,rk3568-iommuîýþ ?’òÎÏ ½aclkifacefê ÆdisabledžImmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcîþ@ ?d òÁÂŽ�½biuciuciu-driveciu-sampleš¥ðÑ€ ësreset Ædisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aîþ? Cmacirqeth_wake_irq@ò†‰‰ÇÃĉÈW½stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref ì sstmmaceth\³JÃÔKçLú Ædisabledmdio,snps,dwmac-mdio stmmac-axi-config žJrx-queues-config-žKqueue0tx-queues-configCžLqueue0vop@fe040000 îþ0þ@Yvopgamma-lut ?”(òÝÞßàá%½aclkhclkdclk_vp0dclk_vp1dclk_vp2_Mê \Æokay,rockchip,rk3568-vop ßàEports žport@0î port@1î port@2î iommu@fe043e00,rockchip,rk3568-iommu îþ>þ? ?”òÝÞ ½aclkifacefê ÆokayžMdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiîþ ?D½pclkòèÎdphyÉNê sapb \ Ædisabledports port@0îport@1îdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiîþ ?E½pclkòéÎdphyÉOê sapb \ Ædisabledports port@0îport@1îhdmi@fe0a0000,rockchip,rk3568-dw-hdmiîþ  ?-(òæç“(Ú½iahbisfrcecref¯default ¥PQRê \c Ædisabledžports port@0îport@1îqos@fe128000,rockchip,rk3568-qossysconîþ€ ž+qos@fe138080,rockchip,rk3568-qossysconîþ€€ ž:qos@fe138100,rockchip,rk3568-qossysconîþ� ž;qos@fe138180,rockchip,rk3568-qossysconîþ�€ ž<qos@fe148000,rockchip,rk3568-qossysconîþ€ ž,qos@fe148080,rockchip,rk3568-qossysconîþ€€ ž-qos@fe148100,rockchip,rk3568-qossysconîþ� ž.qos@fe150000,rockchip,rk3568-qossysconîþ ž8qos@fe158000,rockchip,rk3568-qossysconîþ€ ž2qos@fe158100,rockchip,rk3568-qossysconîþ� ž3qos@fe158180,rockchip,rk3568-qossysconîþ�€ ž4qos@fe158200,rockchip,rk3568-qossysconîþ‚ ž5qos@fe158280,rockchip,rk3568-qossysconîþ‚€ ž6qos@fe158300,rockchip,rk3568-qossysconîþƒ ž7qos@fe180000,rockchip,rk3568-qossysconîþ qos@fe190000,rockchip,rk3568-qossysconîþ ž=qos@fe190280,rockchip,rk3568-qossysconîþ€ žAqos@fe190300,rockchip,rk3568-qossysconîþ žBqos@fe190380,rockchip,rk3568-qossysconîþ€ žCqos@fe190400,rockchip,rk3568-qossysconîþ žDqos@fe198000,rockchip,rk3568-qossysconîþ€ ž9qos@fe1a8000,rockchip,rk3568-qossysconîþ€ ž/qos@fe1a8080,rockchip,rk3568-qossysconîþ€€ ž0qos@fe1a8100,rockchip,rk3568-qossysconîþ� ž1dfi@fe230000,rockchip,rk3568-dfiîþ# ? tSpcie@fe260000,rockchip,rk3568-pcie0îÀ@þ&ôYdbiapbconfig<?KJIHGCsyspmcmsglegacyerr�(ò�‚ƒ„…$½aclk_mstaclk_slvaclk_dbipclkauxâpciE‹`žTTTT¬½ÌÛêUòÉ Îpcie-phyêT]ôôô ô à@ ¡spipe  Ædisabledlegacy-interrupt-controllerE0 ?HžTmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcîþ+@ ?b ò°±Š‹½biuciuciu-driveciu-sampleš¥ðÑ€ ÔsresetÆokayü)4<C¯default¥VWXYPZ\mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcîþ,@ ?c ò²³Œ�½biuciuciu-driveciu-sampleš¥ðÑ€ Ösreset Ædisabledspi@fe300000 ,rockchip,sfcîþ0@ ?eòxv½clk_sfchclk_sfc¥[¯default Ædisabledmmc@fe310000,rockchip,rk3568-dwcmshcîþ1 ? {}0 ëÂn6(ò|zy{}½corebusaxiblocktimer Ædisabledrng@fe388000,rockchip,rk3568-rngîþ8€@òpo ½coreahb mÆokayi2s@fe400000,rockchip,rk3568-i2s-tdmîþ@ ?4 =A0FÏqFÏqò?C9½mclk_txmclk_rxhclk\itx PQ stx-mrx-m\c Ædisabledž i2s@fe410000,rockchip,rk3568-i2s-tdmîþA ?5 EI0FÏqFÏqòGK:½mclk_txmclk_rxhclk\\irxtx RS stx-mrx-m\¯default0¥]^_`abcdefghc Ædisabledi2s@fe420000,rockchip,rk3568-i2s-tdmîþB ?6 M0FÏqòOO;½mclk_txmclk_rxhclk\\itxrx Tstx-m\¯default¥ijklc Ædisabledi2s@fe430000,rockchip,rk3568-i2s-tdmîþC ?7òSW<½mclk_txmclk_rxhclk\\itxrx UV stx-mrx-m\c Ædisabledpdm@fe440000,rockchip,rk3568-pdmîþD ?LòZY½pdm_clkpdm_hclk\ irx¥mnopqr¯default Xspdm-mc Ædisabledspdif@fe460000,rockchip,rk3568-spdifîþF ?f ½mclkhclkò_\\itx¯default¥sc Ædisableddma-controller@fe530000,arm,pl330arm,primecellîþS@? sò  ½apb_pclkŠž%dma-controller@fe550000,arm,pl330arm,primecellîþU@?sò  ½apb_pclkŠž\i2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cîþZ ?/òHG ½i2cpclk¥t¯default  Ædisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cîþ[ ?0òJI ½i2cpclk¥u¯default  Ædisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cîþ\ ?1òLK ½i2cpclk¥v¯default  Ædisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cîþ] ?2òNM ½i2cpclk¥w¯default  Ædisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cîþ^ ?3òPO ½i2cpclk¥x¯default  Ædisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtîþ` ?•ò ½tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiîþa ?gòRQ½spiclkapb_pclk%%itxrx¯default ¥yz{  Ædisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiîþb ?hòTS½spiclkapb_pclk%%itxrx¯default ¥|}~  Ædisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiîþc ?iòVU½spiclkapb_pclk%%itxrx¯default ¥€�  Ædisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiîþd ?jòXW½spiclkapb_pclk%%itxrx¯default ¥‚ƒ„  Ædisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartîþe ?uò½baudclkapb_pclk%%¥…¯default Ædisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartîþf ?vò# ½baudclkapb_pclk%%¥†¯defaultÆokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartîþg ?wò'$½baudclkapb_pclk%%¥‡¯default Ædisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartîþh ?xò+(½baudclkapb_pclk%% ¥ˆ¯default Ædisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartîþi ?yò/,½baudclkapb_pclk% % ¥‰¯default Ædisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartîþj ?zò30½baudclkapb_pclk% % ¥Š¯default Ædisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartîþk ?{ò74½baudclkapb_pclk%%¥‹¯default Ædisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartîþl ?|ò;8½baudclkapb_pclk%%¥Œ¯default Ædisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartîþm ?}ò?<½baudclkapb_pclk%%¥�¯default Ædisabledthermal-zonescpu-thermal•d«è¹Žtripscpu_alert0ÉpÕÐépassivež�cpu_alert1É$øÕÐépassivecpu_critÉsÕÐ écriticalcooling-mapsmap0à�0å ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal•«è¹Žtripsgpu-thresholdÉpÕÐépassivegpu-targetÉ$øÕÐépassivež�gpu-critÉsÕÐ écriticalcooling-mapsmap0à� å‘ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcîþq ?s 0f@ ®`ò½tsadcapb_pclk �‚×\ôs¯defaultsleep¥’ “ Æokay + BžŽsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcîþr ?]ò½saradcapb_pclk € ssaradc-apb ]Æokay o”pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþnòZY ½pwmpclk¥•¯default Ædisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþnòZY ½pwmpclk¥–¯default Ædisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþn òZY ½pwmpclk¥—¯default Ædisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþn0òZY ½pwmpclk¥˜¯default Ædisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþoò]\ ½pwmpclk¥™¯default Ædisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþoò]\ ½pwmpclk¥š¯default Ædisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþo ò]\ ½pwmpclk¥›¯default Ædisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþo0ò]\ ½pwmpclk¥œ¯default Ædisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþpò`_ ½pwmpclk¥�¯default Ædisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþpò`_ ½pwmpclk¥ž¯default Ædisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþp ò`_ ½pwmpclk¥Ÿ¯default Ædisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmîþp0ò`_ ½pwmpclk¥ ¯default Ædisabledphy@fe830000,rockchip,rk3568-naneng-combphyîþƒò"} ½refapbpipe "0õá Çsphy {¡ �¢ £Æokayžphy@fe840000,rockchip,rk3568-naneng-combphyîþ„ò%~ ½refapbpipe %0õá Ésphy {¡ �£ £ Ædisabledžphy@fe870000,rockchip,rk3568-csi-dphyîþ‡òy½pclk £ ºsapb\ Ædisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyîþ… ½refpclkòz £ê sapb » ÆdisabledžNmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyîþ† ½refpclkò{ £ê sapb ¼ ÆdisabledžOusb2phy@fe8a0000,rockchip,rk3568-usb2phyîþŠò½phyclk’clk_usbphy0_480m ?‡ ®¤ÞÆokayžhost-port £Æokay ¾!žotg-port £Æokay ¾¥žusb2phy@fe8b0000,rockchip,rk3568-usb2phyîþ‹ò½phyclk’clk_usbphy1_480m ?ˆ ®¦Þ Ædisabledhost-port £ Ædisabledžotg-port £ Ædisabledžpinctrl,rockchip,rk3568-pinctrl\tS ]ž§gpio@fdd60000,rockchip,gpio-bankîýÖ ?!ò.  É Ù§  å0Ež"gpio@fe740000,rockchip,gpio-bankîþt ?"òcd É Ù§  å0Egpio@fe750000,rockchip,gpio-bankîþu ?#òef É Ù§@  å0Egpio@fe760000,rockchip,gpio-bankîþv ?$ògh É Ù§`  å0Egpio@fe770000,rockchip,gpio-bankîþw ?%òij É Ù§€  å0Epcfg-pull-up ñžªpcfg-pull-none þž¨pcfg-pull-none-drv-level-1 þ ž¬pcfg-pull-none-drv-level-2 þ ž«pcfg-pull-none-drv-level-3 þ ž¯pcfg-pull-up-drv-level-1 ñ ž®pcfg-pull-up-drv-level-2 ñ ž©pcfg-pull-none-smt þ ž­acodecaudiopwmbt656bt1120camcan0can0m0-pins / ¨ ¨ž¸can1can1m0-pins /¨¨ž¹can2can2m0-pins / ¨ ¨žºcifclk32kclk32k-out0 /¨žcpuebcedpdpemmceth0eth1flashfspifspi-pins` /¨¨¨¨¨¨ž[gmac0gmac1gpuhdmitxhdmitxm0-cec /¨žRhdmitx-scl /¨žPhdmitx-sda /¨žQi2c0i2c0-xfer / ­ ­ž i2c1i2c1-xfer / ­ ­žti2c2i2c2m0-xfer / ­­žui2c3i2c3m0-xfer /­­žvi2c4i2c4m0-xfer / ­ ­žwi2c5i2c5m0-xfer / ­ ­žxi2s1i2s1m0-lrckrx /¨ž`i2s1m0-lrcktx /¨ž_i2s1m0-sclkrx /¨ž^i2s1m0-sclktx /¨ž]i2s1m0-sdi0 / ¨žai2s1m0-sdi1 / ¨žbi2s1m0-sdi2 / ¨žci2s1m0-sdi3 /¨ždi2s1m0-sdo0 /¨žei2s1m0-sdo1 /¨žfi2s1m0-sdo2 / ¨žgi2s1m0-sdo3 / ¨žhi2s2i2s2m0-lrcktx /¨žji2s2m0-sclktx /¨žii2s2m0-sdi /¨žki2s2m0-sdo /¨žli2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk /¨žmpdmm0-clk1 /¨žnpdmm0-sdi0 / ¨žopdmm0-sdi1 / ¨žppdmm0-sdi2 / ¨žqpdmm0-sdi3 /¨žrpmicpmic-int /ªž#pmupwm0pwm0m0-pins /¨ž'pwm1pwm1m0-pins /¨ž(pwm2pwm2m0-pins /¨ž)pwm3pwm3-pins /¨ž*pwm4pwm4-pins /¨ž•pwm5pwm5-pins /¨ž–pwm6pwm6-pins /¨ž—pwm7pwm7-pins /¨ž˜pwm8pwm8m0-pins / ¨ž™pwm9pwm9m0-pins / ¨žšpwm10pwm10m0-pins / ¨ž›pwm11pwm11m0-pins /¨žœpwm12pwm12m0-pins /¨ž�pwm13pwm13m0-pins /¨žžpwm14pwm14m0-pins /¨žŸpwm15pwm15m0-pins /¨ž refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ /©©©©žVsdmmc0-clk /©žWsdmmc0-cmd /©žXsdmmc0-det /ªžYsdmmc1sdmmc2spdifspdifm0-tx /¨žsspi0spi0m0-pins0 / ¨¨¨ž{spi0m0-cs0 /¨žyspi0m0-cs1 /¨žzspi1spi1m0-pins0 / ¨¨¨ž~spi1m0-cs0 /¨ž|spi1m0-cs1 /¨ž}spi2spi2m0-pins0 /¨¨¨ž�spi2m0-cs0 /¨žspi2m0-cs1 /¨ž€spi3spi3m0-pins0 / ¨¨ ¨ž„spi3m0-cs0 /¨ž‚spi3m0-cs1 /¨žƒtsadctsadc-shutorg /¨ž’tsadc-pin /¨ž“uart0uart0-xfer /ªªž&uart1uart1m0-xfer / ª ªž…uart2uart2m0-xfer /ªªž†uart3uart3m0-xfer /ªªž‡uart4uart4m0-xfer /ªªžˆuart5uart5m0-xfer /ªªž‰uart6uart6m0-xfer /ªªžŠuart7uart7m0-xfer /ªªž‹uart8uart8m0-xfer /ªªžŒuart9uart9m0-xfer /ªªž�vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-ledsstatus-led-pin /¨ž½rockchip-keyreset-button-pin /ªž¼usbvcc5v0-usb-otg-en /¨ž¿opp-table-0,operating-points-v2 =žopp-408000000 HQ– O øP øPŒ0 ]œ@opp-600000000 H#ÃF O øP øPŒ0 ]œ@opp-816000000 H0£, O øP øPŒ0 ]œ@ nopp-1104000000 HAÍ´ O »  » Œ0 ]œ@opp-1416000000 HTfr O£è£èŒ0 ]œ@opp-1608000000 H_Ø" OÈàÈàŒ0 ]œ@opp-1800000000 HkIÒ OŒ0Œ0Œ0 ]œ@opp-1992000000 Hv»‚ OŒ0Œ0Œ0 ]œ@opp-table-1,operating-points-v2žEopp-200000000 H ë O øP øPB@opp-300000000 HᣠO øP øPB@opp-400000000 Hׄ O øP øPB@opp-600000000 H#ÃF O »  » B@opp-700000000 H)¹' O~ð~ðB@opp-800000000 H/¯ OB@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciîüò–—˜½satapmaliverxoob ?^É Îsata-phyØê Ædisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconîýÇž»qos@fe190080,rockchip,rk3568-qossysconîþ€ ž>qos@fe190100,rockchip,rk3568-qossysconîþ ž?qos@fe190200,rockchip,rk3568-qossysconîþ ž@syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconîýË€ž°phy@fe8c0000,rockchip,rk3568-pcie3-phyîþŒ £ò&'w½refclk_mrefclk_npclk ¾sphy z°Æokay ‹ž²pcie@fe270000,rockchip,rk3568-pcie �(òˆ‰Š‹Œ$½aclk_mstaclk_slvaclk_dbipclkauxâpci<? Ÿž�œCsyspmcmsglegacyerrE‹`ž±±±±¬½ÌÛêUòɲ Îpcie-phyê0îÀ@@þ'òT]òòò ò à@@@Ydbiapbconfig ±spipeÆokay –" ¢³legacy-interrupt-controller0E ?�ž±pcie@fe280000,rockchip,rk3568-pcie � /(ò��‘’“$½aclk_mstaclk_slvaclk_dbipclkauxâpci<?¥¤£¢¡CsyspmcmsglegacyerrE‹`ž´´´´¬½ÌÛê U òɲ Îpcie-phyê0îÀ€@þ(ðT]ððð ð à€€@Ydbiapbconfig ÁspipeÆokay –" ¢³legacy-interrupt-controller0E ?¢ž´ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aîþ*?Cmacirqeth_wake_irq@ò‚……¸´µ…¹W½stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref × sstmmaceth\³µÃÔ¶ç·ú Ædisabledmdio,snps,dwmac-mdio stmmac-axi-config žµrx-queues-config-ž¶queue0tx-queues-configCž·queue0can@fe570000,rockchip,rk3568v2-canfdîþW ?òA@ ½baudpclk UT scoreapb¯default¥¸ Ædisabledcan@fe580000,rockchip,rk3568v2-canfdîþX ?òCB ½baudpclk WV scoreapb¯default¥¹ Ædisabledcan@fe590000,rockchip,rk3568v2-canfdîþY ?òED ½baudpclk YX scoreapb¯default¥º Ædisabledphy@fe820000,rockchip,rk3568-naneng-combphyîþ‚ò| ½refapbpipe 0õá Åsphy {¡ �» £Æokayžchosen ²serial2:1500000n8gpio-keys ,gpio-keys¯default¥¼button-reset ¾2 œ" Ðreset Ö˜gpio-leds ,gpio-leds¯default¥½led-status á çstatus œ" ðheartbeatregulator-vcc12v-dcin,regulator-fixed †vcc12v_dcin•©»·Ó·ž¾regulator-vcc3v3-pcie,regulator-fixed †vcc3v3_pcie•©»2Z Ó2Z !ž³regulator-vcc3v3-sys,regulator-fixed †vcc3v3_sys•©»2Z Ó2Z ¾ž$regulator-vcc5v0-sys,regulator-fixed †vcc5v0_sys•©»LK@ÓLK@¾ž!regulator-vcc5v0-usb-otg,regulator-fixed  "¯default¥¿†vcc5v0_usb_otg»LK@ÓLK@!ž¥ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsstatusarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyvccio3-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr50vmmc-supplyvqmmc-supplydma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesreset-gpiosvpcie3v3-supplystdout-pathdebounce-intervallabellinux,codecolorfunctionlinux,default-triggerenable-active-highgpio