Ð þí�8œ(ód ,anbernic,rg-dsrockchip,rk35687Anbernic RG DS=handsetaliasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000�/i2c@fe5e0000†/serial@fdd50000Ž/serial@fe650000–/serial@fe660000ž/serial@fe670000¦/serial@fe680000®/serial@fe690000¶/serial@fe6a0000¾/serial@fe6b0000Æ/serial@fe6c0000Î/serial@fe6d0000Ö/spi@fe610000Û/spi@fe620000à/spi@fe630000å/spi@fe640000ê/mmc@fe310000ï/mmc@fe2b0000ô/mmc@fe000000cpus cpu@0ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ cpu@100ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ cpu@200ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ cpu@300ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ l3-cache,cache½É/<@Nµdisplay-subsystem,rockchip,display-subsystem×firmwarescmi ,arm,scmi-smcÝ‚è protocol@14îµhdmi-sound,simple-audio-cardûHDMIi2s+ Edisabledsimple-audio-card,codecLsimple-audio-card,cpuL pmu,arm,cortex-a55-pmu0Väåæça psci ,arm,psci-1.0&smcreserved-memory tshmem@10f000,arm,scmi-shmemð{µtimer,arm,armv8-timer0V   ‚xin24m ,fixed-clock™n6©xin24mîµxin32k ,fixed-clock™€©xin32k¼Ædefaultîsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ ›œ�Ôsatapmaliverxoob V_à åsata-phyï Edisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€  ¡¢Ôsatapmaliverxoob V`à åsata-phyï Edisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ V© ¦§¥Ôref_clksuspend_clkbus_clk peripheral utmi_wide ”'Eokayà åusb2-phy @high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ Vª ©ª¨Ôref_clksuspend_clkbus_clkhost àåusb2-phyusb3-phy utmi_wide •' Edisabledinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF V NctýA~(‰t ˜µmsi-controller@fd440000,arm,gic-v3-itsýD˜‰¨µnusb@fd800000 ,generic-ehciý€ V‚ ½¾¼àåusbEokayusb@fd840000 ,generic-ohciý„ Vƒ ½¾¼àåusbEokayusb@fd880000 ,generic-ehciýˆ V… ¿À¼àåusb Edisabledusb@fd8c0000 ,generic-ohciýŒ V† ¿À¼àåusb Edisabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýµlio-domains&,rockchip,rk3568-pmu-io-voltage-domainEokay³ÁÏÝëùsyscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsysconµ¿syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƵsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȵÀsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɵÁsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€µÂsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€µÃclock-controller@fdd00000,rockchip,rk3568-pmucruýÐî#µclock-controller@fdd20000,rockchip,rk3568-cruýÒ Ôxin24mî# 0@€G†Œ ëÂo2 Ulµi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ V. - Ôi2cpclk¼Ædefault Eokaypmic@20,rockchip,rk817 U–0HîÔmclk©rk808-clkout1rk808-clkout2 H V¼!"ÆdefaultyŠ¢°#¼#È#Ô#à#ì#ø##$µêregulatorsDCDC_REG10BY™pq »  ‰vdd_logic˜qregulator-state-mem­Å » DCDC_REG20BY™pq –¨‰vdd_gpu˜qµHregulator-state-memáDCDC_REG30B‰vcc_ddrregulator-state-mem­DCDC_REG40BY2Z q2Z ‰vcc_3v3µregulator-state-mem­Å2Z LDO_REG10Yw@qw@ ‰vcca1v8_pmuregulator-state-mem­Åw@LDO_REG20Y » q »  ‰vdda_0v9regulator-state-memáLDO_REG30Y » q »  ‰vdda0v9_pmuregulator-state-mem­Å » LDO_REG40Y2Z q2Z  ‰vccio_acodecµregulator-state-memáLDO_REG50Y2Z qw@ ‰vccio_sdµregulator-state-memáLDO_REG60Y2Z q2Z  ‰vcc3v3_pmuµregulator-state-mem­Å2Z LDO_REG70Yw@qw@‰vcc_1v8µregulator-state-mem­LDO_REG80Y2Z qw@ ‰vcc1v8_dvpregulator-state-memáLDO_REG90Y*¹€q*¹€ ‰vcc2v8_dvpµ�regulator-state-memáBOOST0YReÀqG·`‰boostµ$regulator-state-memáOTG_SWITCH ‰otg_switchregulator-state-memáchargerú% '/IðU† µ&regulator@40,silergy,syr827@|0Y5°q ß4‰vdd_cpu˜ü™#µregulator-state-memábattery@62,cellwise,cw2015b@¤g�oiecTuPWVNOD5,$$2AMW …4TYm…��„<ll AM€• 8~˜£€‰—Ë/d¥µÁF®½ˆú%Ú& Edisabledserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ Vt  ,Ôbaudclkapb_pclké''¼(Ædefaultîû Edisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Ôpwmpclk¼)Ædefault Edisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Ôpwmpclk¼*Ædefault Edisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0 Ôpwmpclk¼+Ædefault Edisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0 Ôpwmpclk¼,Ædefault Edisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller µpower-domain@7 $-power-domain@8 ÌÍ $./0power-domain@9  ÚÛÜ $123power-domain@10  ñò$456789power-domain@11  í$:power-domain@13  $;power-domain@14  $<=>power-domain@15  $?@ABCDEFgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$V()' +jobmmugpu ÔgpubusEokay–G;Hµ°video-codec@fdea0400,rockchip,rk3568-vpuýê V‹+vdpu îï ÔaclkhclkGI iommu@fdea0800,rockchip,rk3568-iommuýê@ VŠ Ôaclkiface îï NµIrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ VZ óôõÔaclkhclksclk &$% [coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepuýî V@ ýþ ÔaclkhclkGJ iommu@fdee0800,rockchip,rk3568-iommuýî@ V? ýþ Ôaclkiface NµJvideo-capture@fdfe0000,rockchip,rk3568-vicapýþ V’0Ð@ᣠ ÎÏÐÑÔaclkhclkdclkiclkGK( ÷øùûú[arsthrstdrstprstirstl Edisabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommuýþ V’ ÎÏ ÔaclkifaceNg EdisabledµKmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ Vd  ÁÂŽ�Ôbiuciuciu-driveciu-sample‚�õá ë[resetEokay›¥¶ÃÙLä ¼MNOÆdefaultò Pwifi@1QV +host-wake¼RÆdefaultethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþV +macirqeth_wake_irq@ †‰‰ÇÃĉÈWÔstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref ì [stmmacethl S-T@US Edisabledmdio,snps,dwmac-mdio stmmac-axi-config\fvµSrx-queues-config†µTqueue0tx-queues-configœµUqueue0vop@fe040000 þ0þ@²vopgamma-lut V”( ÝÞßàá%Ôaclkhclkdclk_vp0dclk_vp1dclk_vp2GV lEokay,rockchip,rk3568-vop0ßàUports µport@0 endpoint@4¼WµZport@1 endpoint@6¼Xµbport@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? V” ÝÞ ÔaclkifaceN EokayµVdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ VDÔpclk èådphyàY [apb lEokay ports port@0endpoint¼ZµWport@1endpoint¼[µ`panel@01,anbernic,rg-ds-display-bottomjadard,jd9365da-h3Ì\¼]Ædefault Ö â^í_µ“portendpoint¼`µ[dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ VEÔpclk éådphyàa [apb lEokay ports port@0endpoint¼bµXport@1endpoint¼cµhpanel@0.,anbernic,rg-ds-display-topjadard,jd9365da-h3Ìd¼eÆdefault Ö âfígµŽportendpoint¼hµchdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  V-( æç“(ÚÔiahbisfrcecrefÆdefault ¼ijk îly Edisabledµports port@0port@1qos@fe128000,rockchip,rk3568-qossysconþ€ µ-qos@fe138080,rockchip,rk3568-qossysconþ€€ µ<qos@fe138100,rockchip,rk3568-qossysconþ� µ=qos@fe138180,rockchip,rk3568-qossysconþ�€ µ>qos@fe148000,rockchip,rk3568-qossysconþ€ µ.qos@fe148080,rockchip,rk3568-qossysconþ€€ µ/qos@fe148100,rockchip,rk3568-qossysconþ� µ0qos@fe150000,rockchip,rk3568-qossysconþ µ:qos@fe158000,rockchip,rk3568-qossysconþ€ µ4qos@fe158100,rockchip,rk3568-qossysconþ� µ5qos@fe158180,rockchip,rk3568-qossysconþ�€ µ6qos@fe158200,rockchip,rk3568-qossysconþ‚ µ7qos@fe158280,rockchip,rk3568-qossysconþ‚€ µ8qos@fe158300,rockchip,rk3568-qossysconþƒ µ9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ µ?qos@fe190280,rockchip,rk3568-qossysconþ€ µCqos@fe190300,rockchip,rk3568-qossysconþ µDqos@fe190380,rockchip,rk3568-qossysconþ€ µEqos@fe190400,rockchip,rk3568-qossysconþ µFqos@fe198000,rockchip,rk3568-qossysconþ€ µ;qos@fe1a8000,rockchip,rk3568-qossysconþ€ µ1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ µ2qos@fe1a8100,rockchip,rk3568-qossysconþ� µ3dfi@fe230000,rockchip,rk3568-dfiþ# V úlpcie@fe260000,rockchip,rk3568-pcie0À@þ&ô²dbiapbconfig<VKJIHG+syspmcmsglegacyerr ( �‚ƒ„…$Ôaclk_mstaclk_slvaclk_dbipclkauxùpcic ` $mmmm 2 C R a pn xà åpcie-phyTtôôô ô à@ ¡[pipe  Edisabledlegacy-interrupt-controllercN VHµmmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ Vb  °±Š‹Ôbiuciuciu-driveciu-sample‚�ðÑ€ Ô[resetEokay›¥ ‚  ‹¼opqrÆdefaultòs –mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ Vc  ²³Œ�Ôbiuciuciu-driveciu-sample‚�ðÑ€ Ö[reset Edisabledspi@fe300000 ,rockchip,sfcþ0@ Ve xvÔclk_sfchclk_sfc¼tÆdefault Edisabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 V0{}@ ëÂn6( |zy{}ÔcorebusaxiblocktimerEokay›� ë £ ©ä¼uvwxyÆdefaultrng@fe388000,rockchip,rk3568-rngþ8€@ po Ôcoreahb mEokayi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ V40=A@FÏqFÏq ?C9Ômclk_txmclk_rxhclkéz ±tx PQ [tx-mrx-mly Edisabledµ i2s@fe410000,rockchip,rk3568-i2s-tdmþA V50EI@FÏqFÏq GK:Ômclk_txmclk_rxhclkézz ±rxtx RS [tx-mrx-mlÆdefault¼{|}~yEokay »µíi2s@fe420000,rockchip,rk3568-i2s-tdmþB V60M@FÏq OO;Ômclk_txmclk_rxhclkézz ±txrx T[tx-mlÆdefault¼€�‚y Edisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC V7 SW<Ômclk_txmclk_rxhclkézz ±txrx UV [tx-mrx-mly Edisabledpdm@fe440000,rockchip,rk3568-pdmþD VL ZYÔpdm_clkpdm_hclkéz  ±rx¼ƒ„…†‡ˆÆdefault X[pdm-my Edisabledspdif@fe460000,rockchip,rk3568-spdifþF Vf Ômclkhclk _\éz ±txÆdefault¼‰y Edisableddma-controller@fe530000,arm,pl330arm,primecellþS@V  Ö   Ôapb_pclk íµ'dma-controller@fe550000,arm,pl330arm,primecellþU@V Ö   Ôapb_pclk íµzi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ V/ HG Ôi2cpclk¼ŠÆdefault  Edisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ V0 JI Ôi2cpclk¼‹Ædefault Eokay™ @i2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ V1 LK Ôi2cpclk¼ŒÆdefault Eokay™€touchscreen@14 ,goodix,gt911 ø� V   Ž Ö  € )à < S¼��Ædefault ji2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] V2 NM Ôi2cpclk¼‘Ædefault  Edisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ V3 PO Ôi2cpclk¼’Ædefault Eokay™€touchscreen@14 ,goodix,gt911 ø� V   “ Ö  € )༔•Ædefault jwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` V•  Ôtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa Vg RQÔspiclkapb_pclké'' ±txrxÆdefault ¼–—˜  Edisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb Vh TSÔspiclkapb_pclké'' ±txrxÆdefault ¼™š›  Edisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc Vi VUÔspiclkapb_pclké'' ±txrxÆdefault ¼œ�ž  Edisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd Vj XWÔspiclkapb_pclké'' ±txrxÆdefault ¼Ÿ ¡  Edisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe Vu Ôbaudclkapb_pclké'' ¼¢£¤ÆdefaultîûEokay wbluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt ‡  ™  ¦ serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf Vv # Ôbaudclkapb_pclk¼¥ÆdefaultîûEokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg Vw '$Ôbaudclkapb_pclké''¼¦Ædefaultîû Edisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh Vx +(Ôbaudclkapb_pclké'' ¼§Ædefaultîû Edisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi Vy /,Ôbaudclkapb_pclké' ' ¼¨Ædefaultîû Edisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj Vz 30Ôbaudclkapb_pclké' ' ¼©Ædefaultîû Edisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk V{ 74Ôbaudclkapb_pclké''¼ªÆdefaultîû Edisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl V| ;8Ôbaudclkapb_pclké''¼«Ædefaultîû Edisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm V} ?<Ôbaudclkapb_pclké''¼¬Ædefaultîû Edisabledthermal-zonescpu-thermal ¶d Ìè Ú­tripscpu_alert0 êp öÐEpassiveµ®cpu_alert1 ê$ø öÐEpassivecpu_crit ês öÐ Ecriticalcooling-mapsmap0 ®0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal ¶ Ìè Ú­tripsgpu-threshold êp öÐEpassivegpu-target ê$ø öÐEpassiveµ¯gpu-crit ês öÐ Ecriticalcooling-mapsmap0 ¯ °ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq Vs0@f@ ®` Ôtsadcapb_pclk �‚×l sÆdefaultsleep¼± ,² 6Eokay L cµ­saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr V] Ôsaradcapb_pclk € [saradc-apb ~Eokay �µÛpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Ôpwmpclk¼³Ædefault Edisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Ôpwmpclk¼´ÆdefaultEokayµçpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY Ôpwmpclk¼µÆdefaultEokayµèpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY Ôpwmpclk¼¶ÆdefaultEokayµépwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Ôpwmpclk¼·Ædefault Edisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Ôpwmpclk¼¸Ædefault Edisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\ Ôpwmpclk¼¹Ædefault Edisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\ Ôpwmpclk¼ºÆdefault Edisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Ôpwmpclk¼»ÆdefaultEokayµßpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Ôpwmpclk¼¼ÆdefaultEokayµàpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_ Ôpwmpclk¼½ÆdefaultEokayµópwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_ Ôpwmpclk¼¾Ædefault Edisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "} Ôrefapbpipe0"@õá Ç[phy œ¿ ®À Ä Edisabledµphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~ Ôrefapbpipe0%@õá É[phy œ¿ ®Á Ä Edisabledµphy@fe870000,rockchip,rk3568-csi-dphyþ‡ yÔpclk Ä º[apbl Edisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… Ôrefpclk z Ä [apb »EokayµYmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† Ôrefpclk { Ä [apb ¼Eokayµausb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ Ôphyclk©clk_usbphy0_480m V‡ ÏÂîEokayhost-port Ä Edisabledµotg-port ÄEokayµusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹ Ôphyclk©clk_usbphy1_480m Vˆ ÏÃîEokayhost-port Ä Edisabledµotg-port ÄEokayµpinctrl,rockchip,rk3568-pinctrllúl tµÄgpio@fdd60000,rockchip,gpio-bankýÖ V! .  ß ïÄ  ûNcµ gpio@fe740000,rockchip,gpio-bankþt V" cd ß ïÄ  ûNcgpio@fe750000,rockchip,gpio-bankþu V# ef ß ïÄ@  ûNcµãgpio@fe760000,rockchip,gpio-bankþv V$ gh ß ïÄ`  ûNcµâgpio@fe770000,rockchip,gpio-bankþw V% ij ß ïÄ€  ûNcµQpcfg-pull-up µÇpcfg-pull-down µÎpcfg-pull-none #µÅpcfg-pull-none-drv-level-1 # 0µÉpcfg-pull-none-drv-level-2 # 0µÈpcfg-pull-none-drv-level-3 # 0µÌpcfg-pull-up-drv-level-1  0µËpcfg-pull-up-drv-level-2  0µÆpcfg-pull-none-smt # ?µÊpcfg-output-low TµÍacodecaudiopwmbt656bt1120camcan0can0m0-pins _ Šŵ×can1can1m0-pins _ÅŵØcan2can2m0-pins _ ŠŵÙcifclk32kclk32k-out0 _ŵcpuebcedpdpemmcemmc-rstnout _ŵyemmc-bus8€ _ Æ ÆÆÆÆÆÆÆµuemmc-clk _Ƶvemmc-cmd _Ƶwemmc-datastrobe _ŵxeth0eth1flashfspifspi-pins` _ÅÅÅÅÅŵtgmac0gmac1gpuhdmitxhdmitxm0-cec _ŵkhdmitx-scl _ŵihdmitx-sda _ŵji2c0i2c0-xfer _ Ê Êµi2c1i2c1-xfer _ Ê ÊµŠi2c2i2c2m1-xfer _ Ê Êµ‹i2c3i2c3m1-xfer _ ÊʵŒi2c4i2c4m0-xfer _ Ê Êµ‘i2c5i2c5m0-xfer _ Ê Êµ’i2s1i2s1m0-lrcktx _ŵ|i2s1m0-mclk _ŵ!i2s1m0-sclktx _ŵ{i2s1m0-sdi0 _ ŵ}i2s1m0-sdo0 _ŵ~i2s2i2s2m0-lrcktx _ŵ€i2s2m0-sclktx _ŵi2s2m0-sdi _ŵ�i2s2m0-sdo _ŵ‚i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk _ŵƒpdmm0-clk1 _ŵ„pdmm0-sdi0 _ ŵ…pdmm0-sdi1 _ ŵ†pdmm0-sdi2 _ ŵ‡pdmm0-sdi3 _ŵˆpmicpmic-int-l _ǵ"pmupwm0pwm0m0-pins _ŵ)pwm1pwm1m0-pins _ŵ*pwm2pwm2m0-pins _ŵ+pwm3pwm3-pins _ŵ,pwm4pwm4-pins _ŵ³pwm5pwm5-pins _ŵ´pwm6pwm6-pins _ŵµpwm7pwm7-pins _ŵ¶pwm8pwm8m0-pins _ ŵ·pwm9pwm9m0-pins _ ŵ¸pwm10pwm10m0-pins _ ŵ¹pwm11pwm11m0-pins _ŵºpwm12pwm12m1-pins _ŵ»pwm13pwm13m1-pins _ŵ¼pwm14pwm14m0-pins _ŵ½pwm15pwm15m0-pins _ŵ¾refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ _ÆÆÆÆµosdmmc0-clk _Ƶpsdmmc0-cmd _Ƶqsdmmc0-det _ǵrsdmmc1sdmmc2sdmmc2m0-bus4@ _ÆÆÆÆµMsdmmc2m0-clk _ƵNsdmmc2m0-cmd _ƵOspdifspdifm0-tx _ŵ‰spi0spi0m0-pins0 _ ÅÅŵ˜spi0m0-cs0 _ŵ–spi0m0-cs1 _ŵ—spi1spi1m0-pins0 _ ÅÅŵ›spi1m0-cs0 _ŵ™spi1m0-cs1 _ŵšspi2spi2m0-pins0 _ÅÅŵžspi2m0-cs0 _ŵœspi2m0-cs1 _ŵ�spi3spi3m0-pins0 _ ÅŠŵ¡spi3m0-cs0 _ŵŸspi3m0-cs1 _ŵ tsadctsadc-shutorg _ŵ±tsadc-pin _ŵ²uart0uart0-xfer _Çǵ(uart1uart1m1-xfer _Çǵ¢uart1m1-ctsn _ŵ£uart1m1-rtsn _ŵ¤uart2uart2m0-xfer _Çǵ¥uart3uart3m0-xfer _Çǵ¦uart4uart4m0-xfer _Çǵ§uart5uart5m0-xfer _Çǵ¨uart6uart6m0-xfer _Çǵ©uart7uart7m0-xfer _Çǵªuart8uart8m0-xfer _Çǵ«uart9uart9m0-xfer _Çǵ¬vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-keysvol-keys_l _Çǵågamepad-keys-l _ÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇǵágpio-lcdlcd0-rst _ ŵ]lcd1-rst _ ŵehall-sensorhal-int-l _ŵähp-detecthp-det _ŵìjoy-muxjoy-mux-en _͵Þjoy-mux-config _Åŵæsdio-pwrseqwifi-enable-h _ŵësdmmcsdmmc-pwren-l _ŵòtouchtouch0-rst _ ǵ”touch0-irq _ǵ•touch1-rst _ǵ�touch1-irq _ǵ�vcc-lcdvdd-lcd0-h _ŵîvccio-lcd0-h _ŵïvdd-lcd1-h _ŵðvccio-lcd1-h _ŵñvcc-wifivcc-wifi-h _ŵôwifi-irqwifi-host-wake-irq _εRopp-table-0,operating-points-v2 mµopp-408000000 xQ–  øP øPŒ0 �œ@opp-600000000 x#ÃF  øP øPŒ0 �œ@opp-816000000 x0£,  øP øPŒ0 �œ@ žopp-1104000000 xAÍ´  »  » Œ0 �œ@opp-1416000000 xTfr £è£èŒ0 �œ@opp-1608000000 x_Ø" ÈàÈàŒ0 �œ@opp-1800000000 xkIÒ Œ0Œ0Œ0 �œ@opp-1992000000 xv»‚ Œ0Œ0Œ0 �œ@opp-table-1,operating-points-v2µGopp-200000000 x ë  øP øPB@opp-300000000 xᣠ øP øPB@opp-400000000 xׄ  øP øPB@opp-600000000 x#ÃF  »  » B@opp-700000000 x)¹' ~ð~ðB@opp-800000000 x/¯ B@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü –—˜Ôsatapmaliverxoob V^àÏ åsata-phyï Edisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconýǵÚqos@fe190080,rockchip,rk3568-qossysconþ€ µ@qos@fe190100,rockchip,rk3568-qossysconþ µAqos@fe190200,rockchip,rk3568-qossysconþ µBsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconýË€µÐphy@fe8c0000,rockchip,rk3568-pcie3-phyþŒ Ä &'wÔrefclk_mrefclk_npclk ¾[phy ªÐ EdisabledµÒpcie@fe270000,rockchip,rk3568-pcie  ( ˆ‰Š‹Œ$Ôaclk_mstaclk_slvaclk_dbipclkauxùpci<V Ÿž�œ+syspmcmsglegacyerrc ` $ÑÑÑÑ 2 C R a pn xàÒ åpcie-phy0À@@þ'òTtòòò ò à@@@²dbiapbconfig ±[pipe Edisabledlegacy-interrupt-controllerNc V�µÑpcie@fe280000,rockchip,rk3568-pcie   /( ��‘’“$Ôaclk_mstaclk_slvaclk_dbipclkauxùpci<V¥¤£¢¡+syspmcmsglegacyerrc ` $ÓÓÓÓ 2 C R a p n  xàÒ åpcie-phy0À€@þ(ðTtððð ð à€€@²dbiapbconfig Á[pipe Edisabledlegacy-interrupt-controllerNc V¢µÓethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ*V+macirqeth_wake_irq@ ‚……¸´µ…¹WÔstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref × [stmmacethl Ô-Õ@ÖS Edisabledmdio,snps,dwmac-mdio stmmac-axi-config\fvµÔrx-queues-config†µÕqueue0tx-queues-configœµÖqueue0can@fe570000,rockchip,rk3568v2-canfdþW V A@ Ôbaudpclk UT [coreapbÆdefault¼× Edisabledcan@fe580000,rockchip,rk3568v2-canfdþX V CB Ôbaudpclk WV [coreapbÆdefault¼Ø Edisabledcan@fe590000,rockchip,rk3568v2-canfdþY V ED Ôbaudpclk YX [coreapbÆdefault¼Ù Edisabledphy@fe820000,rockchip,rk3568-naneng-combphyþ‚ | Ôrefapbpipe0@õá Å[phy œ¿ ®Ú Ä EdisabledµÏchosen »serial2:1500000n8adc-keys-home ,adc-keys Çbuttons ØÛ äw@ þ<button-home HOME < Öadc-keys-play ,adc-keys Çbuttons ØÛ äÖ  þ<button-play PLAY ¤ Öadc-mux,io-channel-mux Ûleft_xright_xleft_yright_y ~ ØÛ Çparent 7Ü DdµÝadc-joystick ,adc-joystick ØÝÝÝÝ¼ÞÆdefault þ< axis@0 S  \  eÿ axis@1 S  \  eÿ axis@2 S  \  eÿ axis@3 S  \  eÿ backlight0,pwm-backlight ™Q oßa¨µ\backlight1,pwm-backlight ™Q oàa¨µdbattery,simple-battery t=  –“à ³˜–€ ØB`0 þ8€%¿ @6î€`B`0}-ÆÀš¨¯B1Pd@Ýx_?óZ?@U>M8P=¡XK<³F<9øA;¡ <:ê7:aP29Å-9Ž`(9ch#94ˆ8î88�x8H7ä˜ 4”ð3á@µ%gpio-keys-control ,gpio-keys¼áÆdefaultbutton-a Üâ EAST 1button-b Üâ SOUTH 0button-down Üã DPAD-DOWN !button-l1 Üâ TL 6button-l2 Üâ TL2 8button-left Üã DPAD-LEFT "button-menu Üã HOME fbutton-right Üã DPAD-RIGHT #button-r1 Üâ T2 7button-r2 Üâ TR2 9button-select Üâ  SELECT :button-start Üâ  START ;button-thumbl Üã THUMBL =button-thumbr Üã THUMBR >button-up Üã DPAD-UP  button-x Üâ NORTH 3button-y Üâ WEST 4gpio-keys-hall ,gpio-keys¼äÆdefaultlid-switch Ü  LID ÄÕ¢gpio-keys-volume ,gpio-keysé¼åÆdefaultvol-down-key Üâ VOLUMEDOWN rvol-up-key Üâ VOLUMEUP smux-controller ,gpio-muxôââ¼æÆdefaultµÜpwm-leds ,pwm-ledsled-0on%power.ÿ oça¨led-1 %charging.ÿ oèa¨led-2off%status.ÿ oéa¨sdio-pwrseq,mmc-pwrseq-simple Ôext_clock ê¼ëÆdefault=È ÖQµLsound,simple-audio-card¼ìÆdefaulti2s TQ+ ûrk817_extsInternal Speakers\’MICLMic JackHeadphonesHPOLHeadphonesHPORInternal SpeakersHPOLInternal SpeakersHPORC¬MicrophoneMic JackHeadphoneHeadphonesSpeakerInternal Speakerssimple-audio-card,codecLêsimple-audio-card,cpuLíregulator-vdd-lcd0,regulator-fixedÆ Ù ¼îÆdefault ‰vdd_lcd0µ^regulator-state-memáregulator-vccio-lcd0,regulator-fixedÆ Ù ¼ïÆdefault ‰vccio_lcd0µ_regulator-state-memáregulator-vdd-lcd1,regulator-fixedÆ Ù ¼ðÆdefault ‰vdd_lcd1µfregulator-state-memáregulator-vccio-lcd1,regulator-fixedÆ Ù ¼ñÆdefault ‰vccio_lcd1µgregulator-state-memáregulator-vcc3v3-sd,regulator-fixed Ù ¼òÆdefault0 ‰vcc3v3_sdq2Z Y2Z ™µsregulator-vcc-sys,regulator-fixed0q9ûÀY9ûÀ‰vcc_sysµ#pwm-vibrator ,pwm-vibratorÞenable oó† è#regulator-vcc-wifi,regulator-fixedÆ Ù ¼ôÆdefault0q2Z Y2Z  ‰vcc_wifiµP interrupt-parent#address-cells#size-cellscompatiblemodelchassis-typegpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-initial-moderegulator-max-microvoltregulator-min-microvoltregulator-nameregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplycellwise,battery-profilecellwise,monitor-interval-mspower-suppliesdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyvccio-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpvqmmc-supplyno-sdno-sdiodma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsAVDD28-supplyirq-gpiospaneltouchscreen-size-xtouchscreen-size-ytouchscreen-inverted-xtouchscreen-inverted-yVDDIO-supplyuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfstdout-pathio-channel-namesio-channelskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltmux-controlssettle-time-usabs-flatabs-fuzzabs-rangepwmscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsprecharge-current-microampprecharge-upper-limit-microvoltvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0linux,input-typewakeup-event-actionautorepeat#mux-control-cellsmux-gpioscolordefault-statefunctionmax-brightnesspost-power-on-delay-mssimple-audio-card,hp-det-gpiossimple-audio-card,pin-switchessimple-audio-card,routingsimple-audio-card,widgetsenable-active-highgpiopwm-namesvcc-supply