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spi@fe300000 ,rockchip,sfcþ0@ SexvÑclk_sfchclk_sfc¹jÃdefault Bdisabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 SB{}R ëÂn6(|zy{}ÑcorebusaxiblocktimerBokayí u Z  rng@fe388000,rockchip,rk3568-rngþ8€@po Ñcoreahbm Bdisabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ S4B=ARFÏqFÏq?C9Ñmclk_txmclk_rxhclk#k „txPQ •tx-mrx-m~Bokay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA S5BEIRFÏqFÏqGK:Ñmclk_txmclk_rxhclk#kk „rxtxRS •tx-mrx-m~Ãdefault0¹lmnopqrstuvw Bdisabledi2s@fe420000,rockchip,rk3568-i2s-tdmþB S6BMRFÏqOO;Ñmclk_txmclk_rxhclk#kk „txrxT•tx-m~Ãdefault¹xyz{ Bdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC S7SW<Ñmclk_txmclk_rxhclk#kk „txrxUV •tx-mrx-m~ Bdisabledpdm@fe440000,rockchip,rk3568-pdmþD SLZYÑpdm_clkpdm_hclk#k  „rx¹|}~€�ÃdefaultX•pdm-m Bdisabledspdif@fe460000,rockchip,rk3568-spdifþF Sf Ñmclkhclk_\#k „txÃdefault¹‚ Bdisableddma-controller@fe530000,arm,pl330arm,primecellþS@S  Ž  Ñapb_pclk ¥²$dma-controller@fe550000,arm,pl330arm,primecellþU@S Ž  Ñapb_pclk ¥²ki2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ S/HG Ñi2cpclk¹ƒÃdefault Bokayrtc@51 ,nxp,pcf85063Qi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ S0JI Ñi2cpclk¹„Ãdefault  Bdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ S1LK Ñi2cpclk¹…Ãdefault  Bdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] S2NM Ñi2cpclk¹†Ãdefault  Bdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ S3PO Ñi2cpclk¹‡Ãdefault  Bdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` S• Ñtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa SgRQÑspiclkapb_pclk#$$ „txrxÃdefault ¹ˆ‰Š  Bdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb ShTSÑspiclkapb_pclk#$$ „txrxÃdefault ¹‹Œ�  Bdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc SiVUÑspiclkapb_pclk#$$ „txrxÃdefault ¹Ž��  Bdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd SjXWÑspiclkapb_pclk#$$ „txrxÃdefault ¹‘’“  Bdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe SuÑbaudclkapb_pclk#$$ ¹”•–Ãdefault(5Bokay „txrx °bluetooth,brcm,bcm43438-bt—Ñlpo À˜ Ô˜ æ˜Ãdefault ¹™š› õ# œserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf Sv# Ñbaudclkapb_pclk#$$¹�Ãdefault(5Bokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg Sw'$Ñbaudclkapb_pclk#$$¹žÃdefault(5 Bdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh Sx+(Ñbaudclkapb_pclk#$$ ¹ŸÃdefault(5 Bdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi Sy/,Ñbaudclkapb_pclk#$ $ ¹ Ãdefault(5 Bdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj Sz30Ñbaudclkapb_pclk#$ $ ¹¡Ãdefault(5 Bdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk S{74Ñbaudclkapb_pclk#$$¹¢Ãdefault(5Bokayserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl S|;8Ñbaudclkapb_pclk#$$¹£Ãdefault(5 Bdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm S}?<Ñbaudclkapb_pclk#$$¹¤Ãdefault(5 Bdisabledthermal-zonescpu-thermal d $è 2¥tripscpu_alert0 Bp NÐýpassive²¦cpu_alert1 B$ø NÐýpassivecpu_crit Bs NÐ ýcriticalcooling-mapsmap0 Y¦0 ^ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal  $è 2¥tripsgpu-threshold Bp NÐýpassivegpu-target B$ø NÐýpassive²§gpu-crit Bs NÐ ýcriticalcooling-mapsmap0 Y§ ^¨ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq SsBRf@ ®`Ñtsadcapb_pclk�‚×~ msÃdefaultsleep¹© „ª ŽBokay²¥saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr S]Ñsaradcapb_pclk€ •saradc-apb ¤ Bdisabled ¶«pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY Ñpwmpclk¹¬Ãdefault? Bdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY Ñpwmpclk¹­Ãdefault? Bdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Ñpwmpclk¹®Ãdefault? Bdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY Ñpwmpclk¹¯Ãdefault? Bdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ Ñpwmpclk¹°Ãdefault? Bdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ Ñpwmpclk¹±Ãdefault? Bdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Ñpwmpclk¹²Ãdefault? Bdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ Ñpwmpclk¹³Ãdefault? Bdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ Ñpwmpclk¹´Ãdefault? Bdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ Ñpwmpclk¹µÃdefault? Bdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Ñpwmpclk¹¶Ãdefault? Bdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ Ñpwmpclk¹·Ãdefault? Bdisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} ÑrefapbpipeB"RõáÇ•phy ¸ Ô¹ ê Bdisabled²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ ÑrefapbpipeB%RõáÉ•phy ¸ Ôº êBokay2#²phy@fe870000,rockchip,rk3568-csi-dphyþ‡yÑpclk 꺕apb~ Bdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… Ñrefpclkz êþ •apb» Bdisabled²Smipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† Ñrefpclk{ êþ •apb¼ Bdisabled²Tusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠÑphyclk¦clk_usbphy0_480m S‡ õ»ëBokay²host-port ê Bdisabled²otg-port êBokay2¼²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹Ñphyclk¦clk_usbphy1_480m Sˆ õ½ë Bdisabledhost-port ê Bdisabled²otg-port ê Bdisabled²pinctrl,rockchip,rk3568-pinctrl~?\ q²¾gpio@fdd60000,rockchip,gpio-bankýÖ S!.   ¾  !Rg²!nextrst-hog -Í 6nEXTRST @gpio@fe740000,rockchip,gpio-bankþt S"cd  ¾  !Rg²`gpio@fe750000,rockchip,gpio-bankþu S#ef  ¾@  !Rg²˜gpio@fe760000,rockchip,gpio-bankþv S$gh  ¾`  !Rggpio@fe770000,rockchip,gpio-bankþw S%ij  ¾€  !Rgpcfg-pull-up K²Ápcfg-pull-down X²Çpcfg-pull-none g²¿pcfg-pull-none-drv-level-1 g t²Ãpcfg-pull-none-drv-level-2 g t²Âpcfg-pull-none-drv-level-3 g t²Æpcfg-pull-up-drv-level-1 K t²Åpcfg-pull-up-drv-level-2 K t²Àpcfg-pull-none-smt g ƒ²Äacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ˜¿²cpuebcedpdpemmceth0eth1flashfspifspi-pins` ˜¿¿¿¿¿¿²jgmac0gmac1gmac1m0-miim ˜¿¿²Jgmac1m0-clkinout ˜¿²Ngmac1m0-rx-bus20 ˜ ¿ ¿ ¿²Lgmac1m0-tx-bus20 ˜ ¿²Kgmac1m0-rgmii-clk ˜¿Ã²Mgmac1m0-rgmii-bus@ ˜¿¿Â²Ogpuhdmitxhdmitxm0-cec ˜¿²Whdmitx-scl ˜¿²Uhdmitx-sda ˜¿²Vi2c0i2c0-xfer ˜ Ä Ä²i2c1i2c1-xfer ˜ Ä Ä²ƒi2c2i2c2m1-xfer ˜ Ä Ä²„i2c3i2c3m0-xfer ˜ÄIJ…i2c4i2c4m1-xfer ˜ Ä Ä²†i2c5i2c5m0-xfer ˜ Ä Ä²‡i2s1i2s1m1-lrckrx ˜¿²oi2s1m1-lrcktx ˜¿²ni2s1m1-sclkrx ˜¿²mi2s1m1-sclktx ˜¿²li2s1m1-sdi0 ˜¿²pi2s1m1-sdi1 ˜¿²qi2s1m1-sdi2 ˜¿²ri2s1m1-sdi3 ˜¿²si2s1m1-sdo0 ˜¿²ti2s1m1-sdo1 ˜¿²ui2s1m1-sdo2 ˜ ¿²vi2s1m1-sdo3 ˜ ¿²wi2s2i2s2m0-lrcktx ˜¿²yi2s2m0-sclktx ˜¿²xi2s2m0-sdi ˜¿²zi2s2m0-sdo ˜¿²{i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ˜¿²|pdmm0-clk1 ˜¿²}pdmm0-sdi0 ˜ ¿²~pdmm0-sdi1 ˜ ¿²pdmm0-sdi2 ˜ ¿²€pdmm0-sdi3 ˜¿²�pmicpmic-int-l ˜Á²"pmupwm0pwm0m0-pins ˜¿²&pwm1pwm1m0-pins ˜¿²'pwm2pwm2m0-pins ˜¿²(pwm3pwm3-pins ˜¿²)pwm4pwm4-pins ˜¿²¬pwm5pwm5-pins ˜¿²­pwm6pwm6-pins ˜¿²®pwm7pwm7-pins ˜¿²¯pwm8pwm8m0-pins ˜ ¿²°pwm9pwm9m0-pins ˜ ¿²±pwm10pwm10m0-pins ˜ ¿²²pwm11pwm11m0-pins ˜¿²³pwm12pwm12m0-pins ˜¿²´pwm13pwm13m0-pins ˜¿²µpwm14pwm14m0-pins ˜¿²¶pwm15pwm15m0-pins ˜¿²·refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ˜ÀÀÀÀ²asdmmc0-clk ˜À²bsdmmc0-cmd ˜À²csdmmc0-det ˜Á²dsdmmc1sdmmc1-bus4@ ˜ÀÀÀÀ²gsdmmc1-clk ˜À²isdmmc1-cmd ˜À²hsdmmc2spdifspdifm0-tx ˜¿²‚spi0spi0m0-pins0 ˜ ¿¿¿²Šspi0m0-cs0 ˜¿²ˆspi0m0-cs1 ˜¿²‰spi1spi1m0-pins0 ˜ ¿¿¿²�spi1m0-cs0 ˜¿²‹spi1m0-cs1 ˜¿²Œspi2spi2m0-pins0 ˜¿¿¿²�spi2m0-cs0 ˜¿²Žspi2m0-cs1 ˜¿²�spi3spi3m0-pins0 ˜ ¿¿ ¿²“spi3m0-cs0 ˜¿²‘spi3m0-cs1 ˜¿²’tsadctsadc-shutorg ˜¿²©tsadc-pin ˜¿²ªuart0uart0-xfer ˜ÁÁ²%uart1uart1m0-xfer ˜ Á Á²”uart1m0-ctsn ˜¿²•uart1m0-rtsn ˜ ¿²–uart2uart2m0-xfer ˜ÁÁ²�uart3uart3m0-xfer ˜ÁÁ²žuart4uart4m0-xfer ˜ÁÁ²Ÿuart5uart5m0-xfer ˜ÁÁ² uart6uart6m0-xfer ˜ÁÁ²¡uart7uart7m2-xfer ˜ÁÁ²¢uart8uart8m0-xfer ˜ÁÁ²£uart9uart9m0-xfer ˜ÁÁ²¤vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2btbt-enable-h ˜¿²›bt-host-wake-l ˜Ç²™bt-wake-l ˜¿²šledswork-led-enable-h ˜¿²Êdiy-led-enable-h ˜¿²Épciepcie-clkreq-h ˜¿pcie-reset-h ˜ ¿²_sdio-pwrseqwifi-enable-h ˜¿²Ëopp-table-0,operating-points-v2 ¦²opp-408000000 ±Q– ¸ øP øPŒ0 Æœ@opp-600000000 ±#ÃF ¸ øP øPŒ0 Æœ@opp-816000000 ±0£, ¸ øP øPŒ0 Æœ@ ×opp-1104000000 ±AÍ´ ¸ »  » Œ0 Æœ@opp-1416000000 ±Tfr ¸£è£èŒ0 Æœ@opp-1608000000 ±_Ø" ¸ÈàÈàŒ0 Æœ@opp-1800000000 ±kIÒ ¸Œ0Œ0Œ0 Æœ@opp-table-1,operating-points-v2²Aopp-200000000 ± ë ¸ øP øPB@opp-300000000 ±á£ ¸ øP øPB@opp-400000000 ±ׄ ¸ øP øPB@opp-600000000 ±#ÃF ¸ »  » B@opp-700000000 ±)¹' ¸~ð~ðB@opp-800000000 ±/¯ ¸B@B@B@chosen ãserial2:1500000n8external-gmac1-clock ,fixed-clock–sY@ ¦gmac1_clkinë²Ihdmi-con,hdmi-connectorýaportendpointþȲ[leds ,gpio-ledsled-diy ïdiy-led õon Í! heartbeatÃdefault¹É Bokayled-work ïwork-led õoff Í!Ãdefault¹Ê Bokaysdio-pwrseqBokay,mmc-pwrseq-simple— Ñext_clockÃdefault¹Ë ǘ²fregulator-vbus,regulator-fixed¨vbusü·LK@ÏLK@"¼²Ìregulator-vcc5v0-sys,regulator-fixed ¨vcc5v0_sysü·LK@ÏLK@"̲ regulator-vcc3v3-sys,regulator-fixed ¨vcc3v3_sysü·2Z Ï2Z " ²#regulator-vcc12v-dcin,regulator-fixed ¨vcc12v_dcinü··Ï·²Íregulator-vcc-5v,regulator-fixed¨vcc_5vü·LK@ÏLK@"Ͳ¼regulator-vcc-sd-pwr,regulator-fixed ¨vcc_sd_pwrü·2Z Ï2Z "#²e interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2ethernet0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybroken-cdbus-widthcap-sd-highspeeddisable-wpvqmmc-supplyvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr50mmc-hs200-1_8vdma-namesarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsgpio-hogline-nameoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspended