Ð þíØÈ8Í$( ¤Ìì ,radxa,zero-3wrockchip,rk35667Radxa ZERO 3Waliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe310000â/mmc@fe2b0000ç/mmc@fe2c0000cpus cpu@0ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ cpu@100ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ cpu@200ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ cpu@300ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ l3-cache,cache°¼"/@A¨display-subsystem,rockchip,display-subsystemÊfirmwarescmi ,arm,scmi-smcЂÛ protocol@14øá¨hdmi-sound,simple-audio-cardîHDMIi2s8okaysimple-audio-card,codec?simple-audio-card,cpu? pmu,arm,cortex-a55-pmu0IäåæçT psci ,arm,psci-1.0smcreserved-memory gshmem@10f000,arm,scmi-shmemøðn¨timer,arm,armv8-timer0I   uxin24m ,fixed-clockŒn6œxin24má¨xin32k ,fixed-clockŒ€œxin32k¯¹defaultásata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciøü@ü›œ�Çsatapmaliverxoob I_Ó Øsata-phyâô 8disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciøü€ü ¡¢Çsatapmaliverxoob I`Ó Øsata-phyâô 8disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3øüÀ@ I©ü¦§¥Çref_clksuspend_clkbus_clkotg  utmi_wideô”8okayÓ Øusb2-phy3 :high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3øý@ Iªü©ª¨Çref_clksuspend_clkbus_clkhost ÓØusb2-phyusb3-phy  utmi_wideô•8okayinterrupt-controller@fd400000 ,arm,gic-v3 øý@ýF I H]nýAx(ƒg ’¨msi-controller@fd440000,arm,gic-v3-itsøýD’ƒ¢¨Xusb@fd800000 ,generic-ehciøý€ I‚ü½¾¼ÓØusb 8disabledusb@fd840000 ,generic-ohciøý„ Iƒü½¾¼ÓØusb 8disabledusb@fd880000 ,generic-ehciøýˆ I…ü¿À¼ÓØusb 8disabledusb@fd8c0000 ,generic-ohciøýŒ I†ü¿À¼ÓØusb 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8disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×0ü 0 Çpwmpclk¯+¹default5 8disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdøýÙpower-controller!,rockchip,rk3568-power-controller@ ¨power-domain@7øüT,@power-domain@8øüÌÍ T-./@power-domain@9ø üÚÛÜ T012@power-domain@10ø üñòT345678@power-domain@11ø üíT9@power-domain@13üø T:@power-domain@14øü T;<=@power-domain@15øüT>?@AB@gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostøýæ@$I()' [jobmmugpuüÇgpubusô8okay‰CkD¨žvideo-codec@fdea0400,rockchip,rk3568-vpuøýê I‹[vdpuüîï ÇaclkhclkwEô iommu@fdea0800,rockchip,rk3568-iommuøýê@ IŠ Çaclkifaceüîïô ~¨Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaøýë€ IZüóôõÇaclkhclksclk&$% ‹coreaxiahbô video-codec@fdee0000,rockchip,rk3568-vepuøýî I@üýþ ÇaclkhclkwFô iommu@fdee0800,rockchip,rk3568-iommuøýî@ I?üýþ Çaclkifaceô ~¨Fvideo-capture@fdfe0000,rockchip,rk3568-vicapøýþ I’8ÐHᣠüÎÏÐÑÇaclkhclkdclkiclkwGô(÷øùûú‹arsthrstdrstprstirstt  8disabledports port@0øport@1øiommu@fdfe0800,rockchip,rk3568-iommuøýþ I’üÎÏ Çaclkiface~ô— 8disabled¨Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ@ Id üÁÂŽ�Çbiuciuciu-driveciu-sample²½ðÑ€ë‹reset 8disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aøþI [macirqeth_wake_irq@ü†‰‰ÇÃĉÈWÇstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refì ‹stmmacetht ËHÛìIÿJ 8disabledmdio,snps,dwmac-mdio stmmac-axi-config%5¨Hrx-queues-configE¨Iqueue0tx-queues-config[¨Jqueue0vop@fe040000 øþ0þ@qvopgamma-lut I”(üÝÞßàá%Çaclkhclkdclk_vp0dclk_vp1dclk_vp2wKô t 8okay,rockchip,rk3566-vop8ßà]ports ¨port@0ø endpoint@2ø{L¨Tport@1ø port@2ø iommu@fe043e00,rockchip,rk3568-iommu øþ>þ? I”üÝÞ Çaclkiface~ô 8okay¨Kdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ IDÇpclküèØdphyÓMô ‹apbt  8disabledports port@0øport@1ødsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ IEÇpclküéØdphyÓNô ‹apbt  8disabledports port@0øport@1øhdmi@fe0a0000,rockchip,rk3568-dw-hdmiøþ  I-(üæç“(ÚÇiahbisfrcecref¹default ¯OPQô t ‹8okayœR¬S¨ports port@0øendpoint{T¨Lport@1øendpoint{U¨¼qos@fe128000,rockchip,rk3568-qossysconøþ€ ¨,qos@fe138080,rockchip,rk3568-qossysconøþ€€ ¨;qos@fe138100,rockchip,rk3568-qossysconøþ� ¨<qos@fe138180,rockchip,rk3568-qossysconøþ�€ ¨=qos@fe148000,rockchip,rk3568-qossysconøþ€ ¨-qos@fe148080,rockchip,rk3568-qossysconøþ€€ ¨.qos@fe148100,rockchip,rk3568-qossysconøþ� ¨/qos@fe150000,rockchip,rk3568-qossysconøþ ¨9qos@fe158000,rockchip,rk3568-qossysconøþ€ ¨3qos@fe158100,rockchip,rk3568-qossysconøþ� ¨4qos@fe158180,rockchip,rk3568-qossysconøþ�€ ¨5qos@fe158200,rockchip,rk3568-qossysconøþ‚ ¨6qos@fe158280,rockchip,rk3568-qossysconøþ‚€ ¨7qos@fe158300,rockchip,rk3568-qossysconøþƒ ¨8qos@fe180000,rockchip,rk3568-qossysconøþ qos@fe190000,rockchip,rk3568-qossysconøþ ¨>qos@fe190280,rockchip,rk3568-qossysconøþ€ ¨?qos@fe190300,rockchip,rk3568-qossysconøþ ¨@qos@fe190380,rockchip,rk3568-qossysconøþ€ ¨Aqos@fe190400,rockchip,rk3568-qossysconøþ ¨Bqos@fe198000,rockchip,rk3568-qossysconøþ€ ¨:qos@fe1a8000,rockchip,rk3568-qossysconøþ€ ¨0qos@fe1a8080,rockchip,rk3568-qossysconøþ€€ ¨1qos@fe1a8100,rockchip,rk3568-qossysconøþ� ¨2dfi@fe230000,rockchip,rk3568-dfiøþ# I ¼Vpcie@fe260000,rockchip,rk3568-pcie0øÀ@þ&ôqdbiapbconfig<IKJIHG[syspmcmsglegacyerrÉ(ü�‚ƒ„…$Çaclk_mstaclk_slvaclk_dbipclkauxìpci]Ó`æWWWWô#2X:Ó Øpcie-phyôTgôôô ô à@¡‹pipe  8disabledlegacy-interrupt-controller]H IH¨Wmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ+@ Ib ü°±Š‹Çbiuciuciu-driveciu-sample²½ðÑ€Ô‹reset8okayDN_¹default¯YZ[\j]vmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ,@ Ic ü²³Œ�Çbiuciuciu-driveciu-sample²½ðÑ€Ö‹reset8okayDNƒ�¦^±¸¾¹default ¯_`aÌjvspi@fe300000 ,rockchip,sfcøþ0@ IeüxvÇclk_sfchclk_sfc¯b¹default 8disabledmmc@fe310000,rockchip,rk3568-dwcmshcøþ1 I8{}H ëÂn6(ü|zy{}Çcorebusaxiblocktimer8okayDÚ½ ëÂì¸û¾¹default¯cdefjvrng@fe388000,rockchip,rk3568-rngøþ8€@üpo Çcoreahbm 8disabledi2s@fe400000,rockchip,rk3568-i2s-tdmøþ@ I48=AHFÏqFÏqü?C9Çmclk_txmclk_rxhclkg txPQ ‹tx-mrx-mt ‹8okay¨ i2s@fe410000,rockchip,rk3568-i2s-tdmøþA I58EIHFÏqFÏqüGK:Çmclk_txmclk_rxhclkgg rxtxRS ‹tx-mrx-mt ¹default0¯hijklmnopqrs‹ 8disabledi2s@fe420000,rockchip,rk3568-i2s-tdmøþB I68MHFÏqüOO;Çmclk_txmclk_rxhclkgg txrxT‹tx-mt ¹default¯tuvw‹ 8disabledi2s@fe430000,rockchip,rk3568-i2s-tdmøþC I7üSW<Çmclk_txmclk_rxhclkgg txrxUV ‹tx-mrx-mt ‹ 8disabledpdm@fe440000,rockchip,rk3568-pdmøþD ILüZYÇpdm_clkpdm_hclkg  rx¯xyz{|}¹defaultX‹pdm-m‹ 8disabledspdif@fe460000,rockchip,rk3568-spdiføþF If Çmclkhclkü_\g tx¹default¯~‹ 8disableddma-controller@fe530000,arm,pl330arm,primecelløþS@I  ü  Çapb_pclk $¨&dma-controller@fe550000,arm,pl330arm,primecelløþU@I ü  Çapb_pclk $¨gi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþZ I/üHG Çi2cpclk¯¹default  8disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ[ I0üJI Çi2cpclk¯€¹default  8disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ\ I1üLK Çi2cpclk¯�¹default  8disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ] I2üNM Çi2cpclk¯‚¹default  8disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ^ I3üPO Çi2cpclk¯ƒ¹default  8disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtøþ` I•ü Çtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiøþa IgüRQÇspiclkapb_pclk&& txrx¹default ¯„…†  8disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiøþb IhüTSÇspiclkapb_pclk&& txrx¹default ¯‡ˆ‰  8disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiøþc IiüVUÇspiclkapb_pclk&& txrx¹default ¯Š‹Œ  8disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiøþd IjüXWÇspiclkapb_pclk&& txrx¹default ¯�Ž�  8disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartøþe IuüÇbaudclkapb_pclk&& ¯�‘’¹default+8okay /serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartøþf Ivü# Çbaudclkapb_pclk&&¯“¹default+8okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartøþg Iwü'$Çbaudclkapb_pclk&&¯”¹default+ 8disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartøþh Ixü+(Çbaudclkapb_pclk&& ¯•¹default+ 8disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartøþi Iyü/,Çbaudclkapb_pclk& & ¯–¹default+ 8disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþj Izü30Çbaudclkapb_pclk& & ¯—¹default+ 8disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþk I{ü74Çbaudclkapb_pclk&&¯˜¹default+ 8disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþl I|ü;8Çbaudclkapb_pclk&&¯™¹default+ 8disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþm I}ü?<Çbaudclkapb_pclk&&¯š¹default+ 8disabledthermal-zonescpu-thermal ?d Uè c›tripscpu_alert0 sp Ðópassive¨œcpu_alert1 s$ø Ðópassivecpu_crit ss Ð ócriticalcooling-mapsmap0 Šœ0 � ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal ? Uè c›tripsgpu-threshold sp Ðópassivegpu-target s$ø Ðópassive¨�gpu-crit ss Ð ócriticalcooling-mapsmap0 Š� �žÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcøþq Is8Hf@ ®`üÇtsadcapb_pclk�‚×t  žs¹defaultsleep¯Ÿ µ  ¿8okay Õ ì¨›saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcøþr I]üÇsaradcapb_pclk€ ‹saradc-apb 8okay ¡pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY Çpwmpclk¯¢¹default5 8disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY Çpwmpclk¯£¹default5 8disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn üZY Çpwmpclk¯¤¹default5 8disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn0üZY Çpwmpclk¯¥¹default5 8disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ Çpwmpclk¯¦¹default5 8disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ Çpwmpclk¯§¹default5 8disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo ü]\ Çpwmpclk¯¨¹default5 8disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo0ü]\ Çpwmpclk¯©¹default5 8disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ Çpwmpclk¯ª¹default5 8disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ Çpwmpclk¯«¹default5 8disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp ü`_ Çpwmpclk¯¬¹default5 8disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp0ü`_ Çpwmpclk¯­¹default5 8disabledphy@fe830000,rockchip,rk3568-naneng-combphyøþƒü"} Çrefapbpipe8"HõáÇ‹phy %® 7¯ M8okay¨phy@fe840000,rockchip,rk3568-naneng-combphyøþ„ü%~ Çrefapbpipe8%HõáÉ‹phy %® 7° M 8disabled¨phy@fe870000,rockchip,rk3568-csi-dphyøþ‡üyÇpclk Mº‹apbt  8disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyøþ… Çrefpclküz Mô ‹apb» 8disabled¨Mmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyøþ† Çrefpclkü{ Mô ‹apb¼ 8disabled¨Nusb2phy@fe8a0000,rockchip,rk3568-usb2phyøþŠüÇphyclkœclk_usbphy0_480m I‡ X±á8okay¨host-port M8okay¨otg-port M8okay¨usb2phy@fe8b0000,rockchip,rk3568-usb2phyøþ‹üÇphyclkœclk_usbphy1_480m Iˆ X²á 8disabledhost-port M 8disabled¨otg-port M 8disabled¨pinctrl,rockchip,rk3568-pinctrlt ¼V g¨³gpio@fdd60000,rockchip,gpio-bankøýÖ I!ü.  h x³  „H]B �pin-10 [GPIO0_D0]pin-08 [GPIO0_D1]¨"gpio@fe740000,rockchip,gpio-bankøþt I"ücd h x³  „H]S �pin-03 [GPIO1_A0]pin-05 [GPIO1_A1]pin-37 [GPIO1_A4]gpio@fe750000,rockchip,gpio-bankøþu I#üef h x³@  „H] �gpio@fe760000,rockchip,gpio-bankøþv I$ügh h x³`  „H]0 �pin-11 [GPIO3_A1]pin-13 [GPIO3_A2]pin-12 [GPIO3_A3]pin-35 [GPIO3_A4]pin-40 [GPIO3_A5]pin-38 [GPIO3_A6]pin-36 [GPIO3_A7]pin-15 [GPIO3_B0]pin-16 [GPIO3_B1]pin-18 [GPIO3_B2]pin-29 [GPIO3_B3]pin-31 [GPIO3_B4]pin-22 [GPIO3_C1]pin-32 [GPIO3_C2]pin-33 [GPIO3_C3]pin-07 [GPIO3_C4]gpio@fe770000,rockchip,gpio-bankøþw I%üij h x³€  „H]† �pin-27 [GPIO4_B2]pin-28 [GPIO4_B3]pin-23 [GPIO4_C2]pin-19 [GPIO4_C3]pin-21 [GPIO4_C5]pin-24 [GPIO4_C6]pcfg-pull-up  ¨¶pcfg-pull-none ­¨´pcfg-pull-none-drv-level-1 ­ º¨¸pcfg-pull-none-drv-level-2 ­ º¨·pcfg-pull-none-drv-level-3 ­ º¨»pcfg-pull-up-drv-level-1   º¨ºpcfg-pull-up-drv-level-2   º¨µpcfg-pull-none-smt ­ ɨ¹acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 Þ´¨cpuebcedpdpemmcemmc-bus8€ Þ µ µµµµµµµ¨cemmc-clk Þµ¨demmc-cmd Þµ¨eemmc-datastrobe Þ´¨feth0eth1flashfspifspi-pins` Þ´´´´´´¨bgmac0gmac1gpuhdmitxhdmitxm0-cec Þ´¨Qhdmitx-scl Þ´¨Ohdmitx-sda Þ´¨Pi2c0i2c0-xfer Þ ¹ ¹¨!i2c1i2c1-xfer Þ ¹ ¹¨i2c2i2c2m0-xfer Þ ¹¹¨€i2c3i2c3m0-xfer Þ¹¹¨�i2c4i2c4m0-xfer Þ ¹ ¹¨‚i2c5i2c5m0-xfer Þ ¹ ¹¨ƒi2s1i2s1m0-lrckrx Þ´¨ki2s1m0-lrcktx Þ´¨ji2s1m0-sclkrx Þ´¨ii2s1m0-sclktx Þ´¨hi2s1m0-sdi0 Þ ´¨li2s1m0-sdi1 Þ ´¨mi2s1m0-sdi2 Þ ´¨ni2s1m0-sdi3 Þ´¨oi2s1m0-sdo0 Þ´¨pi2s1m0-sdo1 Þ´¨qi2s1m0-sdo2 Þ ´¨ri2s1m0-sdo3 Þ ´¨si2s2i2s2m0-lrcktx Þ´¨ui2s2m0-sclktx Þ´¨ti2s2m0-sdi Þ´¨vi2s2m0-sdo Þ´¨wi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Þ´¨xpdmm0-clk1 Þ´¨ypdmm0-sdi0 Þ ´¨zpdmm0-sdi1 Þ ´¨{pdmm0-sdi2 Þ ´¨|pdmm0-sdi3 Þ´¨}pmicpmic-int-l Þ¶¨#pmupwm0pwm0m0-pins Þ´¨(pwm1pwm1m0-pins Þ´¨)pwm2pwm2m0-pins Þ´¨*pwm3pwm3-pins Þ´¨+pwm4pwm4-pins Þ´¨¢pwm5pwm5-pins Þ´¨£pwm6pwm6-pins Þ´¨¤pwm7pwm7-pins Þ´¨¥pwm8pwm8m0-pins Þ ´¨¦pwm9pwm9m0-pins Þ ´¨§pwm10pwm10m0-pins Þ ´¨¨pwm11pwm11m0-pins Þ´¨©pwm12pwm12m0-pins Þ´¨ªpwm13pwm13m0-pins Þ´¨«pwm14pwm14m0-pins Þ´¨¬pwm15pwm15m0-pins Þ´¨­refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ Þµµµµ¨Ysdmmc0-clk Þµ¨Zsdmmc0-cmd Þµ¨[sdmmc0-det Þ¶¨\sdmmc1sdmmc1-bus4@ Þµµµµ¨_sdmmc1-clk Þµ¨`sdmmc1-cmd Þµ¨asdmmc2spdifspdifm0-tx Þ´¨~spi0spi0m0-pins0 Þ ´´´¨†spi0m0-cs0 Þ´¨„spi0m0-cs1 Þ´¨…spi1spi1m0-pins0 Þ ´´´¨‰spi1m0-cs0 Þ´¨‡spi1m0-cs1 Þ´¨ˆspi2spi2m0-pins0 Þ´´´¨Œspi2m0-cs0 Þ´¨Šspi2m0-cs1 Þ´¨‹spi3spi3m0-pins0 Þ ´´ ´¨�spi3m0-cs0 Þ´¨�spi3m0-cs1 Þ´¨Žtsadctsadc-shutorg Þ´¨Ÿtsadc-pin Þ´¨ uart0uart0-xfer Þ¶¶¨'uart1uart1m0-xfer Þ ¶ ¶¨�uart1m0-ctsn Þ´¨‘uart1m0-rtsn Þ ´¨’uart2uart2m0-xfer Þ¶¶¨“uart3uart3m0-xfer Þ¶¶¨”uart4uart4m0-xfer Þ¶¶¨•uart5uart5m0-xfer Þ¶¶¨–uart6uart6m0-xfer Þ¶¶¨—uart7uart7m0-xfer Þ¶¶¨˜uart8uart8m0-xfer Þ¶¶¨™uart9uart9m0-xfer Þ¶¶¨švopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-led2 Þ´¨½bluetoothbt-reg-on-h Þ´bt-wake-host-h Þ ´host-wake-bt-h Þ ´wifiwifi-reg-on-h Þ´¨Àwifi-wake-host-h Þ´opp-table-0,operating-points-v2 ì¨opp-408000000 ÷Q– þ øP øPŒ0 œ@opp-600000000 ÷#ÃF þ øP øPŒ0 œ@opp-816000000 ÷0£, þ øP øPŒ0 œ@ opp-1104000000 ÷AÍ´ þ »  » Œ0 œ@opp-1416000000 ÷Tfr þ£è£èŒ0 œ@opp-table-1,operating-points-v2¨Copp-200000000 ÷ ë þ øP øPB@opp-300000000 ÷ᣠþ øP øPB@opp-400000000 ÷ׄ þ øP øPB@opp-600000000 ÷#ÃF þ »  » B@opp-700000000 ÷)¹' þ~ð~ðB@chosen )serial2:1500000n8hdmi-con,hdmi-connectoródportendpoint{¼¨Uleds ,gpio-leds¹default¯½led-green 5 ;on Iheartbeat R" Xheartbeatregulator-1v8-vcc,regulator-fixedvcc_1v8"6_w@ww@¾¨regulator-1v8-vcca,regulator-fixed vcca_1v8"6_w@ww@¾¨¡regulator-1v8-vcca-image,regulator-fixedvcca1v8_image"6_w@ww@¾¨Sregulator-3v3-vcc,regulator-fixedvcc_3v3"6_2Z w2Z ]¨regulator-5v0-vcc-sys,regulator-fixedvcc_sys"6_LK@wLK@¨$sdio-pwrseq,mmc-pwrseq-simpleü¿ Çext_clock¹default¯À nd …LK@ ˜"¨^ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104cap-mmc-highspeedmmc-hs200-1_8vno-sdiodma-namesarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsgpio-line-namesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolordefault-statefunctiongpioslinux,default-triggerpost-power-on-delay-mspower-off-delay-usreset-gpios