Ð þíÕÂ8Ê�( 2ÊX ,radxa,zero-3erockchip,rk35667Radxa ZERO 3Ealiases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe2b0000cpus cpu@0ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ cpu@100ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ cpu@200ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ cpu@300ìcpu,arm,cortex-a55øüpsci €-@?€L€Y@k€x‰�¨ l3-cache,cache°¼"/@A¨display-subsystem,rockchip,display-subsystemÊfirmwarescmi ,arm,scmi-smcЂÛ protocol@14øá¨hdmi-sound,simple-audio-cardîHDMIi2s8okaysimple-audio-card,codec?simple-audio-card,cpu? pmu,arm,cortex-a55-pmu0IäåæçT psci ,arm,psci-1.0smcreserved-memory gshmem@10f000,arm,scmi-shmemøðn¨timer,arm,armv8-timer0I   uxin24m ,fixed-clockŒn6œxin24má¨xin32k ,fixed-clockŒ€œxin32k¯¹defaultásata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciøü@ü›œ�Çsatapmaliverxoob I_Ó Øsata-phyâô 8disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciøü€ü ¡¢Çsatapmaliverxoob I`Ó Øsata-phyâô 8disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3øüÀ@ I©ü¦§¥Çref_clksuspend_clkbus_clkotg  utmi_wideô”8okayÓ Øusb2-phy3 :high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3øý@ Iªü©ª¨Çref_clksuspend_clkbus_clkhost ÓØusb2-phyusb3-phy  utmi_wideô•8okayinterrupt-controller@fd400000 ,arm,gic-v3 øý@ýF I H]nýAx(ƒg ’¨msi-controller@fd440000,arm,gic-v3-itsøýD’ƒ¢¨ausb@fd800000 ,generic-ehciøý€ I‚ü½¾¼ÓØusb 8disabledusb@fd840000 ,generic-ohciøý„ Iƒü½¾¼ÓØusb 8disabledusb@fd880000 ,generic-ehciøýˆ I…ü¿À¼ÓØusb 8disabledusb@fd8c0000 ,generic-ohciøýŒ I†ü¿À¼ÓØusb 8disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdøý¨_io-domains&,rockchip,rk3568-pmu-io-voltage-domain8okay­»É×åósyscon@fdc50000øýÅ ,rockchip,rk3566-pipe-grfsyscon¨­syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdøýƨ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconøýȨ®syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconøýɨ¯syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconøýÊ€¨°syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconøýÊ€€¨±clock-controller@fdd00000,rockchip,rk3568-pmucruøýÐá+¨clock-controller@fdd20000,rockchip,rk3568-cruøýÒüÇxin24má+8 H€G†Œ ëÂ]t ¨i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cøýÔ I.ü- Çi2cpclk¯!¹default 8okaypmic@20,rockchip,rk817ø áœrk817-clkout1rk817-clkout2"I¹default¯#�™§$³$¿$Ë$×$ã$ï$û$%regulatorsDCDC_REG1 vdd_logic"6H_¡ w™p�qregulator-state-mem¤½ » DCDC_REG2 vdd_gpu_npu"6H_¡ w™p�q¨Dregulator-state-mem¤DCDC_REG3vcc_ddr"6Hregulator-state-memÙDCDC_REG4 vcc3v3_sys"6H_2Z w2Z ¨fregulator-state-memÙ½2Z LDO_REG1 vcca1v8_pmu"6_w@ww@¨regulator-state-memÙ½w@LDO_REG2 vdda_0v9"6_ » w » ¨[regulator-state-mem¤LDO_REG3 vdda0v9_pmu"6_ » w » regulator-state-memÙ½ » LDO_REG4 vccio_acodec"6_2Z w2Z ¨regulator-state-mem¤LDO_REG5 vccio_sd"6_w@w2Z ¨regulator-state-mem¤LDO_REG6 vcc3v3_pmu"6_2Z w2Z ¨regulator-state-memÙ½2Z LDO_REG7 vcc_1v8_p"6_w@ww@¨½regulator-state-mem¤LDO_REG8 vcc1v8_dvp"6_w@ww@regulator-state-mem¤LDO_REG9 vcc2v8_dvp"6_*¹€w*¹€regulator-state-mem¤BOOST vcc5v_midu"6_LK@wLK@¨%regulator-state-mem¤OTG_SWITCHvbusregulator-state-mem¤regulator@40,rockchip,rk8600ø@ñvdd_cpu"6_ ß4w5°�ü$¨regulator-state-mem¤serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartøýÕ Itü ,Çbaudclkapb_pclk&&¯'¹default+ 8disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×ü 0 Çpwmpclk¯(¹default5 8disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×ü 0 Çpwmpclk¯)¹default5 8disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý× ü 0 Çpwmpclk¯*¹default5 8disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×0ü 0 Çpwmpclk¯+¹default5 8disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdøýÙpower-controller!,rockchip,rk3568-power-controller@ ¨power-domain@7øüT,@power-domain@8øüÌÍ T-./@power-domain@9ø üÚÛÜ T012@power-domain@10ø üñòT345678@power-domain@11ø üíT9@power-domain@13üø T:@power-domain@14øü T;<=@power-domain@15øüT>?@AB@gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostøýæ@$I()' [jobmmugpuüÇgpubusô8okay‰CkD¨�video-codec@fdea0400,rockchip,rk3568-vpuøýê I‹[vdpuüîï ÇaclkhclkwEô iommu@fdea0800,rockchip,rk3568-iommuøýê@ IŠ Çaclkifaceüîïô ~¨Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaøýë€ IZüóôõÇaclkhclksclk&$% ‹coreaxiahbô video-codec@fdee0000,rockchip,rk3568-vepuøýî I@üýþ ÇaclkhclkwFô iommu@fdee0800,rockchip,rk3568-iommuøýî@ I?üýþ Çaclkifaceô ~¨Fvideo-capture@fdfe0000,rockchip,rk3568-vicapøýþ I’8ÐHᣠüÎÏÐÑÇaclkhclkdclkiclkwGô(÷øùûú‹arsthrstdrstprstirstt  8disabledports port@0øport@1øiommu@fdfe0800,rockchip,rk3568-iommuøýþ I’üÎÏ Çaclkiface~ô— 8disabled¨Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ@ Id üÁÂŽ�Çbiuciuciu-driveciu-sample²½ðÑ€ë‹reset 8disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aøþI [macirqeth_wake_irq@ü†‰‰ÇÃĉÈWÇstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refì ‹stmmacetht ËHÛìIÿJ8okay8‰†]‡Åinput(K 3rgmii-id<¹default¯LMNOPQmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22ø¹default¯RGN WÃP iS¨Kstmmac-axi-configu�¨Hrx-queues-configŸ¨Iqueue0tx-queues-configµ¨Jqueue0vop@fe040000 øþ0þ@Ëvopgamma-lut I”(üÝÞßàá%Çaclkhclkdclk_vp0dclk_vp1dclk_vp2wTô t 8okay,rockchip,rk3566-vop8ßà]ports ¨port@0ø endpoint@2øÕU¨]port@1ø port@2ø iommu@fe043e00,rockchip,rk3568-iommu øþ>þ? I”üÝÞ Çaclkiface~ô 8okay¨Tdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ IDÇpclküèØdphyÓVô ‹apbt  8disabledports port@0øport@1ødsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ IEÇpclküéØdphyÓWô ‹apbt  8disabledports port@0øport@1øhdmi@fe0a0000,rockchip,rk3568-dw-hdmiøþ  I-(üæç“(ÚÇiahbisfrcecref¹default ¯XYZô t å8okayö[\¨ports port@0øendpointÕ]¨Uport@1øendpointÕ^¨»qos@fe128000,rockchip,rk3568-qossysconøþ€ ¨,qos@fe138080,rockchip,rk3568-qossysconøþ€€ ¨;qos@fe138100,rockchip,rk3568-qossysconøþ� ¨<qos@fe138180,rockchip,rk3568-qossysconøþ�€ ¨=qos@fe148000,rockchip,rk3568-qossysconøþ€ ¨-qos@fe148080,rockchip,rk3568-qossysconøþ€€ ¨.qos@fe148100,rockchip,rk3568-qossysconøþ� ¨/qos@fe150000,rockchip,rk3568-qossysconøþ ¨9qos@fe158000,rockchip,rk3568-qossysconøþ€ ¨3qos@fe158100,rockchip,rk3568-qossysconøþ� ¨4qos@fe158180,rockchip,rk3568-qossysconøþ�€ ¨5qos@fe158200,rockchip,rk3568-qossysconøþ‚ ¨6qos@fe158280,rockchip,rk3568-qossysconøþ‚€ ¨7qos@fe158300,rockchip,rk3568-qossysconøþƒ ¨8qos@fe180000,rockchip,rk3568-qossysconøþ qos@fe190000,rockchip,rk3568-qossysconøþ ¨>qos@fe190280,rockchip,rk3568-qossysconøþ€ ¨?qos@fe190300,rockchip,rk3568-qossysconøþ ¨@qos@fe190380,rockchip,rk3568-qossysconøþ€ ¨Aqos@fe190400,rockchip,rk3568-qossysconøþ ¨Bqos@fe198000,rockchip,rk3568-qossysconøþ€ ¨:qos@fe1a8000,rockchip,rk3568-qossysconøþ€ ¨0qos@fe1a8080,rockchip,rk3568-qossysconøþ€€ ¨1qos@fe1a8100,rockchip,rk3568-qossysconøþ� ¨2dfi@fe230000,rockchip,rk3568-dfiøþ# I _pcie@fe260000,rockchip,rk3568-pcie0øÀ@þ&ôËdbiapbconfig<IKJIHG[syspmcmsglegacyerr#(ü�‚ƒ„…$Çaclk_mstaclk_slvaclk_dbipclkauxìpci]-`@````N_n}Œa”Ó Øpcie-phyôTgôôô ô à@¡‹pipe  8disabledlegacy-interrupt-controller]H IH¨`mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ+@ Ib ü°±Š‹Çbiuciuciu-driveciu-sample²½ðÑ€Ô‹reset8okayž¨¹¹default¯bcdeÄfÐmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ,@ Ic ü²³Œ�Çbiuciuciu-driveciu-sample²½ðÑ€Ö‹reset 8disabledspi@fe300000 ,rockchip,sfcøþ0@ IeüxvÇclk_sfchclk_sfc¯g¹default 8disabledmmc@fe310000,rockchip,rk3568-dwcmshcøþ1 I8{}H ëÂn6(ü|zy{}Çcorebusaxiblocktimer 8disabledrng@fe388000,rockchip,rk3568-rngøþ8€@üpo Çcoreahbm 8disabledi2s@fe400000,rockchip,rk3568-i2s-tdmøþ@ I48=AHFÏqFÏqü?C9Çmclk_txmclk_rxhclkhÝtxPQ ‹tx-mrx-mt å8okay¨ i2s@fe410000,rockchip,rk3568-i2s-tdmøþA I58EIHFÏqFÏqüGK:Çmclk_txmclk_rxhclkhhÝrxtxRS ‹tx-mrx-mt ¹default0¯ijklmnopqrstå 8disabledi2s@fe420000,rockchip,rk3568-i2s-tdmøþB I68MHFÏqüOO;Çmclk_txmclk_rxhclkhhÝtxrxT‹tx-mt ¹default¯uvwxå 8disabledi2s@fe430000,rockchip,rk3568-i2s-tdmøþC I7üSW<Çmclk_txmclk_rxhclkhhÝtxrxUV ‹tx-mrx-mt å 8disabledpdm@fe440000,rockchip,rk3568-pdmøþD ILüZYÇpdm_clkpdm_hclkh Ýrx¯yz{|}~¹defaultX‹pdm-må 8disabledspdif@fe460000,rockchip,rk3568-spdiføþF If Çmclkhclkü_\hÝtx¹default¯å 8disableddma-controller@fe530000,arm,pl330arm,primecelløþS@I çü  Çapb_pclkþ¨&dma-controller@fe550000,arm,pl330arm,primecelløþU@Içü  Çapb_pclkþ¨hi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþZ I/üHG Çi2cpclk¯€¹default  8disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ[ I0üJI Çi2cpclk¯�¹default  8disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ\ I1üLK Çi2cpclk¯‚¹default  8disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ] I2üNM Çi2cpclk¯ƒ¹default  8disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ^ I3üPO Çi2cpclk¯„¹default  8disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtøþ` I•ü Çtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiøþa IgüRQÇspiclkapb_pclk&&Ýtxrx¹default ¯…†‡  8disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiøþb IhüTSÇspiclkapb_pclk&&Ýtxrx¹default ¯ˆ‰Š  8disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiøþc IiüVUÇspiclkapb_pclk&&Ýtxrx¹default ¯‹Œ�  8disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiøþd IjüXWÇspiclkapb_pclk&&Ýtxrx¹default ¯Ž��  8disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartøþe IuüÇbaudclkapb_pclk&&¯‘¹default+ 8disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartøþf Ivü# Çbaudclkapb_pclk&&¯’¹default+8okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartøþg Iwü'$Çbaudclkapb_pclk&&¯“¹default+ 8disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartøþh Ixü+(Çbaudclkapb_pclk&& ¯”¹default+ 8disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartøþi Iyü/,Çbaudclkapb_pclk& & ¯•¹default+ 8disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþj Izü30Çbaudclkapb_pclk& & ¯–¹default+ 8disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþk I{ü74Çbaudclkapb_pclk&&¯—¹default+ 8disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþl I|ü;8Çbaudclkapb_pclk&&¯˜¹default+ 8disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþm I}ü?<Çbaudclkapb_pclk&&¯™¹default+ 8disabledthermal-zonescpu-thermal d è -štripscpu_alert0 =p IÐópassive¨›cpu_alert1 =$ø IÐópassivecpu_crit =s IÐ ócriticalcooling-mapsmap0 T›0 Y ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal  è -štripsgpu-threshold =p IÐópassivegpu-target =$ø IÐópassive¨œgpu-crit =s IÐ ócriticalcooling-mapsmap0 Tœ Y�ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcøþq Is8Hf@ ®`üÇtsadcapb_pclk�‚×t  hs¹defaultsleep¯ž Ÿ ‰8okay Ÿ ¶¨šsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcøþr I]üÇsaradcapb_pclk€ ‹saradc-apb Ñ8okay ã pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY Çpwmpclk¯¡¹default5 8disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY Çpwmpclk¯¢¹default5 8disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn üZY Çpwmpclk¯£¹default5 8disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn0üZY Çpwmpclk¯¤¹default5 8disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ Çpwmpclk¯¥¹default5 8disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ Çpwmpclk¯¦¹default5 8disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo ü]\ Çpwmpclk¯§¹default5 8disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo0ü]\ Çpwmpclk¯¨¹default5 8disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ Çpwmpclk¯©¹default5 8disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ Çpwmpclk¯ª¹default5 8disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp ü`_ Çpwmpclk¯«¹default5 8disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp0ü`_ Çpwmpclk¯¬¹default5 8disabledphy@fe830000,rockchip,rk3568-naneng-combphyøþƒü"} Çrefapbpipe8"HõáÇ‹phy ï­ ® 8okay¨phy@fe840000,rockchip,rk3568-naneng-combphyøþ„ü%~ Çrefapbpipe8%HõáÉ‹phy ï­ ¯  8disabled¨phy@fe870000,rockchip,rk3568-csi-dphyøþ‡üyÇpclk º‹apbt  8disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyøþ… Çrefpclküz ô ‹apb» 8disabled¨Vmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyøþ† Çrefpclkü{ ô ‹apb¼ 8disabled¨Wusb2phy@fe8a0000,rockchip,rk3568-usb2phyøþŠüÇphyclkœclk_usbphy0_480m I‡ "°á8okay¨host-port 8okay¨otg-port 8okay¨usb2phy@fe8b0000,rockchip,rk3568-usb2phyøþ‹üÇphyclkœclk_usbphy1_480m Iˆ "±á 8disabledhost-port  8disabled¨otg-port  8disabled¨pinctrl,rockchip,rk3568-pinctrlt _ g¨²gpio@fdd60000,rockchip,gpio-bankøýÖ I!ü.  2 B²  NH]B Zpin-10 [GPIO0_D0]pin-08 [GPIO0_D1]¨"gpio@fe740000,rockchip,gpio-bankøþt I"ücd 2 B²  NH]S Zpin-03 [GPIO1_A0]pin-05 [GPIO1_A1]pin-37 [GPIO1_A4]gpio@fe750000,rockchip,gpio-bankøþu I#üef 2 B²@  NH] Zgpio@fe760000,rockchip,gpio-bankøþv I$ügh 2 B²`  NH]0 Zpin-11 [GPIO3_A1]pin-13 [GPIO3_A2]pin-12 [GPIO3_A3]pin-35 [GPIO3_A4]pin-40 [GPIO3_A5]pin-38 [GPIO3_A6]pin-36 [GPIO3_A7]pin-15 [GPIO3_B0]pin-16 [GPIO3_B1]pin-18 [GPIO3_B2]pin-29 [GPIO3_B3]pin-31 [GPIO3_B4]pin-22 [GPIO3_C1]pin-32 [GPIO3_C2]pin-33 [GPIO3_C3]pin-07 [GPIO3_C4]¨Sgpio@fe770000,rockchip,gpio-bankøþw I%üij 2 B²€  NH]† Zpin-27 [GPIO4_B2]pin-28 [GPIO4_B3]pin-23 [GPIO4_C2]pin-19 [GPIO4_C3]pin-21 [GPIO4_C5]pin-24 [GPIO4_C6]pcfg-pull-up j¨µpcfg-pull-none w¨³pcfg-pull-none-drv-level-1 w „¨·pcfg-pull-none-drv-level-2 w „¨¶pcfg-pull-none-drv-level-3 w „¨ºpcfg-pull-up-drv-level-1 j „¨¹pcfg-pull-up-drv-level-2 j „¨´pcfg-pull-none-smt w “¨¸acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ¨³¨cpuebcedpdpemmceth0eth1flashfspifspi-pins` ¨³³³³³³¨ggmac0gmac1gmac1m1-miim ¨³³¨Lgmac1m1-clkinout ¨³¨Qgmac1m1-rx-bus20 ¨³³ ³¨Ngmac1m1-tx-bus20 ¨¶¶³¨Mgmac1m1-rgmii-clk ¨³·¨Ogmac1m1-rgmii-bus@ ¨³³¶¶¨Pgmac1-rstn ¨³¨Rgpuhdmitxhdmitxm0-cec ¨³¨Zhdmitx-scl ¨³¨Xhdmitx-sda ¨³¨Yi2c0i2c0-xfer ¨ ¸ ¸¨!i2c1i2c1-xfer ¨ ¸ ¸¨€i2c2i2c2m0-xfer ¨ ¸¸¨�i2c3i2c3m0-xfer ¨¸¸¨‚i2c4i2c4m0-xfer ¨ ¸ ¸¨ƒi2c5i2c5m0-xfer ¨ ¸ ¸¨„i2s1i2s1m0-lrckrx ¨³¨li2s1m0-lrcktx ¨³¨ki2s1m0-sclkrx ¨³¨ji2s1m0-sclktx ¨³¨ii2s1m0-sdi0 ¨ ³¨mi2s1m0-sdi1 ¨ ³¨ni2s1m0-sdi2 ¨ ³¨oi2s1m0-sdi3 ¨³¨pi2s1m0-sdo0 ¨³¨qi2s1m0-sdo1 ¨³¨ri2s1m0-sdo2 ¨ ³¨si2s1m0-sdo3 ¨ ³¨ti2s2i2s2m0-lrcktx ¨³¨vi2s2m0-sclktx ¨³¨ui2s2m0-sdi ¨³¨wi2s2m0-sdo ¨³¨xi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ¨³¨ypdmm0-clk1 ¨³¨zpdmm0-sdi0 ¨ ³¨{pdmm0-sdi1 ¨ ³¨|pdmm0-sdi2 ¨ ³¨}pdmm0-sdi3 ¨³¨~pmicpmic-int-l ¨µ¨#pmupwm0pwm0m0-pins ¨³¨(pwm1pwm1m0-pins ¨³¨)pwm2pwm2m0-pins ¨³¨*pwm3pwm3-pins ¨³¨+pwm4pwm4-pins ¨³¨¡pwm5pwm5-pins ¨³¨¢pwm6pwm6-pins ¨³¨£pwm7pwm7-pins ¨³¨¤pwm8pwm8m0-pins ¨ ³¨¥pwm9pwm9m0-pins ¨ ³¨¦pwm10pwm10m0-pins ¨ ³¨§pwm11pwm11m0-pins ¨³¨¨pwm12pwm12m0-pins ¨³¨©pwm13pwm13m0-pins ¨³¨ªpwm14pwm14m0-pins ¨³¨«pwm15pwm15m0-pins ¨³¨¬refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ¨´´´´¨bsdmmc0-clk ¨´¨csdmmc0-cmd ¨´¨dsdmmc0-det ¨µ¨esdmmc1sdmmc2spdifspdifm0-tx ¨³¨spi0spi0m0-pins0 ¨ ³³³¨‡spi0m0-cs0 ¨³¨…spi0m0-cs1 ¨³¨†spi1spi1m0-pins0 ¨ ³³³¨Šspi1m0-cs0 ¨³¨ˆspi1m0-cs1 ¨³¨‰spi2spi2m0-pins0 ¨³³³¨�spi2m0-cs0 ¨³¨‹spi2m0-cs1 ¨³¨Œspi3spi3m0-pins0 ¨ ³³ ³¨�spi3m0-cs0 ¨³¨Žspi3m0-cs1 ¨³¨�tsadctsadc-shutorg ¨³¨žtsadc-pin ¨³¨Ÿuart0uart0-xfer ¨µµ¨'uart1uart1m0-xfer ¨ µ µ¨‘uart2uart2m0-xfer ¨µµ¨’uart3uart3m0-xfer ¨µµ¨“uart4uart4m0-xfer ¨µµ¨”uart5uart5m0-xfer ¨µµ¨•uart6uart6m0-xfer ¨µµ¨–uart7uart7m0-xfer ¨µµ¨—uart8uart8m0-xfer ¨µµ¨˜uart9uart9m0-xfer ¨µµ¨™vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-led2 ¨³¨¼opp-table-0,operating-points-v2 ¶¨opp-408000000 ÁQ– È øP øPŒ0 Öœ@opp-600000000 Á#ÃF È øP øPŒ0 Öœ@opp-816000000 Á0£, È øP øPŒ0 Öœ@ çopp-1104000000 ÁAÍ´ È »  » Œ0 Öœ@opp-1416000000 ÁTfr È£è£èŒ0 Öœ@opp-table-1,operating-points-v2¨Copp-200000000 Á ëÂ È øP øPB@opp-300000000 Áá£ È øP øPB@opp-400000000 Áׄ È øP øPB@opp-600000000 Á#ÃF È »  » B@opp-700000000 Á)¹' È~ð~ðB@chosen óserial2:1500000n8hdmi-con,hdmi-connectoródportendpointÕ»¨^leds ,gpio-leds¹default¯¼led-green ÿ on heartbeat o" heartbeatregulator-1v8-vcc,regulator-fixedvcc_1v8"6_w@ww@½¨regulator-1v8-vcca,regulator-fixed vcca_1v8"6_w@ww@½¨ regulator-1v8-vcca-image,regulator-fixedvcca1v8_image"6_w@ww@½¨\regulator-3v3-vcc,regulator-fixedvcc_3v3"6_2Z w2Z f¨regulator-5v0-vcc-sys,regulator-fixedvcc_sys"6_LK@wLK@¨$ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplydma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsgpio-line-namesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolordefault-statefunctionlinux,default-trigger