Ð þíÚ8Ïp( ­Ï8 ,qnap,ts133rockchip,rk3566 7Qnap TS-133-2G NAS System 1-Bayaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe310000â/i2c@fe5a0000/rtc@51ç/ethernet@fe010000cpus cpu@0ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ cpu@100ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ cpu@200ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ cpu@300ñcpu,arm,cortex-a55ýpsci%€2@D€Q€^@p€}Ž¢­ l3-cache,cacheµÁ'4@F­display-subsystem,rockchip,display-subsystemÏfirmwarescmi ,arm,scmi-smcÕ‚à protocol@14ýæ­hdmi-sound,simple-audio-cardóHDMI i2s# =disabledsimple-audio-card,codecDsimple-audio-card,cpuD pmu,arm,cortex-a55-pmu0NäåæçY psci ,arm,psci-1.0smcreserved-memory lshmem@10f000,arm,scmi-shmemýðs­timer,arm,armv8-timer0N   zxin24m ,fixed-clock‘n6¡xin24mæ­xin32k ,fixed-clock‘€¡xin32k´¾defaultæsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciýü@›œ�Ìsatapmaliverxoob N_Ø Ýsata-phyçù =disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciýü€ ¡¢Ìsatapmaliverxoob N`Ø Ýsata-phyçù=okayusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3ýüÀ@ N©¦§¥Ìref_clksuspend_clkbus_clkhost utmi_wideù”=okayØ Ýusb2-phy8 ?high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ýý@ Nª©ª¨Ìref_clksuspend_clkbus_clkhost ØÝusb2-phyusb3-phy utmi_wideù•=okayinterrupt-controller@fd400000 ,arm,gic-v3 ýý@ýF N MbsýA}(ˆl —­msi-controller@fd440000,arm,gic-v3-itsýýD—ˆ§­Uusb@fd800000 ,generic-ehciýý€ N‚½¾¼ØÝusb =disabledusb@fd840000 ,generic-ohciýý„ Nƒ½¾¼ØÝusb =disabledusb@fd880000 ,generic-ehciýýˆ N…¿À¼ØÝusb =disabledusb@fd8c0000 ,generic-ohciýýŒ N†¿À¼ØÝusb =disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýý­Sio-domains&,rockchip,rk3568-pmu-io-voltage-domain=okay²Àsyscon@fdc50000ýýÅ ,rockchip,rk3566-pipe-grfsyscon­£syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýýÆ­syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýýÈ­¤syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýýÉ­¥syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýýÊ€­¦syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýýÊ€€­¨clock-controller@fdd00000,rockchip,rk3568-pmucruýýÐæÎ­clock-controller@fdd20000,rockchip,rk3568-cruýýÒÌxin24mæÎÛ ë€G†Œ ë­i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýýÔ N.- Ìi2cpclk´¾default =okaypmic@20,rockchip,rk809ý Næ¾default´$<HT`lx„�œ¨regulatorsDCDC_REG1 ¶vdd_logicÅÙë¡ ™p2qregulator-state-memGDCDC_REG2¶vdd_gpuÅë¡ ™p2q­?regulator-state-memGDCDC_REG3¶vcc_ddrÅÙëregulator-state-mem`DCDC_REG4¶vdd_npuë¡ ™p2qregulator-state-memGDCDC_REG5¶vcc_1v8ÅÙw@w@­regulator-state-memGLDO_REG1¶vdda0v9_imageÅ »  » regulator-state-memGLDO_REG2 ¶vdda_0v9ÅÙ »  » regulator-state-memGLDO_REG3 ¶vdda0v9_pmuÅÙ »  » regulator-state-mem`x » LDO_REG4 ¶vccio_acodecÅÙ2Z 2Z regulator-state-memGLDO_REG5 ¶vccio_sdw@2Z regulator-state-memGLDO_REG6 ¶vcc3v3_pmuÅÙ2Z 2Z regulator-state-mem`x2Z LDO_REG7 ¶vcca_1v8ÅÙw@w@regulator-state-memGLDO_REG8 ¶vcca1v8_pmuÅÙw@w@regulator-state-mem`xw@LDO_REG9¶vcca1v8_imageÅw@w@regulator-state-memGSWITCH_REG1¶vcc_3v3ÅÙregulator-state-memGSWITCH_REG2 ¶vcc3v3_sdÅÙregulator-state-memGregulator@40,silergy,syr827ý@”¶vdd_cpuÅÙ ß45°2ü± ­serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýýÕ Nt ,Ìbaudclkapb_pclk¼!!´"¾defaultÁÎ=okaymcu,qnap,ts133-mcufan-0 Ø@Y€¦ÌÝî­�nvmem-layout ,fixed-layout serial-number@0ýext-port@22ý"mac@24 ,mac-baseý$çmac@35 ,mac-baseý5çmac@46 ,mac-baseýFçmac@57 ,mac-baseýWçmac@68 ,mac-baseýhçmac@79 ,mac-baseýyçmac@8a ,mac-baseýŠçmac@9b ,mac-baseý›çpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 Ìpwmpclk´#¾defaultù =disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 Ìpwmpclk´$¾defaultù =disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý×  0 Ìpwmpclk´%¾defaultù =disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý×0 0 Ìpwmpclk´&¾defaultù =disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýýÙpower-controller!,rockchip,rk3568-power-controller ­power-domain@7ý'power-domain@8ýÌÍ ()*power-domain@9ý ÚÛÜ +,-power-domain@10ý ñò./0123power-domain@11ý í4power-domain@13ý 5power-domain@14ý 678power-domain@15ý9:;<=gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýýæ@$N()' jobmmugpuÌgpubusù=okayŽ>/?­”video-codec@fdea0400,rockchip,rk3568-vpuýýê N‹vdpuîï Ìaclkhclk;@ù iommu@fdea0800,rockchip,rk3568-iommuýýê@ NŠ Ìaclkifaceîïù B­@rga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýýë€ NZóôõÌaclkhclksclk&$% Ocoreaxiahbù video-codec@fdee0000,rockchip,rk3568-vepuýýî N@ýþ Ìaclkhclk;Aù iommu@fdee0800,rockchip,rk3568-iommuýýî@ N?ýþ Ìaclkifaceù B­Avideo-capture@fdfe0000,rockchip,rk3568-vicapýýþ N’ÛÐëᣠÎÏÐÑÌaclkhclkdclkiclk;Bù(÷øùûúOarsthrstdrstprstirst =disabledports port@0ýport@1ýiommu@fdfe0800,rockchip,rk3568-iommuýýþ N’ÎÏ ÌaclkifaceBù[ =disabled­Bmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ@ Nd ÁÂŽ�Ìbiuciuciu-driveciu-samplev�ðÑ€ëOreset =disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aýþN macirqeth_wake_irq@†‰‰ÇÃĉÈWÌstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refì Ostmmaceth�CŸ°DÃEÖ=okayÛ‰†‡ÅësY@ßoutputìF ÷rgmii-id¾default´GHIJKmdio,snps,dwmac-mdio ethernet-phy@3,ethernet-phy-ieee802.3-c22ý´L¾default' ­Fstmmac-axi-config&6­Crx-queues-configF­Dqueue0tx-queues-config\­Equeue0vop@fe040000 ýþ0þ@rvopgamma-lut N”(ÝÞßàá%Ìaclkhclkdclk_vp0dclk_vp1dclk_vp2;Mù  =disabled,rockchip,rk3566-vopports ­port@0ý port@1ý port@2ý iommu@fe043e00,rockchip,rk3568-iommu ýþ>þ? N”ÝÞ ÌaclkifaceBù  =disabled­Mdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiýþ NDÌpclkèÝdphyØNù Oapb =disabledports port@0ýport@1ýdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiýþ NEÌpclkéÝdphyØOù Oapb =disabledports port@0ýport@1ýhdmi@fe0a0000,rockchip,rk3568-dw-hdmiýþ  N-(æç“(ÚÌiahbisfrcecref¾default ´PQRù Á| =disabled­ports port@0ýport@1ýqos@fe128000,rockchip,rk3568-qossysconýþ€ ­'qos@fe138080,rockchip,rk3568-qossysconýþ€€ ­6qos@fe138100,rockchip,rk3568-qossysconýþ� ­7qos@fe138180,rockchip,rk3568-qossysconýþ�€ ­8qos@fe148000,rockchip,rk3568-qossysconýþ€ ­(qos@fe148080,rockchip,rk3568-qossysconýþ€€ ­)qos@fe148100,rockchip,rk3568-qossysconýþ� ­*qos@fe150000,rockchip,rk3568-qossysconýþ ­4qos@fe158000,rockchip,rk3568-qossysconýþ€ ­.qos@fe158100,rockchip,rk3568-qossysconýþ� ­/qos@fe158180,rockchip,rk3568-qossysconýþ�€ ­0qos@fe158200,rockchip,rk3568-qossysconýþ‚ ­1qos@fe158280,rockchip,rk3568-qossysconýþ‚€ ­2qos@fe158300,rockchip,rk3568-qossysconýþƒ ­3qos@fe180000,rockchip,rk3568-qossysconýþ qos@fe190000,rockchip,rk3568-qossysconýþ ­9qos@fe190280,rockchip,rk3568-qossysconýþ€ ­:qos@fe190300,rockchip,rk3568-qossysconýþ ­;qos@fe190380,rockchip,rk3568-qossysconýþ€ ­<qos@fe190400,rockchip,rk3568-qossysconýþ ­=qos@fe198000,rockchip,rk3568-qossysconýþ€ ­5qos@fe1a8000,rockchip,rk3568-qossysconýþ€ ­+qos@fe1a8080,rockchip,rk3568-qossysconýþ€€ ­,qos@fe1a8100,rockchip,rk3568-qossysconýþ� ­-dfi@fe230000,rockchip,rk3568-dfiýþ# N �Spcie@fe260000,rockchip,rk3568-pcie0ýÀ@þ&ôrdbiapbconfig<NKJIHGsyspmcmsglegacyerrš(�‚ƒ„…$Ìaclk_mstaclk_slvaclk_dbipclkauxñpcib¤`·TTTTÅÖåôU Ø Ýpcie-phyùTlôôô ô à@¡Opipe  =disabledlegacy-interrupt-controllerbM NH­Tmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ+@ Nb °±Š‹Ìbiuciuciu-driveciu-samplev�ðÑ€ÔOreset =disabledmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcýþ,@ Nc ²³Œ�Ìbiuciuciu-driveciu-samplev�ðÑ€ÖOreset =disabledspi@fe300000 ,rockchip,sfcýþ0@ NexvÌclk_sfchclk_sfc´V¾default =disabledmmc@fe310000,rockchip,rk3568-dwcmshcýþ1 NÛ{}ë ëÂn6(|zy{}Ìcorebusaxiblocktimer=okay� ë¾default´WXYZrng@fe388000,rockchip,rk3568-rngýþ8€@po Ìcoreahbm =disabledi2s@fe400000,rockchip,rk3568-i2s-tdmýþ@ N4Û=AëFÏqFÏq?C9Ìmclk_txmclk_rxhclk¼[-txPQ Otx-mrx-m| =disabled­ i2s@fe410000,rockchip,rk3568-i2s-tdmýþA N5ÛEIëFÏqFÏqGK:Ìmclk_txmclk_rxhclk¼[[-rxtxRS Otx-mrx-m¾default0´\]^_`abcdefg| =disabledi2s@fe420000,rockchip,rk3568-i2s-tdmýþB N6ÛMëFÏqOO;Ìmclk_txmclk_rxhclk¼[[-txrxTOtx-m¾default´hijk| =disabledi2s@fe430000,rockchip,rk3568-i2s-tdmýþC N7SW<Ìmclk_txmclk_rxhclk¼[[-txrxUV Otx-mrx-m| =disabledpdm@fe440000,rockchip,rk3568-pdmýþD NLZYÌpdm_clkpdm_hclk¼[ -rx´lmnopq¾defaultXOpdm-m| =disabledspdif@fe460000,rockchip,rk3568-spdifýþF Nf Ìmclkhclk_\¼[-tx¾default´r| =disableddma-controller@fe530000,arm,pl330arm,primecellýþS@N 7  Ìapb_pclkN­!dma-controller@fe550000,arm,pl330arm,primecellýþU@N7  Ìapb_pclkN­[i2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþZ N/HG Ìi2cpclk´s¾default =okayrtc@51,microcrystal,rv8263ýQ¨eeprom@54,giantec,gt24c04aatmel,24c04ýTYVPD_MB_mvi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ[ N0JI Ìi2cpclk´t¾default  =disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ\ N1LK Ìi2cpclk´u¾default  =disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ] N2NM Ìi2cpclk´v¾default  =disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ^ N3PO Ìi2cpclk´w¾default  =disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtýþ` N• Ìtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiýþa NgRQÌspiclkapb_pclk¼!!-txrx¾default ´xyz  =disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiýþb NhTSÌspiclkapb_pclk¼!!-txrx¾default ´{|}  =disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiýþc NiVUÌspiclkapb_pclk¼!!-txrx¾default ´~€  =disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiýþd NjXWÌspiclkapb_pclk¼!!-txrx¾default ´�‚ƒ  =disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartýþe NuÌbaudclkapb_pclk¼!!´„¾defaultÁÎ =disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartýþf Nv# Ìbaudclkapb_pclk¼!!´…¾defaultÁÎ=okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartýþg Nw'$Ìbaudclkapb_pclk¼!!´†¾defaultÁÎ =disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartýþh Nx+(Ìbaudclkapb_pclk¼!! ´‡¾defaultÁÎ =disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartýþi Ny/,Ìbaudclkapb_pclk¼! ! ´ˆ¾defaultÁÎ =disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþj Nz30Ìbaudclkapb_pclk¼! ! ´‰¾defaultÁÎ =disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþk N{74Ìbaudclkapb_pclk¼!!´Š¾defaultÁÎ =disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþl N|;8Ìbaudclkapb_pclk¼!!´‹¾defaultÁÎ =disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartýþm N}?<Ìbaudclkapb_pclk¼!!´Œ¾defaultÁÎ =disabledthermal-zonescpu-thermal€d–è¤�tripscpu_alert0´pÀÐøpassive­Žcpu_alert1´$øÀÐøpassivecpu_crit´sÀÐ øcriticalcase-fan0Àдˆ¸øactive­�case-fan1Àд¯Èøactive­‘case-fan2Àдýèøactive­’cooling-mapsmap0ËŽ0Ð ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿmap1 Ð�ÿÿÿÿË�map2 Ð�Ë‘map3 Ð�ÿÿÿÿË’gpu-thermal€–è¤�tripsgpu-threshold´pÀÐøpassivegpu-target´$øÀÐøpassive­“gpu-crit´sÀÐ øcriticalcooling-mapsmap0Ë“ Дÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcýþq NsÛëf@ ®`Ìtsadcapb_pclk�‚×ßs¾defaultsleep´•ö– =okay  -­�saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcýþr N]Ìsaradcapb_pclk€ Osaradc-apb H =disabledpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþnZY Ìpwmpclk´—¾defaultù =disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþnZY Ìpwmpclk´˜¾defaultù =disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþn ZY Ìpwmpclk´™¾defaultù =disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþn0ZY Ìpwmpclk´š¾defaultù =disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo]\ Ìpwmpclk´›¾defaultù =disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo]\ Ìpwmpclk´œ¾defaultù =disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo ]\ Ìpwmpclk´�¾defaultù =disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþo0]\ Ìpwmpclk´ž¾defaultù =disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp`_ Ìpwmpclk´Ÿ¾defaultù =disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp`_ Ìpwmpclk´ ¾defaultù =disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp `_ Ìpwmpclk´¡¾defaultù =disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmýþp0`_ Ìpwmpclk´¢¾defaultù =disabledphy@fe830000,rockchip,rk3568-naneng-combphyýþƒ"} ÌrefapbpipeÛ"ëõáÇOphy Z£ l¤ ‚=okay­phy@fe840000,rockchip,rk3568-naneng-combphyýþ„%~ ÌrefapbpipeÛ%ëõáÉOphy Z£ l¥ ‚=okay­phy@fe870000,rockchip,rk3568-csi-dphyýþ‡yÌpclk ‚ºOapb =disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyýþ… Ìrefpclkz ‚ù Oapb» =disabled­Nmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyýþ† Ìrefpclk{ ‚ù Oapb¼ =disabled­Ousb2phy@fe8a0000,rockchip,rk3568-usb2phyýþŠÌphyclk¡clk_usbphy0_480m N‡ �¦æ=okay­host-port ‚=okay �§­otg-port ‚=okay �§­usb2phy@fe8b0000,rockchip,rk3568-usb2phyýþ‹Ìphyclk¡clk_usbphy1_480m Nˆ �¨æ =disabledhost-port ‚ =disabled­otg-port ‚ =disabled­pinctrl,rockchip,rk3568-pinctrl�S l­©gpio@fdd60000,rockchip,gpio-bankýýÖ N!.  ¨ ¸©  ÄMb­gpio@fe740000,rockchip,gpio-bankýþt N"cd ¨ ¸©  ÄMb­³gpio@fe750000,rockchip,gpio-bankýþu N#ef ¨ ¸©@  ÄMbgpio@fe760000,rockchip,gpio-bankýþv N$gh ¨ ¸©`  ÄMbgpio@fe770000,rockchip,gpio-bankýþw N%ij ¨ ¸©€  ÄMbpcfg-pull-up Э¬pcfg-pull-none Ý­ªpcfg-pull-none-drv-level-1 Ý ê­®pcfg-pull-none-drv-level-2 Ý ê­­pcfg-pull-none-drv-level-3 Ý ê­±pcfg-pull-up-drv-level-1 Ð ê­°pcfg-pull-up-drv-level-2 Ð ê­«pcfg-pull-none-smt Ý ù­¯acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ª­cpuebcedpdpemmcemmc-bus8€  « «««««««­Wemmc-clk «­Xemmc-cmd «­Yemmc-datastrobe ª­Zeth0eth1flashfspifspi-pins` ªªªªªª­Vgmac0gmac1gmac1m1-miim ªª­Ggmac1m1-rx-bus20 ªª ª­Igmac1m1-tx-bus20 ­­ª­Hgmac1m1-rgmii-clk ª®­Jgmac1m1-rgmii-bus@ ªª­­­Keth-phy0-reset-pin ¬­Lgpuhdmitxhdmitxm0-cec ª­Rhdmitx-scl ª­Phdmitx-sda ª­Qi2c0i2c0-xfer  ¯ ¯­i2c1i2c1-xfer  ¯ ¯­si2c2i2c2m0-xfer  ¯¯­ti2c3i2c3m0-xfer ¯¯­ui2c4i2c4m0-xfer  ¯ ¯­vi2c5i2c5m0-xfer  ¯ ¯­wi2s1i2s1m0-lrckrx ª­_i2s1m0-lrcktx ª­^i2s1m0-sclkrx ª­]i2s1m0-sclktx ª­\i2s1m0-sdi0  ª­`i2s1m0-sdi1  ª­ai2s1m0-sdi2  ª­bi2s1m0-sdi3 ª­ci2s1m0-sdo0 ª­di2s1m0-sdo1 ª­ei2s1m0-sdo2  ª­fi2s1m0-sdo3  ª­gi2s2i2s2m0-lrcktx ª­ii2s2m0-sclktx ª­hi2s2m0-sdi ª­ji2s2m0-sdo ª­ki2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ª­lpdmm0-clk1 ª­mpdmm0-sdi0  ª­npdmm0-sdi1  ª­opdmm0-sdi2  ª­ppdmm0-sdi3 ª­qpmicpmic-int-l ¬­pmupwm0pwm0m0-pins ª­#pwm1pwm1m0-pins ª­$pwm2pwm2m0-pins ª­%pwm3pwm3-pins ª­&pwm4pwm4-pins ª­—pwm5pwm5-pins ª­˜pwm6pwm6-pins ª­™pwm7pwm7-pins ª­špwm8pwm8m0-pins  ª­›pwm9pwm9m0-pins  ª­œpwm10pwm10m0-pins  ª­�pwm11pwm11m0-pins ª­žpwm12pwm12m0-pins ª­Ÿpwm13pwm13m0-pins ª­ pwm14pwm14m0-pins ª­¡pwm15pwm15m0-pins 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0rtc0ethernet0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellsvccio4-supplyvccio6-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shiftcooling-levels#nvmem-cell-cells#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthnon-removabledma-namesarm,pl330-periph-burst#dma-cellslabelnum-addressespagesizeread-onlypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathlinux,codecolorfunctionlinux,default-triggerenable-active-highgpio