Ð þíèÄ8Ú°(Úx #,powkiddy,rgb10max3rockchip,rk35667handsetDPowkiddy RGB10MAX3aliasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000�/i2c@fe5e0000†/serial@fdd50000Ž/serial@fe650000–/serial@fe660000ž/serial@fe670000¦/serial@fe680000®/serial@fe690000¶/serial@fe6a0000¾/serial@fe6b0000Æ/serial@fe6c0000Î/serial@fe6d0000Ö/spi@fe610000Û/spi@fe620000à/spi@fe630000å/spi@fe640000ê/mmc@fe2b0000ï/mmc@fe2c0000ô/mmc@fe000000cpus cpu@0ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ cpu@100ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ cpu@200ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ cpu@300ùcpu,arm,cortex-a55 psci-€:@L€Y€f@x€…–ªµ l3-cache,cache½É/<@Nµdisplay-subsystem,rockchip,display-subsystem×firmwarescmi ,arm,scmi-smcÝ‚è protocol@14îµhdmi-sound,simple-audio-cardûHDMIi2s+Eokaysimple-audio-card,codecLsimple-audio-card,cpuL pmu,arm,cortex-a55-pmu0Väåæça psci ,arm,psci-1.0&smcreserved-memory tshmem@10f000,arm,scmi-shmemð{µtimer,arm,armv8-timer0V   ‚xin24m ,fixed-clock™n6©xin24mîµxin32k ,fixed-clock™€©xin32k¼Ædefaultîsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ ›œ�Ôsatapmaliverxoob V_à åsata-phyï Edisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€  ¡¢Ôsatapmaliverxoob V`à åsata-phyï Edisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ V© ¦§¥Ôref_clksuspend_clkbus_clk peripheral utmi_wide ”'Eokayà åusb2-phy@ Ghigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ Vª ©ª¨Ôref_clksuspend_clkbus_clkhost àåusb2-phyusb3-phy utmi_wide •'Eokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF V Uj{ýA…(�t Ÿµmsi-controller@fd440000,arm,gic-v3-itsýDŸ�¯µdusb@fd800000 ,generic-ehciý€ V‚ ½¾¼àåusb Edisabledusb@fd840000 ,generic-ohciý„ Vƒ ½¾¼àåusb Edisabledusb@fd880000 ,generic-ehciýˆ V… ¿À¼àåusbEokayusb@fd8c0000 ,generic-ohciýŒ V† ¿À¼àåusbEokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýµbio-domains&,rockchip,rk3568-pmu-io-voltage-domainEokayºÈÖäòsyscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsysconµ­syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƵsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȵ®syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɵ¯syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€µ°syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€µ±clock-controller@fdd00000,rockchip,rk3568-pmucruýÐî*µclock-controller@fdd20000,rockchip,rk3568-cruýÒ Ôxin24mî* 7G€G†Œ 눶\sµi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ V. - Ôi2cpclk¼ Ædefault Eokaypmic@20,rockchip,rk817 !V©rk808-clkout1rk808-clkout2Ômclk H7H\–î€Ædefault¼"#‘Ÿ$«$·$Ã$Ï$Û$ç$ó$ÿ%µÈregulatorsDCDC_REG1 1¡ I™paqv �vdd_logicregulator-state-memœµ » DCDC_REG2 1¡ I™paqv�vdd_gpuµEregulator-state-memœDCDC_REG3 v�vcc_ddrregulator-state-memÑDCDC_REG4 12Z I2Z v�vcc_3v3µregulator-state-memѵ2Z LDO_REG1 1w@Iw@ �vcca1v8_pmuµNregulator-state-memѵw@LDO_REG2 1 » I »  �vdda_0v9regulator-state-memœLDO_REG3 1 » I »  �vdda0v9_pmuregulator-state-memѵ » LDO_REG4 12Z I2Z  �vccio_acodecµregulator-state-memœLDO_REG5 1w@I2Z  �vccio_sdµregulator-state-memœLDO_REG6 12Z I2Z  �vcc3v3_pmuµregulator-state-memѵ2Z LDO_REG7 1w@Iw@�vcc_1v8µregulator-state-memœLDO_REG8 1w@I2Z  �vcc1v8_dvpµregulator-state-memœLDO_REG9 1*¹€I*¹€ �vcc2v8_dvpregulator-state-memœBOOST 1G·`IReÀ�boostµ%regulator-state-memœOTG_SWITCH �otg_switchregulator-state-memœchargeré&û'“àD† regulator@40 ,fcs,fan53555@k 1 ß4I5°�vdd_cpuaüˆ$µregulator-state-memœserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ Vt  ,Ôbaudclkapb_pclk“''¼(Ædefault˜¥ Edisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Ôpwmpclk¼)Ædefault¯EokayµÇpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Ôpwmpclk¼*Ædefault¯ Edisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0 Ôpwmpclk¼+Ædefault¯ Edisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0 Ôpwmpclk¼,Ædefault¯ Edisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerº µpower-domain@7 Î-ºpower-domain@8 ÌÍ Î./0ºpower-domain@9  ÚÛÜ Î123ºpower-domain@10  ñòÎ456789ºpower-domain@11  íÎ:ºpower-domain@13  Î;ºpower-domain@14  Î<=>ºpower-domain@15 Î?@ABCºgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$V()' Õjobmmugpu ÔgpubusEokay–DåEµžvideo-codec@fdea0400,rockchip,rk3568-vpuýê V‹Õvdpu îï ÔaclkhclkñF iommu@fdea0800,rockchip,rk3568-iommuýê@ VŠ Ôaclkiface îï øµFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ VZ óôõÔaclkhclksclk &$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepuýî V@ ýþ ÔaclkhclkñG iommu@fdee0800,rockchip,rk3568-iommuýî@ V? ýþ Ôaclkiface øµGvideo-capture@fdfe0000,rockchip,rk3568-vicapýþ V’7ÐGᣠ ÎÏÐÑÔaclkhclkdclkiclkñH( ÷øùûúarsthrstdrstprstirsts Edisabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommuýþ V’ ÎÏ Ôaclkifaceø EdisabledµHmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ Vd  ÁÂŽ�Ôbiuciuciu-driveciu-sample,7ðÑ€ ëresetEokayEO`mƒIŽ ¼JKLÆdefaultœM¨Nethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþV Õmacirqeth_wake_irq@ †‰‰ÇÃĉÈWÔstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref ì stmmacethsµOÅÖPéQü Edisabledmdio,snps,dwmac-mdio stmmac-axi-configµOrx-queues-config/µPqueue0tx-queues-configEµQqueue0vop@fe040000 þ0þ@[vopgamma-lut V”( ÝÞßàá%Ôaclkhclkdclk_vp0dclk_vp1dclk_vp2ñR sEokay,rockchip,rk3566-vop7ßà\ports µport@0 endpoint@2eSµ`port@1 endpoint@4eTµVport@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? V” ÝÞ Ôaclkifaceø EokayµRdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ VDÔpclk èådphyàU apb sEokay ports port@0endpointeVµTport@1endpointeWµ\panel@0,powkiddy,rgb10max3-paneluXY¼ZÆdefault Œ[˜�Yportendpointe\µWdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ VEÔpclk éådphyà] apb s Edisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  V-( æç“(ÚÔiahbisfrcecrefÆdefault¼^ ˜s€Eokay¡_µports port@0endpointe`µSport@1endpointeaµÄqos@fe128000,rockchip,rk3568-qossysconþ€ µ-qos@fe138080,rockchip,rk3568-qossysconþ€€ µ<qos@fe138100,rockchip,rk3568-qossysconþ� µ=qos@fe138180,rockchip,rk3568-qossysconþ�€ µ>qos@fe148000,rockchip,rk3568-qossysconþ€ µ.qos@fe148080,rockchip,rk3568-qossysconþ€€ µ/qos@fe148100,rockchip,rk3568-qossysconþ� µ0qos@fe150000,rockchip,rk3568-qossysconþ µ:qos@fe158000,rockchip,rk3568-qossysconþ€ µ4qos@fe158100,rockchip,rk3568-qossysconþ� µ5qos@fe158180,rockchip,rk3568-qossysconþ�€ µ6qos@fe158200,rockchip,rk3568-qossysconþ‚ µ7qos@fe158280,rockchip,rk3568-qossysconþ‚€ µ8qos@fe158300,rockchip,rk3568-qossysconþƒ µ9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ µ?qos@fe190280,rockchip,rk3568-qossysconþ€ µ@qos@fe190300,rockchip,rk3568-qossysconþ µAqos@fe190380,rockchip,rk3568-qossysconþ€ µBqos@fe190400,rockchip,rk3568-qossysconþ µCqos@fe198000,rockchip,rk3568-qossysconþ€ µ;qos@fe1a8000,rockchip,rk3568-qossysconþ€ µ1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ µ2qos@fe1a8100,rockchip,rk3568-qossysconþ� µ3dfi@fe230000,rockchip,rk3568-dfiþ# V ­bpcie@fe260000,rockchip,rk3568-pcie0À@þ&ô[dbiapbconfig<VKJIHGÕsyspmcmsglegacyerrº( �‚ƒ„…$Ôaclk_mstaclk_slvaclk_dbipclkauxùpcijÄ`×ccccåö   #d +à åpcie-phyTtôôô ô à@ ¡pipe  Edisabledlegacy-interrupt-controllerjU VHµcmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ Vb  °±Š‹Ôbiuciuciu-driveciu-sample,7ðÑ€ ÔresetEokayEO 5! >¼efghÆdefault Iœ¨mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ Vc  ²³Œ�Ôbiuciuciu-driveciu-sample,7ðÑ€ ÖresetEokayEO 5i  >¼jklmÆdefault Iœ¨spi@fe300000 ,rockchip,sfcþ0@ Ve xvÔclk_sfchclk_sfc¼nÆdefault Edisabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 V7{}G ëÂn6( |zy{}Ôcorebusaxiblocktimer Edisabledrng@fe388000,rockchip,rk3568-rngþ8€@ po Ôcoreahb m Edisabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ V47=AGFÏqFÏq ?C9Ômclk_txmclk_rxhclk“o Wtx PQ tx-mrx-ms€Eokayµ i2s@fe410000,rockchip,rk3568-i2s-tdmþA V57EIGFÏqFÏq GK:Ômclk_txmclk_rxhclk“oo Wrxtx RS tx-mrx-msÆdefault¼pqrs€Eokay aµÊi2s@fe420000,rockchip,rk3568-i2s-tdmþB V67MGFÏq OO;Ômclk_txmclk_rxhclk“oo Wtxrx Ttx-msÆdefault¼tuvw€ Edisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC V7 SW<Ômclk_txmclk_rxhclk“oo Wtxrx UV tx-mrx-ms€ Edisabledpdm@fe440000,rockchip,rk3568-pdmþD VL ZYÔpdm_clkpdm_hclk“o  Wrx¼xyz{|}Ædefault Xpdm-m€ Edisabledspdif@fe460000,rockchip,rk3568-spdifþF Vf Ômclkhclk _\“o WtxÆdefault¼~€ Edisableddma-controller@fe530000,arm,pl330arm,primecellþS@V  |   Ôapb_pclk “µ'dma-controller@fe550000,arm,pl330arm,primecellþU@V |   Ôapb_pclk “µoi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ V/ HG Ôi2cpclk¼Ædefault  Edisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ V0 JI Ôi2cpclk¼€Ædefault  Edisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ V1 LK Ôi2cpclk¼�Ædefault  Edisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] V2 NM Ôi2cpclk¼‚Ædefault  Edisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ V3 PO Ôi2cpclk¼ƒÆdefault Eokayµ_watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` V•  Ôtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa Vg RQÔspiclkapb_pclk“'' WtxrxÆdefault ¼„…†  Edisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb Vh TSÔspiclkapb_pclk“'' WtxrxÆdefault ¼‡ˆ‰  Edisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc Vi VUÔspiclkapb_pclk“'' WtxrxÆdefault ¼Š‹Œ  Edisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd Vj XWÔspiclkapb_pclk“'' WtxrxÆdefault ¼�Ž�  Edisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe Vu Ôbaudclkapb_pclk“'' ¼�‘’Ædefault˜¥Eokay žbluetooth,realtek,rtl8723ds-bt ®[ À[ Í[serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf Vv # Ôbaudclkapb_pclk“''¼“Ædefault˜¥ Edisabledserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg Vw '$Ôbaudclkapb_pclk“''¼”Ædefault˜¥ Edisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh Vx +(Ôbaudclkapb_pclk“'' ¼•Ædefault˜¥ Edisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi Vy /,Ôbaudclkapb_pclk“' ' ¼–Ædefault˜¥ Edisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj Vz 30Ôbaudclkapb_pclk“' ' ¼—Ædefault˜¥ Edisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk V{ 74Ôbaudclkapb_pclk“''¼˜Ædefault˜¥ Edisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl V| ;8Ôbaudclkapb_pclk“''¼™Ædefault˜¥ Edisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm V} ?<Ôbaudclkapb_pclk“''¼šÆdefault˜¥ Edisabledthermal-zonescpu-thermal Ýd óè ›tripscpu_alert0 p Ð?passiveµœcpu_alert1 $ø Ð?passivecpu_crit s Ð ?criticalcooling-mapsmap0 (œ0 - ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal Ý óè ›tripsgpu-threshold p Ð?passivegpu-target $ø Ð?passiveµ�gpu-crit s Ð ?criticalcooling-mapsmap0 (� -žÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq Vs7Gf@ ®` Ôtsadcapb_pclk �‚×s <sÆdefaultsleep¼Ÿ S  ]Eokay s е›saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr V] Ôsaradcapb_pclk € saradc-apb ¥Eokay ·µ¾pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Ôpwmpclk¼¡Ædefault¯EokayµÀpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Ôpwmpclk¼¢Ædefault¯ Edisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY Ôpwmpclk¼£Ædefault¯EokayµÅpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY Ôpwmpclk¼¤Ædefault¯EokayµÆpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Ôpwmpclk¼¥Ædefault¯ Edisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Ôpwmpclk¼¦Ædefault¯ Edisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\ Ôpwmpclk¼§Ædefault¯ Edisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\ Ôpwmpclk¼¨Ædefault¯ Edisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Ôpwmpclk¼©Ædefault¯ Edisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Ôpwmpclk¼ªÆdefault¯ Edisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_ Ôpwmpclk¼«Ædefault¯ Edisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_ Ôpwmpclk¼¬Ædefault¯ Edisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "} Ôrefapbpipe7"Gõá Çphy í Õ® ëEokayµphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~ Ôrefapbpipe7%Gõá Éphy í Õ¯ ë Edisabledµphy@fe870000,rockchip,rk3568-csi-dphyþ‡ yÔpclk ë ºapbs Edisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… Ôrefpclk z ë apb »EokayµUmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† Ôrefpclk { ë apb ¼ Edisabledµ]usb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ Ôphyclk©clk_usbphy0_480m V‡ ö°îEokayµhost-port ë Edisabledotg-port ëEokayµusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹ Ôphyclk©clk_usbphy1_480m Vˆ ö±îEokayhost-port ëEokayµotg-port ë Edisabledµpinctrl,rockchip,rk3568-pinctrls­b tµ²gpio@fdd60000,rockchip,gpio-bankýÖ V! .   ²  "Ujµ!gpio@fe740000,rockchip,gpio-bankþt V" cd  ²  "Ujgpio@fe750000,rockchip,gpio-bankþu V# ef  ²@  "Ujµigpio@fe760000,rockchip,gpio-bankþv V$ gh  ²`  "UjµÂgpio@fe770000,rockchip,gpio-bankþw V% ij  ²€  "Ujµ[pcfg-pull-up .µµpcfg-pull-none ;µ³pcfg-pull-none-drv-level-1 ; Hµ·pcfg-pull-none-drv-level-2 ; Hµ¶pcfg-pull-none-drv-level-3 ; Hµºpcfg-pull-up-drv-level-1 . Hµ¹pcfg-pull-up-drv-level-2 . Hµ´pcfg-pull-none-smt ; Wµ¸pcfg-output-low lµ»acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 w³µcpuebcedpdpemmceth0eth1flashfspifspi-pins` w³³³³³³µngmac0gmac1gpuhdmitxhdmitxm0-cec w³µ^i2c0i2c0-xfer w ¸ ¸µ i2c1i2c1-xfer w ¸ ¸µi2c2i2c2m0-xfer w ¸¸µ€i2c3i2c3m0-xfer w¸¸µ�i2c4i2c4m0-xfer w ¸ ¸µ‚i2c5i2c5m1-xfer w¸¸µƒi2s1i2s1m0-lrcktx w³µqi2s1m0-mclk w³µ"i2s1m0-sclktx w³µpi2s1m0-sdi0 w ³µri2s1m0-sdo0 w³µsi2s2i2s2m0-lrcktx w³µui2s2m0-sclktx w³µti2s2m0-sdi w³µvi2s2m0-sdo w³µwi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk w³µxpdmm0-clk1 w³µypdmm0-sdi0 w ³µzpdmm0-sdi1 w ³µ{pdmm0-sdi2 w ³µ|pdmm0-sdi3 w³µ}pmicpmic-int-l wµµ#pmupwm0pwm0m1-pins w³µ)pwm1pwm1m0-pins w³µ*pwm2pwm2m0-pins w³µ+pwm3pwm3-pins w³µ,pwm4pwm4-pins w³µ¡pwm5pwm5-pins w³µ¢pwm6pwm6-pins w³µ£pwm7pwm7-pins w³µ¤pwm8pwm8m0-pins w ³µ¥pwm9pwm9m0-pins w ³µ¦pwm10pwm10m0-pins w ³µ§pwm11pwm11m0-pins w³µ¨pwm12pwm12m0-pins w³µ©pwm13pwm13m0-pins w³µªpwm14pwm14m0-pins w³µ«pwm15pwm15m0-pins w³µ¬refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ w´´´´µesdmmc0-clk w´µfsdmmc0-cmd w´µgsdmmc0-det wµµhsdmmc1sdmmc1-bus4@ w´´´´µjsdmmc1-clk w´µlsdmmc1-cmd w´µksdmmc1-det w µµmsdmmc2sdmmc2m0-bus4@ w´´´´µJsdmmc2m0-clk w´µLsdmmc2m0-cmd w´µKspdifspdifm0-tx w³µ~spi0spi0m0-pins0 w ³³³µ†spi0m0-cs0 w³µ„spi0m0-cs1 w³µ…spi1spi1m0-pins0 w ³³³µ‰spi1m0-cs0 w³µ‡spi1m0-cs1 w³µˆspi2spi2m0-pins0 w³³³µŒspi2m0-cs0 w³µŠspi2m0-cs1 w³µ‹spi3spi3m0-pins0 w ³³ ³µ�spi3m0-cs0 w³µ�spi3m0-cs1 w³µŽtsadctsadc-shutorg w³µŸtsadc-pin w³µ uart0uart0-xfer wµµµ(uart1uart1m1-xfer wµµµ�uart1m1-ctsn w³µ‘uart1m1-rtsn w³µ’uart2uart2m0-xfer wµµµ“uart3uart3m0-xfer wµµµ”uart4uart4m0-xfer wµµµ•uart5uart5m0-xfer wµµµ–uart6uart6m0-xfer wµµµ—uart7uart7m0-xfer wµµµ˜uart8uart8m0-xfer wµµµ™uart9uart9m0-xfer wµµµšvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-btnsbtn-pins-ctrl wµµµµµµ µ µ µ µ µµµµµµµÁbtn-pins-vol wµµµÃjoy-muxjoy-mux-en w »µ½gpio-lcdlcd-rst w³µZsdio-pwrseqwifi-enable-h w³µÉvcc3v3-lcdvcc-lcd-h w³µËvcc-wifivcc-wifi-h w³µÌopp-table-0,operating-points-v2 …µopp-408000000 �Q– — øP øPŒ0 ¥œ@opp-600000000 �#ÃF — øP øPŒ0 ¥œ@opp-816000000 �0£, — øP øPŒ0 ¥œ@ ¶opp-1104000000 �AÍ´ — »  » Œ0 ¥œ@opp-1416000000 �Tfr —£è£èŒ0 ¥œ@opp-1608000000 �_Ø" —ÈàÈàŒ0 ¥œ@opp-1800000000 �kIÒ —Œ0Œ0Œ0 ¥œ@opp-table-1,operating-points-v2µDopp-200000000 � ë — øP øPB@opp-300000000 �ᣠ— øP øPB@opp-400000000 �ׄ — øP øPB@opp-600000000 �#ÃF — »  » B@opp-700000000 �)¹' —~ð~ðB@opp-800000000 �/¯ —B@B@B@adc-joystick ,adc-joystick ¼¼¼¼¼½Ædefault Î< axis@0 Ü  å  îÿ øaxis@1 Ü  å  îÿ øaxis@2 Ü  å  îÿ øaxis@3 Ü  å  îÿ øadc-mux,io-channel-mux Åleft_xright_xleft_yright_y ¥ ¾ parent ¿ !dµ¼backlight,pwm-backlight 0$ =Àa¨µXbattery,simple-battery B0˜ d“à �„€ ¦@Ù� ÌÉ ó?¨à 3á@ -¨ B?¨àd>p`_=‘¸Z<áðU<¸P;nØK:ÆàF:A9gP<8§è78À27¦-7_È(7!H#6æ°6˜�6+05²5Ø 4u°3á@µ&gpio-keys-control ,gpio-keys¼ÁÆdefaultbutton-a ’ WEAST ø1button-b ’ WSOUTH ø0button-down ’ WDPAD-DOWN ø!button-l1 ’  WTL ø6button-l2 ’  WTL2 ø8button-left ’ WDPAD-LEFT ø"button-r1 ’  WTR ø7button-r2 ’  WTR2 ø9button-right ’ WDPAD-RIGHT ø#button-select ’ WSELECT ø:button-start ’  WSTART ø;button-thumbl ’ WTHUMBL ø=button-thumbr ’ WTHUMBR ø>button-up ’ WDPAD-UP ø button-x ’ WNORTH ø3button-y ’ WWEST ø4gpio-keys-vol ,gpio-keys ]¼ÃÆdefaultbutton-vol-down ’ WVOLUMEDOWN ørbutton-vol-up ’ WVOLUMEUP øsmux-controller ,gpio-mux h!! rµ¿hdmi-con,hdmi-connector¡_?cportendpointeĵapwm-leds ,pwm-ledsled-0 … ‹power ”ÿ =Åa¨ £onled-1 … ‹status ”ÿ =Æa¨ £offled-2 … ‹charging ”ÿ =Ça¨sdio-pwrseq,mmc-pwrseq-simple È Ôext_clock¼ÉÆdefault ±È Œ[µIsound,simple-audio-card ûrk817_exti2s+ ÈHeadphoneHeadphones âHeadphonesHPOLHeadphonesHPORsimple-audio-card,codecLÈsimple-audio-card,cpuLÊregulator-vcc3v3-lcd0,regulator-fixed ü!¼ËÆdefault12Z I2Z �vcc3v3_lcd0_nˆµYregulator-state-memœregulator-vcc-sys,regulator-fixed 19ûÀI9ûÀ�vcc_sysµ$regulator-vcc-wifi,regulator-fixed ü!¼ÌÆdefault 12Z I2Z  �vcc_wifiµM interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc1mmc2mmc3device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightiovcc-supplyreset-gpiosrotationddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendio-channelspoll-intervalabs-flatabs-fuzzabs-rangelinux,codeio-channel-namesmux-controlssettle-time-uspower-supplypwmscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0labelautorepeatmux-gpios#mux-control-cellscolorfunctionmax-brightnessdefault-statepost-power-on-delay-mssimple-audio-card,widgetssimple-audio-card,routinggpioenable-active-high