Ð þíÞK8Ñì( _Ñ´ =,xunlong,orangepi-3b-v1.1xunlong,orangepi-3brockchip,rk35667Xunlong Orange Pi 3B v1.1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe310000ì/mmc@fe2b0000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55 psci*€7@I€V€c@u€‚“§² cpu@100öcpu,arm,cortex-a55 psci*€7@I€V€c@u€‚“§² cpu@200öcpu,arm,cortex-a55 psci*€7@I€V€c@u€‚“§² cpu@300öcpu,arm,cortex-a55 psci*€7@I€V€c@u€‚“§² l3-cache,cacheºÆ,9@K²display-subsystem,rockchip,display-subsystemÔfirmwarescmi ,arm,scmi-smcÚ‚å protocol@14ë²hdmi-sound,simple-audio-cardøHDMIi2s(Bokaysimple-audio-card,codecIsimple-audio-card,cpuI pmu,arm,cortex-a55-pmu0Säåæç^ psci ,arm,psci-1.0#smcreserved-memory qshmem@10f000,arm,scmi-shmemðx²timer,arm,armv8-timer0S   xin24m ,fixed-clock–n6¦xin24më²xin32k ,fixed-clock–€¦xin32k¹Ãdefaultësata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�Ñsatapmaliverxoob S_Ý âsata-phyìþ Bdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢Ñsatapmaliverxoob S`Ý âsata-phyìþ Bdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ S©¦§¥Ñref_clksuspend_clkbus_clk host utmi_wideþ”$BokayÝ âusb2-phy= Dhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ Sª©ª¨Ñref_clksuspend_clkbus_clk host Ýâusb2-phyusb3-phy utmi_wideþ•$Bokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF S RgxýA‚(�q œ²msi-controller@fd440000,arm,gic-v3-itsýDœ�¬²_usb@fd800000 ,generic-ehciý€ S‚½¾¼ÝâusbBokayusb@fd840000 ,generic-ohciý„ Sƒ½¾¼ÝâusbBokayusb@fd880000 ,generic-ehciýˆ S…¿À¼ÝâusbBokayusb@fd8c0000 ,generic-ohciýŒ S†¿À¼ÝâusbBokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²]io-domains&,rockchip,rk3568-pmu-io-voltage-domainBokay·ÅÓáïý 'syscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsyscon²¯syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲ°syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ±syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²²syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²µclock-controller@fdd00000,rockchip,rk3568-pmucruýÐë5²clock-controller@fdd20000,rockchip,rk3568-cruýÒÑxin24më5B R€G†Œ ëÂg~²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ S.- Ñi2cpclk¹ Ãdefault Bokaypmic@20,rockchip,rk809 BHg–ëHÑmclk¦rk809-clkout1rk809-clkout2!SÃdefault¹"#‹œ´Â$Î$Ú$æ$ò$þ$ $$"$²ÆregulatorsDCDC_REG1 .vdd_logic=Qcz¡ ’™pªqregulator-state-mem¿DCDC_REG2.vdd_gpu=Qcz¡ ’™pªq²Cregulator-state-mem¿DCDC_REG3.vcc_ddr=Qcregulator-state-memØDCDC_REG4.vdd_npucz¡ ’™pªqregulator-state-mem¿DCDC_REG5.vcc_1v8=Qzw@’w@²regulator-state-mem¿LDO_REG1.vdda0v9_imagez » ’ » ²Yregulator-state-mem¿LDO_REG2 .vdda_0v9=Qz » ’ » regulator-state-mem¿LDO_REG3 .vdda0v9_pmu=Qz » ’ » regulator-state-memØð » LDO_REG4 .vccio_acodec=Qz2Z ’2Z ²regulator-state-mem¿LDO_REG5 .vccio_sd=Qzw@’2Z ²regulator-state-mem¿LDO_REG6 .vcc3v3_pmu=Qz2Z ’2Z ²regulator-state-memØð2Z LDO_REG7 .vcca_1v8=Qzw@’w@²¢regulator-state-mem¿LDO_REG8 .vcca1v8_pmu=Qzw@’w@regulator-state-memØðw@LDO_REG9.vcca1v8_imagezw@’w@²Zregulator-state-mem¿SWITCH_REG1.vcc_3v3=Q²regulator-state-mem¿SWITCH_REG2 .vcc3v3_sd=Q²fregulator-state-mem¿regulator@40,silergy,syr827@ .vdd_cpu=Qz ª0’O€ªü)$²regulator-state-mem¿serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ St ,Ñbaudclkapb_pclk4%%¹&Ãdefault9F Bdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 Ñpwmpclk¹'ÃdefaultP Bdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 Ñpwmpclk¹(ÃdefaultP Bdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 Ñpwmpclk¹)ÃdefaultP Bdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 Ñpwmpclk¹*ÃdefaultP Bdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller[ ²power-domain@7o+[power-domain@8ÌÍ o,-.[power-domain@9 ÚÛÜ o/01[power-domain@10 ñòo234567[power-domain@11 ío8[power-domain@13 o9[power-domain@14 o:;<[power-domain@15o=>?@A[gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$S()' vjobmmugpuÑgpubus þBokay“B†C²Ÿvideo-codec@fdea0400,rockchip,rk3568-vpuýê S‹vvdpuîï Ñaclkhclk’Dþ iommu@fdea0800,rockchip,rk3568-iommuýê@ SŠ Ñaclkifaceîïþ ™²Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ SZóôõÑaclkhclksclk&$% ¦coreaxiahbþ video-codec@fdee0000,rockchip,rk3568-vepuýî S@ýþ Ñaclkhclk’Eþ iommu@fdee0800,rockchip,rk3568-iommuýî@ S?ýþ Ñaclkifaceþ ™²Evideo-capture@fdfe0000,rockchip,rk3568-vicapýþ S’BÐRᣠÎÏÐÑÑaclkhclkdclkiclk’Fþ(÷øùûú¦arsthrstdrstprstirst~ Bdisabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommuýþ S’ÎÏ Ñaclkiface™þ² Bdisabled²Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ Sd ÁÂŽ�Ñbiuciuciu-driveciu-sampleÍØðÑ€ë¦reset Bdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþS vmacirqeth_wake_irq@†‰‰ÇÃĉÈWÑstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refì ¦stmmaceth~æGöHI-BokayB‰†g‡Å6input Crgmii-idLÃdefault¹JKLMNOWPmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22bN rÃP „Q²Pstmmac-axi-config�šª²Grx-queues-configº²Hqueue0tx-queues-configвIqueue0vop@fe040000 þ0þ@ævopgamma-lut S”(ÝÞßàá%Ñaclkhclkdclk_vp0dclk_vp1dclk_vp2’Rþ ~Bokay,rockchip,rk3566-vopBßàgports ²port@0 endpoint@2ðS²[port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? S”ÝÞ Ñaclkiface™þ Bokay²Rdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ SDÑpclkèâdphyÝTþ ¦apb~ Bdisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ SEÑpclkéâdphyÝUþ ¦apb~ Bdisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  S-(æç“(ÚÑiahbisfrcecrefÃdefault ¹VWXþ 9~‹BokayYZ²ports port@0endpointð[²Sport@1endpointð\²Àqos@fe128000,rockchip,rk3568-qossysconþ€ ²+qos@fe138080,rockchip,rk3568-qossysconþ€€ ²:qos@fe138100,rockchip,rk3568-qossysconþ� ²;qos@fe138180,rockchip,rk3568-qossysconþ�€ ²<qos@fe148000,rockchip,rk3568-qossysconþ€ ²,qos@fe148080,rockchip,rk3568-qossysconþ€€ ²-qos@fe148100,rockchip,rk3568-qossysconþ� ².qos@fe150000,rockchip,rk3568-qossysconþ ²8qos@fe158000,rockchip,rk3568-qossysconþ€ ²2qos@fe158100,rockchip,rk3568-qossysconþ� ²3qos@fe158180,rockchip,rk3568-qossysconþ�€ ²4qos@fe158200,rockchip,rk3568-qossysconþ‚ ²5qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²6qos@fe158300,rockchip,rk3568-qossysconþƒ ²7qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²=qos@fe190280,rockchip,rk3568-qossysconþ€ ²>qos@fe190300,rockchip,rk3568-qossysconþ ²?qos@fe190380,rockchip,rk3568-qossysconþ€ ²@qos@fe190400,rockchip,rk3568-qossysconþ ²Aqos@fe198000,rockchip,rk3568-qossysconþ€ ²9qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²/qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²0qos@fe1a8100,rockchip,rk3568-qossysconþ� ²1dfi@fe230000,rockchip,rk3568-dfiþ# S  ]pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôædbiapbconfig<SKJIHGvsyspmcmsglegacyerr-(�‚ƒ„…$Ñaclk_mstaclk_slvaclk_dbipclkauxöpcig7`J^^^^Xix‡–_žÝ âpcie-phyþTqôôô ô à@¡¦pipe BokayÃdefault¹` „!¨alegacy-interrupt-controllergR SH²^mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ Sb °±Š‹Ñbiuciuciu-driveciu-sampleÍØðÑ€Ô¦resetBokay¸ÂÓÃdefault¹bcdeÞfêmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ Sc ²³Œ�Ñbiuciuciu-driveciu-sampleÍØðÑ€Ö¦resetBokay¸Â÷  g % , 2Ãdefault ¹hij @Þêspi@fe300000 ,rockchip,sfcþ0@ SexvÑclk_sfchclk_sfc¹kÃdefaultBokay flash@0,jedec,spi-nor N2ê ` qmmc@fe310000,rockchip,rk3568-dwcmshcþ1 SB{}R ëÂn6(|zy{}ÑcorebusaxiblocktimerBokay¸ ‚Ø ë ” 2Ãdefault¹lmnoÞêrng@fe388000,rockchip,rk3568-rngþ8€@po Ñcoreahbm Bdisabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ S4B=ARFÏqFÏq?C9Ñmclk_txmclk_rxhclk4p £txPQ ¦tx-mrx-m~‹Bokay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA S5BEIRFÏqFÏqGK:Ñmclk_txmclk_rxhclk4pp £rxtxRS ¦tx-mrx-m~Ãdefault¹qrst‹Bokay ­²Èi2s@fe420000,rockchip,rk3568-i2s-tdmþB S6BMRFÏqOO;Ñmclk_txmclk_rxhclk4pp £txrxT¦tx-m~Ãdefault¹uvwx‹ Bdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC S7SW<Ñmclk_txmclk_rxhclk4pp £txrxUV ¦tx-mrx-m~‹ Bdisabledpdm@fe440000,rockchip,rk3568-pdmþD SLZYÑpdm_clkpdm_hclk4p  £rx¹yz{|}~ÃdefaultX¦pdm-m‹ Bdisabledspdif@fe460000,rockchip,rk3568-spdifþF Sf Ñmclkhclk_\4p £txÃdefault¹‹ Bdisableddma-controller@fe530000,arm,pl330arm,primecellþS@S  È  Ñapb_pclk ß²%dma-controller@fe550000,arm,pl330arm,primecellþU@S È  Ñapb_pclk ß²pi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ S/HG Ñi2cpclk¹€Ãdefault  Bdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ S0JI Ñi2cpclk¹�Ãdefault Bokayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ S1LK Ñi2cpclk¹‚Ãdefault  Bdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] S2NM Ñi2cpclk¹ƒÃdefault  Bdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ S3PO Ñi2cpclk¹„Ãdefault  Bdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` S• Ñtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa SgRQÑspiclkapb_pclk4%% £txrxÃdefault ¹…†‡  Bdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb ShTSÑspiclkapb_pclk4%% £txrxÃdefault ¹ˆ‰Š  Bdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc SiVUÑspiclkapb_pclk4%% £txrxÃdefault ¹‹Œ�  Bdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd SjXWÑspiclkapb_pclk4%% £txrxÃdefault ¹Ž��  Bdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe SuÑbaudclkapb_pclk4%% ¹‘’“Ãdefault9FBokay êserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf Sv# Ñbaudclkapb_pclk4%%¹”Ãdefault9FBokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg Sw'$Ñbaudclkapb_pclk4%%¹•Ãdefault9F Bdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh Sx+(Ñbaudclkapb_pclk4%% ¹–Ãdefault9F Bdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi Sy/,Ñbaudclkapb_pclk4% % ¹—Ãdefault9F Bdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj Sz30Ñbaudclkapb_pclk4% % ¹˜Ãdefault9F Bdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk S{74Ñbaudclkapb_pclk4%%¹™Ãdefault9F Bdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl S|;8Ñbaudclkapb_pclk4%%¹šÃdefault9F Bdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm S}?<Ñbaudclkapb_pclk4%%¹›Ãdefault9F Bdisabledthermal-zonescpu-thermal úd è œtripscpu_alert0 .p :Ðýpassive²�cpu_alert1 .$ø :Ðýpassivecpu_crit .s :Ð ýcriticalcooling-mapsmap0 E�0 J ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal ú è œtripsgpu-threshold .p :Ðýpassivegpu-target .$ø :Ðýpassive²žgpu-crit .s :Ð ýcriticalcooling-mapsmap0 Ež JŸÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq SsBRf@ ®`Ñtsadcapb_pclk�‚×~ YsÃdefaultsleep¹  p¡ zBokay � §²œsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr S]Ñsaradcapb_pclk€ ¦saradc-apb ÂBokay Ô¢pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY Ñpwmpclk¹£ÃdefaultP Bdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY Ñpwmpclk¹¤ÃdefaultP Bdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY Ñpwmpclk¹¥ÃdefaultP Bdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY Ñpwmpclk¹¦ÃdefaultP Bdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ Ñpwmpclk¹§ÃdefaultP Bdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ Ñpwmpclk¹¨ÃdefaultP Bdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ Ñpwmpclk¹©ÃdefaultP Bdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ Ñpwmpclk¹ªÃdefaultP Bdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ Ñpwmpclk¹«ÃdefaultP Bdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ Ñpwmpclk¹¬ÃdefaultP Bdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ Ñpwmpclk¹­ÃdefaultP Bdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ Ñpwmpclk¹®ÃdefaultP Bdisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} ÑrefapbpipeB"RõáǦphy ௠ò° Bokay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ ÑrefapbpipeB%Rõáɦphy ௠ò± Bokay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡yÑpclk º¦apb~ Bdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… Ñrefpclkz þ ¦apb» Bdisabled²Tmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† Ñrefpclk{ þ ¦apb¼ Bdisabled²Uusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠÑphyclk¦clk_usbphy0_480m S‡ ²ëBokay²host-port BokayL³²otg-port BokayL´²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹Ñphyclk¦clk_usbphy1_480m Sˆ µëBokayhost-port BokayL³²otg-port BokayL³²pinctrl,rockchip,rk3568-pinctrl~ ] q²¶gpio@fdd60000,rockchip,gpio-bankýÖ S!.  # 3¶  ?Rg²!gpio@fe740000,rockchip,gpio-bankþt S"cd # 3¶  ?Rggpio@fe750000,rockchip,gpio-bankþu S#ef # 3¶@  ?Rggpio@fe760000,rockchip,gpio-bankþv S$gh # 3¶`  ?Rg²Qgpio@fe770000,rockchip,gpio-bankþw S%ij # 3¶€  ?Rgpcfg-pull-up K²¹pcfg-pull-down X²¿pcfg-pull-none g²·pcfg-pull-none-drv-level-1 g t²»pcfg-pull-none-drv-level-2 g t²ºpcfg-pull-none-drv-level-3 g t²¾pcfg-pull-up-drv-level-1 K t²½pcfg-pull-up-drv-level-2 K t²¸pcfg-pull-none-smt g ƒ²¼acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ˜·²cpuebcedpdpemmcemmc-bus8€ ˜ ¸ ¸¸¸¸¸¸¸²lemmc-clk ˜¸²memmc-cmd ˜¸²nemmc-datastrobe ˜·²oeth0eth1flashfspifspi-pins` ˜······²kgmac0gmac1gmac1m0-miim ˜··²Jgmac1m0-clkinout ˜·²Ogmac1m0-rx-bus20 ˜ · · ·²Lgmac1m0-tx-bus20 ˜ ºº·²Kgmac1m0-rgmii-clk ˜·»²Mgmac1m0-rgmii-bus@ ˜··ºº²Ngpuhdmitxhdmitxm0-cec ˜·²Xhdmitx-scl ˜·²Vhdmitx-sda ˜·²Wi2c0i2c0-xfer ˜ ¼ ¼² i2c1i2c1-xfer ˜ ¼ ¼²€i2c2i2c2m1-xfer ˜ ¼ ¼²�i2c3i2c3m0-xfer ˜¼¼²‚i2c4i2c4m0-xfer ˜ ¼ ¼²ƒi2c5i2c5m0-xfer ˜ ¼ ¼²„i2s1i2s1m0-lrcktx ˜·²ri2s1m0-mclk ˜·²#i2s1m0-sclktx ˜·²qi2s1m0-sdi0 ˜ ·²si2s1m0-sdo0 ˜·²ti2s2i2s2m0-lrcktx ˜·²vi2s2m0-sclktx ˜·²ui2s2m0-sdi ˜·²wi2s2m0-sdo ˜·²xi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ˜·²ypdmm0-clk1 ˜·²zpdmm0-sdi0 ˜ ·²{pdmm0-sdi1 ˜ ·²|pdmm0-sdi2 ˜ ·²}pdmm0-sdi3 ˜·²~pmicpmic-int-l ˜¹²"pmupwm0pwm0m0-pins ˜·²'pwm1pwm1m0-pins ˜·²(pwm2pwm2m0-pins ˜·²)pwm3pwm3-pins ˜·²*pwm4pwm4-pins ˜·²£pwm5pwm5-pins ˜·²¤pwm6pwm6-pins ˜·²¥pwm7pwm7-pins ˜·²¦pwm8pwm8m0-pins ˜ ·²§pwm9pwm9m0-pins ˜ ·²¨pwm10pwm10m0-pins ˜ ·²©pwm11pwm11m0-pins ˜·²ªpwm12pwm12m0-pins ˜·²«pwm13pwm13m0-pins ˜·²¬pwm14pwm14m0-pins ˜·²­pwm15pwm15m0-pins ˜·²®refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ˜¸¸¸¸²bsdmmc0-clk ˜¸²csdmmc0-cmd ˜¸²dsdmmc0-det ˜¹²esdmmc1sdmmc1-bus4@ ˜¸¸¸¸²hsdmmc1-clk ˜¸²isdmmc1-cmd ˜¸²jsdmmc2spdifspdifm0-tx ˜·²spi0spi0m0-pins0 ˜ ···²‡spi0m0-cs0 ˜·²…spi0m0-cs1 ˜·²†spi1spi1m0-pins0 ˜ ···²Šspi1m0-cs0 ˜·²ˆspi1m0-cs1 ˜·²‰spi2spi2m0-pins0 ˜···²�spi2m0-cs0 ˜·²‹spi2m0-cs1 ˜·²Œspi3spi3m0-pins0 ˜ ·· ·²�spi3m0-cs0 ˜·²Žspi3m0-cs1 ˜·²�tsadctsadc-shutorg ˜·² tsadc-pin ˜·²¡uart0uart0-xfer ˜¹¹²&uart1uart1m0-xfer ˜ ¹ ¹²‘uart1m0-ctsn ˜·²’uart1m0-rtsn ˜ ·²“uart2uart2m0-xfer ˜¹¹²”uart3uart3m0-xfer ˜¹¹²•uart4uart4m0-xfer ˜¹¹²–uart5uart5m0-xfer ˜¹¹²—uart6uart6m0-xfer ˜¹¹²˜uart7uart7m0-xfer ˜¹¹²™uart8uart8m0-xfer ˜¹¹²šuart9uart9m0-xfer ˜¹¹²›vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h ˜·bt-wake-host-h ˜¿host-wake-bt-h ˜·ledswork-led ˜·²Ápciepcie20-pins0 ˜·· ·²`pcie20-pwren ˜·²Âusbusb-host-pwren-h ˜·²Äusb-otg-pwren-h ˜·²Åwifiwifi-reg-on-h ˜·²Çwifi-wake-host-h ˜¿opp-table-0,operating-points-v2 ¦²opp-408000000 ±Q– ¸ øP øPŒ0 Æœ@opp-600000000 ±#ÃF ¸ øP øPŒ0 Æœ@opp-816000000 ±0£, ¸ øP øPŒ0 Æœ@ ×opp-1104000000 ±AÍ´ ¸ »  » Œ0 Æœ@opp-1416000000 ±Tfr ¸£è£èŒ0 Æœ@opp-1608000000 ±_Ø" ¸ÈàÈàŒ0 Æœ@opp-1800000000 ±kIÒ ¸Œ0Œ0Œ0 Æœ@opp-table-1,operating-points-v2²Bopp-200000000 ± ë ¸ øP øPB@opp-300000000 ±á£ ¸ øP øPB@opp-400000000 ±ׄ ¸ øP øPB@opp-600000000 ±#ÃF ¸ »  » B@opp-700000000 ±)¹' ¸~ð~ðB@opp-800000000 ±/¯ ¸B@B@B@chosen ãserial2:1500000n8hdmi-con,hdmi-connectorýaportendpointðÀ²\leds ,gpio-ledsÃdefault¹Áled-0 ï õon heartbeat Š! heartbeatregulator-3v3-vcc-pcie30,regulator-fixed " Š!Ãdefault¹Â.vcc3v3_pcie30z2Z ’2Z )$²aregulator-3v3-vcc-sys,regulator-fixed .vcc3v3_sys=Qz2Z ’2Z )ò$regulator-5v0-vcc-sys,regulator-fixed .vcc5v0_sys=QzLK@’LK@²Ãregulator-5v0-vcc-usb-host,regulator-fixed " Š!Ãdefault¹Ä.vcc5v0_usb_hostzLK@’LK@)ò³regulator-5v0-vcc-usb-otg,regulator-fixed " Š!Ãdefault¹Å.vcc5v0_usb_otgzLK@’LK@)ò´sdio-pwrseq,mmc-pwrseq-simpleÆ Ñext_clockÃdefault¹Ç 5È LLK@ „!²gsound,simple-audio-cardi2s øAnalog RK809(simple-audio-card,cpuIÈsimple-audio-card,codecIÆ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio6-supplyvccio7-supplyvccio5-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplyphy-handlereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthcap-mmc-highspeedmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolordefault-statefunctionlinux,default-triggerenable-active-highpost-power-on-delay-mspower-off-delay-us