Ð þí‡ñ8 (Qh)rockchip,rk3562-evb2-v10rockchip,rk3562 +7Rockchip RK3562 EVB2 V10 Boardaliases=/pinctrl/gpio@ff260000C/pinctrl/gpio@ff620000I/pinctrl/gpio@ff630000O/pinctrl/gpio@ffac0000U/pinctrl/gpio@ffad0000clock-xin32k fixed-clock[h€xxin32kclock-xin24m fixed-clock[hn6xxin24mcpus+cpu@0‹cpuarm,cortex-a53—›psci©°ÀÔãŠýcpu@1‹cpuarm,cortex-a53—›psci©°ÀÔãŠýcpu@2‹cpuarm,cortex-a53—›psci©°ÀÔãŠýcpu@3‹cpuarm,cortex-a53—›psci©°ÀÔãŠýidle-statespscicpu-sleeparm,idle-state#:xKú[„ýopp-table-cpu0operating-points-v2lýopp-408000000wQ– ~ –¨ –¨Œ0Œœ@�opp-600000000w#ÃF ~ –¨ –¨Œ0Œœ@opp-816000000w0£, ~ –¨ –¨Œ0Œœ@opp-1008000000w<Ü ~ øP øPŒ0Œœ@opp-1200000000wG†Œ ~HHŒ0Œœ@opp-1416000000wTfr ~B@B@Œ0Œœ@opp-1608000000©ùÿÿw_Ø" ~Ô¼Ô¼Œ0Œœ@opp-1800000000wkIÒ ~*ˆ*ˆŒ0Œœ@opp-2016000000wx)¸ ~Œ0Œ0Œ0Œœ@opp-table-gpuoperating-points-v2ý2opp-300000000wᣠ~ –¨ –¨B@opp-400000000wׄ ~ –¨ –¨B@opp-500000000wÍe ~ –¨ –¨B@opp-600000000w#ÃF ~ –¨ –¨B@opp-700000000w)¹' ~ »  » B@opp-800000000w/¯ ~~ð~ðB@opp-900000000w5¤é ~B@B@B@arm-pmuarm,cortex-a53-pmu0ºäåæçÅfirmwarescmi arm,scmi-smcØ Þ‚+protocol@14—[ýpinctrlrockchip,rk3562-pinctrlé +öý gpio@ff260000rockchip,gpio-bank—ÿ&©  ý  º.:ýgpio@ff620000rockchip,gpio-bank—ÿb©  ý  º.:gpio@ff630000rockchip,gpio-bank—ÿc©  ý @  º.:gpio@ffac0000rockchip,gpio-bank—ÿ¬© T &ý `  º.:ýgpio@ffad0000rockchip,gpio-bank—ÿ­© U 'ý €  º.:ý]pcfg-pull-upKýpcfg-pull-noneXý pcfg-pull-none-drv-level-1Xeýpcfg-pull-none-drv-level-3Xeýpcfg-pull-none-drv-level-4Xeýpcfg-pull-up-drv-level-2Keýpcfg-pull-none-smtXtýpcfg-output-low‰ýcamcan0can1clkclk0clk1cpudsmemmcethfspigpui2c0i2c0-xfer ”  ýi2c1i2c1m0-xfer ”  ýTi2c2i2c2m0-xfer ” ýUi2c3i2c3m0-xfer ”ýVi2c4i2c4m0-xfer ”ýWi2c5i2c5m0-xfer ”ýXi2s0i2s1i2s2ispjtagnpupcie20pdmpmicpmic-int”ýpmupwm0pwm0m0-pins”ý"pwm1pwm1m0-pins”ý#pwm2pwm2m0-pins”ý$pwm3pwm3m0-pins”ý%pwm4pwm4m0-pins”ý;pwm5pwm5m0-pins”ý<pwm6pwm6m0-pins”ý=pwm7pwm7m0-pins”ý>pwm8pwm8m0-pins”ý?pwm9pwm9m0-pins”ý@pwm10pwm10m0-pins” ýApwm11pwm11m0-pins”ýBpwm12pwm12m0-pins”ýCpwm13pwm13m0-pins”ýDpwm14pwm14m0-pins”ýEpwm15pwm15m0-pins”ýFpwrrefrgmiirmiisdmmc0sdmmc0-bus4@”   ýJsdmmc0-clk”ýKsdmmc0-cmd”ýLsdmmc0-det”ýMsdmmc1sdmmc1-bus4@”ýQsdmmc1-clk”ýSsdmmc1-cmd”ýRspdifspi0spi0m0-pins0”ý!spi0m0-csn0”ýspi0m0-csn1”ý spi1spi1m0-pins0”ý5spi1m0-csn0”ý3spi1m0-csn1”ý4spi2spi2m0-pins0”ý8spi2m0-csn0” ý6spi2m0-csn1” ý7tsadcuart0uart1uart1m0-xfer ”ý9uart1m0-ctsn” ý:uart2uart3uart4uart5uart6uart7uart8uart9vosdio-pwrseqwifi-enable-h” ý[usbusb-host-pwren” ý_usb-otg-pwren” ý`psci arm,psci-1.0¢smcreserved-memory+öshmem@10f000arm,scmi-shmem—ð¢ý timerarm,armv8-timer0º   soc simple-bus+öpcie@fe000000*rockchip,rk3562-pcierockchip,rk3568-pcie0—þ@ÿPü©dbiapbconfig³ÿ(©      $½aclk_mstaclk_slvaclk_dbipclkaux‹pciHº�‘Ž��’Ésyspmcmsglegacyerrmsi:Ù`ìú )6EO Tpcie-phy^Töüüü ü à@l Mspipe+okay †’legacy-interrupt-controller:  º�ýinterrupt-controller@fe901000 arm,gic-400:@—þ�þ� þ�@ þ�`  º ýqos@fee03800rockchip,rk3562-qossyscon—þà8 qos@fee10000rockchip,rk3562-qossyscon—þá qos@fee10100rockchip,rk3562-qossyscon—þá qos@fee10200rockchip,rk3562-qossyscon—þá qos@fee10300rockchip,rk3562-qossyscon—þá qos@fee10400rockchip,rk3562-qossyscon—þá qos@fee20000rockchip,rk3562-qossyscon—þâ qos@fee30000rockchip,rk3562-qossyscon—þã ý&qos@fee40000rockchip,rk3562-qossyscon—þä ý'qos@fee50000rockchip,rk3562-qossyscon—þå ý(qos@fee60000rockchip,rk3562-qossyscon—þæ ý+qos@fee70000rockchip,rk3562-qossyscon—þç ý)qos@fee70100rockchip,rk3562-qossyscon—þç ý*qos@fee80000rockchip,rk3562-qossyscon—þè ý,qos@fee90000rockchip,rk3562-qossyscon—þé ý/qos@fee90100rockchip,rk3562-qossyscon—þé ý-qos@fee90200rockchip,rk3562-qossyscon—þé ý.qos@feea0000rockchip,rk3562-qossyscon—þê ý0qos@feea0100rockchip,rk3562-qossyscon—þê ý1qos@feeb0000rockchip,rk3562-qossyscon—þë qos@feeb0100rockchip,rk3562-qossyscon—þë qos@feeb0200rockchip,rk3562-qossyscon—þë qos@feeb0300rockchip,rk3562-qossyscon—þë qos@feeb0400rockchip,rk3562-qossyscon—þë qos@feeb0500rockchip,rk3562-qossyscon—þë qos@feeb0600rockchip,rk3562-qossyscon—þë qos@feeb0700rockchip,rk3562-qossyscon—þë qos@feeb0800rockchip,rk3562-qossyscon—þë syscon@ff010000*rockchip,rk3562-pmu-grfsysconsimple-mfd—ÿreboot-modesyscon-reboot-mode¢ ©RBõRBÃÁRBÃÏRBà syscon@ff030000rockchip,rk3562-sys-grfsyscon—ÿsyscon@ff040000 rockchip,rk3562-peri-grfsyscon—ÿýHsyscon@ff060000rockchip,rk3562-ioc-grfsyscon—ÿý syscon@ff090000"rockchip,rk3562-usbphy-grfsyscon—ÿ €syscon@ff098000#rockchip,rk3562-pipephy-grfsyscon—ÿ €€ýIclock-controller@ff100000rockchip,rk3562-cru—ÿ[ßì    üFÏq;šÊ:˜ý i2c@ff200000(rockchip,rk3562-i2crockchip,rk3399-i2c—ÿ © & % ½i2cpclk º default+okaypmic@20rockchip,rk809—  º-defaultpmic-sleeppmic-power-offpmic-reset)J[xrk808-clkout1rk808-clkout2Xdp|ˆ” ¬¸ýZregulatorsDCDC_REG1ÄØê¡ ™pq/ Fvdd_logicregulator-state-memUDCDC_REG2ÄØê¡ ™pq/Fvdd_cpuregulator-state-memUDCDC_REG3ÄØ/Fvcc_ddrregulator-state-memnDCDC_REG4ÄØê¡ ™pq/Fvdd_gpuregulator-state-memULDO_REG1ê*¹€*¹€ Fvcc2v8_dvpregulator-state-memULDO_REG2ÄØê »  »  Fvdda_0v9regulator-state-memULDO_REG3ÄØê »  »  Fvdda0v9_pmuregulator-state-memn† » LDO_REG4ÄØê-ÆÀ-ÆÀ Fvccio_acodecregulator-state-memULDO_REG5ÄØêw@2Z  Fvccio_sdýOregulator-state-memULDO_REG6ÄØê2Z 2Z  Fvcc3v3_pmuregulator-state-memn†2Z LDO_REG7ÄØêw@w@ Fvcca_1v8regulator-state-memULDO_REG8ÄØêw@w@ Fvcca1v8_pmuregulator-state-memn†w@LDO_REG9êw@w@ Fvcc1v8_dvpregulator-state-memUDCDC_REG5ÄØêw@w@Fvcc_1v8ýGregulator-state-memUSWITCH_REG1ÄØFvcc_3v3regulator-state-memUSWITCH_REG2ÄØ Fvcc3v3_sdýNregulator-state-memUserial@ff210000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿ! º© + '½baudclkapb_pclk¢¬okayspi@ff220000(rockchip,rk3562-spirockchip,rk3066-spi—ÿ" º4© - ,½spiclkapb_pclk¹  ¾txrxÈdefault  !+ disabledpwm@ff230000(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿ#© 0 / ½pwmpclkdefault"Ï disabledpwm@ff230010(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿ#© 0 / ½pwmpclkdefault#Ï disabledpwm@ff230020(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿ# © 0 / ½pwmpclkdefault$Ï disabledpwm@ff230030(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿ#0© 0 / ½pwmpclkdefault%Ï disabledpower-management@ff258000&rockchip,rk3562-pmusysconsimple-mfd—ÿ%€power-controller!rockchip,rk3562-power-controllerÚ+ýpower-domain@8—î&Úpower-domain@7—î'Úpower-domain@11— î(Úpower-domain@12— î)*Ú+power-domain@10— î+Úpower-domain@13— î,Ú+power-domain@14— î-./Úpower-domain@15—î01Úgpu@ff320000&rockchip,rk3562-maliarm,mali-bifrost—ÿ2@© k i½clk_gpuclk_gpu_brgaclk_gpuã4$ºLMK ÉjobmmugpuÀ2^Ô disabledspi@ff640000rockchip,rk3066-spi—ÿd º5© ¡  ½spiclkapb_pclk¹¾txrxÈdefault 345+ disabledspi@ff650000rockchip,rk3066-spi—ÿe º6© ¤ £½spiclkapb_pclk¹¾txrxÈdefault 678+ disabledserial@ff670000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿg º© ² ¦½baudclkapb_pclk¢¬okaydefault9:serial@ff680000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿh º © ¶ §½baudclkapb_pclk¢¬ disabledserial@ff690000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿi º!© º ¨½baudclkapb_pclk¢¬ disabledserial@ff6a0000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿj º"© ¾ ©½baudclkapb_pclk¢¬ disabledserial@ff6b0000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿk º#©  ª½baudclkapb_pclk¢¬ disabledserial@ff6c0000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿl º$© Æ «½baudclkapb_pclk¢¬ disabledserial@ff6d0000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿm º%© Ê ¬½baudclkapb_pclk¢¬ disabledserial@ff6e0000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿn º&© Î ­½baudclkapb_pclk¢¬ disabledserial@ff6f0000&rockchip,rk3562-uartsnps,dw-apb-uart—ÿo º'© Ò ®½baudclkapb_pclk¢¬ disabledpwm@ff700000(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿp© Ô Ó ½pwmpclkdefault;Ï disabledpwm@ff700010(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿp© Ô Ó ½pwmpclkdefault<Ï disabledpwm@ff700020(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿp © Ô Ó ½pwmpclkdefault=Ï disabledpwm@ff700030(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿp0© Ô Ó ½pwmpclkdefault>Ï disabledpwm@ff710000(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿq© × Ö ½pwmpclkdefault?Ï disabledpwm@ff710010(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿq© × Ö ½pwmpclkdefault@Ï disabledpwm@ff710020(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿq © × Ö ½pwmpclkdefaultAÏ disabledpwm@ff710030(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿq0© × Ö ½pwmpclkdefaultBÏ disabledpwm@ff720000(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿr© Ú Ù ½pwmpclkdefaultCÏ disabledpwm@ff720010(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿr© Ú Ù ½pwmpclkdefaultDÏ disabledpwm@ff720020(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿr © Ú Ù ½pwmpclkdefaultEÏ disabledpwm@ff720030(rockchip,rk3562-pwmrockchip,rk3328-pwm—ÿr0© Ú Ù ½pwmpclkdefaultFÏ disabledadc@ff730000rockchip,rk3562-saradc—ÿs º(© þ ý½saradcapb_pclkl  ssaradc-apbõokayGýYphy@ff750000rockchip,rk3562-naneng-combphy—ÿu© : ü  ½refapbpipeì :üõál OsphyH0Iokayýspi@ff860000 rockchip,sfc—ÿ† º€© œ �½clk_sfchclk_sfc+ disabledmmc@ff8700000rockchip,rk3562-dwcmshcrockchip,rk3588-dwcmshc—ÿ‡ º?ì š ™ü ë ëÂ(© ™ — ˜ š ›½corebusaxiblocktimer(l Ð Î Ï Ñ ÒscorebusaxiblocktimerF ëÂokayT^flz‰£mmc@ff8800000rockchip,rk3562-dw-mshcrockchip,rk3288-dw-mshc—ÿˆ º8 © � � “ ”½biuciuciu-driveciu-sample½F ëÂl Ìsresetokay^ÈTÏáòdefaultJKLMý NOmmc@ff8900000rockchip,rk3562-dw-mshcrockchip,rk3288-dw-mshc—ÿ‰ º9 © ‘ ’ • –½biuciuciu-driveciu-sample½F ëÂl ÍsresetokayfÈTòá$1GPldefault QRSýdma-controller@ff990000arm,pl330arm,primecell—ÿ™@R© ñ ½apb_pclkºoniýi2c@ffa00000(rockchip,rk3562-i2crockchip,rk3399-i2c—ÿ ©  ½i2cpclk º defaultT+ disabledi2c@ffa10000(rockchip,rk3562-i2crockchip,rk3399-i2c—ÿ¡© !  ½i2cpclk ºdefaultU+ disabledi2c@ffa20000(rockchip,rk3562-i2crockchip,rk3399-i2c—ÿ¢© "  ½i2cpclk ºdefaultV+ disabledi2c@ffa30000(rockchip,rk3562-i2crockchip,rk3399-i2c—ÿ£© #  ½i2cpclk ºdefaultW+ disabledi2c@ffa40000(rockchip,rk3562-i2crockchip,rk3399-i2c—ÿ¤© $  ½i2cpclk ºdefaultX+ disabledadc@ffaa0000rockchip,rk3562-saradc—ÿª º|© D V½saradcapb_pclkl ‡ ssaradc-apbõ disabledchosentserial0:1500000n8adc-keys adc-keys€YŒbuttons�w@·dbutton-vol-upÅs Ðvolume upÖBhbutton-vol-downÅr Ðvolume downÖQ0button-menuÅ‹ÐmenuÖ 5button-backÅžÐbackÖO€leds gpio-ledsled-0 Œ  ðheartbeatsdio-pwrseqmmc-pwrseq-simple©Z ½ext_clockdefault[È † ýPregulator-vcc12v-dcinregulator-fixed Fvcc12v_dcinÄØê··ý\regulator-vcc3v3-pcie20regulator-fixedFvcc3v3_pcie20ê2Z 2Z  Œ0ˆA\ýregulator-vcc5v0-sysregulator-fixed Fvcc5v0_sysÄØêLK@LK@A\ýaregulator-vcc5v0-usbregulator-fixed Fvcc5v0_usbÄØêLK@LK@A\ý^regulator-vcc5v0-usb-hostregulator-fixedFvcc5v0_usb_hostØÄêLK@LK@ L]A^default_regulator-vcc5v0-usb-otgregulator-fixedFvcc5v0_usb_otgêLK@LK@ LA^default`regulator-vcc3v3-clkregulator-fixed Fvcc3v3_clkê2Z 2Z Aaregulator-vcc-sysregulator-fixed Fvcc3v3_sysÄØê2Z 2Z A\ý compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4#clock-cellsclock-frequencyclock-output-namesdevice_typeregenable-methodclockscpu-idle-statesoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendopp-supported-hwinterruptsinterrupt-affinityshmemarm,smc-idrockchip,grfrangesgpio-controllergpio-rangesinterrupt-controller#gpio-cells#interrupt-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsno-mapreg-namesbus-rangeclock-namesinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-ib-windowsnum-viewportnum-ob-windowsnum-lanesphysphy-namespower-domainsresetsreset-namesstatusreset-gpiosvpcie3v3-supplyoffsetmode-normalmode-loadermode-recoverymode-bootloader#reset-cellsassigned-clocksassigned-clock-ratespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltreg-shiftreg-io-widthdmasdma-namesnum-cs#pwm-cells#power-domain-cellspm_qos#io-channel-cellsvref-supply#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-strobefull-pwr-cycle-in-suspendfifo-depthno-mmccap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqarm,pl330-periph-burst#dma-cellsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codelabelpress-threshold-microvoltlinux,default-triggerpost-power-on-delay-msenable-active-highstartup-delay-usvin-supplygpio