Ð þí{í8tÔ(tœ)friendlyarm,nanopi-zero2rockchip,rk3528 +7FriendlyElec NanoPi Zero2aliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/ethernet@ffbe0000e/soc/i2c@ffa58000j/soc/mmc@ffbf0000o/soc/mmc@ffc30000t/soc/serial@ff9f0000cpus+cpu-mapcluster0core0|core1|core2|core3|cpu@0arm,cortex-a53€„cpu�psciž¥¹Äcpu@1arm,cortex-a53€„cpu�psciž¥¹Äcpu@2arm,cortex-a53€„cpu�psciž¥¹Äcpu@3arm,cortex-a53€„cpu�psciž¥¹Äfirmwarescmi arm,scmi-smcÌ‚× +protocol@14€ÝÄopp-table-cpuoperating-points-v2êÄopp-1200000000õG†Œ ü Yø YøÈà œ@opp-1416000000õTfr üHHÈà œ@opp-1608000000õ_Ø" üà˜à˜Èà œ@opp-1800000000õkIÒ üÔ¼Ô¼Èà œ@opp-2016000000õx)¸ üÈàÈàÈà œ@opp-table-gpuoperating-points-v2Ä.opp-300000000õᣠü Yø YøB@opp-500000000õÍe ü Yø YøB@opp-600000000õ#ÃF ü Yø YøB@opp-700000000õ)¹' ü »  » B@opp-800000000õ/¯ ü~ð~ðB@pinctrlrockchip,rk3528-pinctrl' +4Ä gpio@ff610000rockchip,gpio-bank€ÿaž r s ;GFVb nƒgpio@ffaf0000rockchip,gpio-bank€ÿ¯ž ‘ ’ ;IFVb nƒ” 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Ä`led-sysàÄartcrtc-int-làÄ4usbusb20-host1-pwrenà Ädpsciarm,psci-1.0arm,psci-0.2—smcreserved-memory+4shmem@10f000arm,scmi-shmem€ðîÄ timerarm,armv8-timer0;   clock-xin24m fixed-clockõn6xin24mÝÄclock-gmac50m fixed-clockõúð€gmac0ÝÄsoc simple-bus4üüD+pcie@fe000000*rockchip,rk3528-pcierockchip,rk3568-pcie0€þ@þOüdbiapbconfig"ÿ(ž ° ± ² ® ¯$,aclk_mstaclk_slvaclk_dbipclkaux„pciH;œ�š›™ž8syspmcmsglegacyerrmsiƒH`[iz‰“ ˜pcie-phy” T4üüü ü à@¢ d b ©pwrpipe+ µdisabledlegacy-interrupt-controllern  ;›ƒÄinterrupt-controller@fed01000 arm,gic-400@€þÐþÐ þÐ@ þÐ`  ; nƒÄqos@ff200000rockchip,rk3528-qossyscon€ÿ qos@ff200080rockchip,rk3528-qossyscon€ÿ € qos@ff200100rockchip,rk3528-qossyscon€ÿ  qos@ff200200rockchip,rk3528-qossyscon€ÿ  qos@ff200280rockchip,rk3528-qossyscon€ÿ € qos@ff200300rockchip,rk3528-qossyscon€ÿ  qos@ff200380rockchip,rk3528-qossyscon€ÿ € qos@ff210000rockchip,rk3528-qossyscon€ÿ! qos@ff210080rockchip,rk3528-qossyscon€ÿ!€ qos@ff220000rockchip,rk3528-qossyscon€ÿ" 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0$1µokay;defaultI1serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿŸ€ž  ë,baudclkapb_pclk ;)0 0 ” $1 µdisabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ ž   ,baudclkapb_pclk ;*0 0 ” $1 µdisabledserial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ €ž  ì,baudclkapb_pclk ;+00” $1 µdisabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¡ž  1,baudclkapb_pclk ;,00” $1 µdisabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¡€ž " ¡,baudclkapb_pclk ;-00” $1 µdisabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¢ž % ¢,baudclkapb_pclk ;.00” $1 µdisabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uart€ÿ¢€ž ( £,baudclkapb_pclk ;/00” $1 µdisabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¥ž ß Þ ,i2cpclk ;=” + µdisabledi2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¥€ž Ý Ü ,i2cpclk ;>” +µokay;defaultI2rtc@51haoyu,hym8563€QÝ 3;;defaultI4Si2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2c€ÿ¦ž j i ,i2cpclk ;?;defaultI5+ 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ž r q ,pwmpclka µdisabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwm€ÿ©€0ž r q ,pwmpclka µdisabledadc@ffae0000rockchip,rk3528-saradc€ÿ®ž à Â,saradcapb_pclk ;Œ” ¢ o ©saradc-apblµokay~:Ä_ethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20a€ÿ½0ž      >,stmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_mac;qt8macirqeth_wake_irqŠ;•rmii” ¢ ´ ©stmmaceth'<ž=®¿>Ò?å µdisabledmdiosnps,dwmac-mdio+ethernet-phy@2ethernet-phy-ieee802.3-c22€ž "î;defaultI@A¢ ¸Ä;stmmac-axi-config Ä=rx-queues-config*Ä>queue0tx-queues-config@Ä?queue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20a€ÿ¾ ž ­ ¬ « ª(,stmmacethclk_mac_refpclk_macaclk_mac;y|8macirqeth_wake_irq” ¢ a ©stmmaceth'BžC®¿DÒEåµokayVoutputŠF •rgmii-idcG;defaultIHIJKLmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22€;defaultIMnN ~†  �3ÄFstmmac-axi-config ÄCrx-queues-config*ÄDqueue0tx-queues-config@ÄEqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshc€ÿ¿¼ � � Œ Ì ëÂn6 ëÂ(ž Œ � Ž � �,corebusaxiblocktimer ;ˆœ ëÂ;defaultINOPQ” (¢ A B C D E©corebusaxiblocktimerµokayª´ÆÕÛãñGý:mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc€ÿÁ@ ž ¹ ¸ — ˜,biuciuciu-driveciu-sample  ;‰œ ëÂ;default IRST” ¢ g©reset µdisabledmmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc€ÿÂ@ ž » º ™ š,biuciuciu-driveciu-sample  ;Šœ ëÂ;default IUVW” ¢ h©reset µdisabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc€ÿÃ@ ž ( ' • –,biuciuciu-driveciu-sample  ;…œðÑ€;defaultIXYZ[” ¢ ½©resetZµokayª´3DOñ\ý]dma-controller@ffd60000arm,pl330arm,primecell€ÿÖ@ž ^ ,apb_pclkl;]hÄ0phy@ffdc0000rockchip,rk3528-naneng-combphy€ÿܼ {Ìõáž { ³ ´ ,refapbpipe” ¢ c e©phyapbŠBœ^ µdisabledÄchosen²serial0:1500000n8adc-keys-0 adc-keys¾_ÊbuttonsÛw@õdbutton-maskromMASK �adc-keys-1 adc-keys¾_ÊbuttonsÛw@õdbutton-recovery RECOVERY hleds gpio-leds;defaultI`aled-0.4on Bheartbeat –3 Kheartbeatled-1.4onBstatus –3  Kdefault-onregulator-0v6-vcc-ddrregulator-fixed avcc0v6_ddrp„– 'À® 'ÀÆbregulator-0v9-vddregulator-fixedavdd_0v9p„– » ® » Æbregulator-1v1-vcc-ddrregulator-fixedavcc_ddrp„–Èà®ÈàÆbregulator-1v8-vccregulator-fixedavcc_1v8p„–w@®w@ÆGÄ:regulator-3v3-vccregulator-fixedavcc_3v3p„–2Z ®2Z ÆbÄGregulator-3v3-vcc-sdregulator-fixed –3;defaultIc avcc3v3_sd–2Z ®2Z ÆGÄ\regulator-5v0-vcc-sysregulator-fixed avcc5v0_sysp„–LK@®LK@Äbregulator-5v0-usb2-hostregulator-fixedÑ –3 ;defaultId ausb2_host_5v–LK@®LK@Æbregulator-vccio-sdregulator-gpio –3;defaultIe avccio_sd–w@®2Z äw@2Z ÆbÄ]regulator-vdd-armpwm-regulatorëfˆðbavdd_armp„– b®ShûúÄregulator-vdd-logicpwm-regulatorëgˆðb avdd_logicp„– Áè®Y°ûúÄ/ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4ethernet0i2c1mmc0mmc1serial0cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesreg-namesbus-rangeclock-namesinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-lanesphysphy-namesresetsreset-namesstatusassigned-clocksassigned-clock-rates#reset-cells#power-domain-cellspm_qosmali-supplydmasdma-namesreg-io-widthreg-shiftpinctrl-namespinctrl-0wakeup-source#pwm-cells#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useclock_in_outphy-supplyreset-assert-usreset-deassert-usreset-gpiosmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthrockchip,default-sample-phasecap-sd-highspeeddisable-wpsd-uhs-sdr104#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highstatespwmspwm-supplyregulator-settling-time-up-us