Ð þí†m8~�(Ý~Xarmsom,sige1rockchip,rk3528 + 7ArmSoM Sige1aliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/ethernet@ffbe0000e/soc/i2c@ffa50000j/soc/mmc@ffbf0000o/soc/mmc@ffc30000t/soc/mmc@ffc10000y/soc/serial@ff9f0000�/soc/serial@ffa00000cpus+cpu-mapcluster0core0‰core1‰core2‰core3‰cpu@0arm,cortex-a53�‘cpu�psci«²ÆÑcpu@1arm,cortex-a53�‘cpu�psci«²ÆÑcpu@2arm,cortex-a53�‘cpu�psci«²ÆÑcpu@3arm,cortex-a53�‘cpu�psci«²ÆÑfirmwarescmi arm,scmi-smcÙ‚ä +protocol@14�êÑopp-table-cpuoperating-points-v2÷Ñopp-1200000000G†Œ  Yø YøÈàœ@opp-1416000000Tfr  HHÈàœ@opp-1608000000_Ø"  à˜à˜Èàœ@opp-1800000000kIÒ  Ô¼Ô¼Èàœ@opp-2016000000x)¸  ÈàÈàÈàœ@opp-table-gpuoperating-points-v2Ñ2opp-300000000ᣠ Yø YøB@(opp-500000000Íe  Yø YøB@opp-600000000#ÃF  Yø YøB@opp-700000000)¹'  »  » B@opp-800000000/¯  ~ð~ðB@pinctrlrockchip,rk3528-pinctrl4 +AÑ gpio@ff610000rockchip,gpio-bank�ÿa« r s HGSco {�gpio@ffaf0000rockchip,gpio-bank�ÿ¯« ‘ ’ HISco {�¡ Ñ:gpio@ffb00000rockchip,gpio-bank�ÿ°« $ % HKSco @ {�¡ gpio@ffb10000rockchip,gpio-bank�ÿ±« › œ HLSco ` {�¡ Ñ9gpio@ffb20000rockchip,gpio-bank�ÿ²« ä å HNSco € {�¡ Ñpcfg-pull-up¯Ñpcfg-pull-down¼Ñpcfg-pull-noneËÑpcfg-pull-none-drv-level-0ËØÑpcfg-pull-none-drv-level-2ËØÑpcfg-pull-up-drv-level-2¯ØÑpcfg-pull-none-smtËçÑarmclkclkm1-32k-outüÑxemmcemmc-bus8€üÑXemmc-clküÑYemmc-cmdüÑZemmc-strbüÑ[ethfephyfephym0-led-linküÑKfephym0-led-spdüÑLfspigpuhdmihsmi2c0i2c0m0-xfer üÑ?i2c1i2c2i2c2m1-xfer üÑAi2c3i2c4i2c4-xfer üÑBi2c5i2c6i2c7i2c7-xfer üÑCi2s0i2s1jtagpciepcie20-perstnüÑpdmpmupwm0pwm1pwm2pwm2m0-pinsüÑDpwm3pwm3m0-pinsüÑEpwm4pwm5pwm6pwm7pwrrefrgmiirgmii-miim üÑRrgmii-rx-bus20üÑTrgmii-tx-bus20üÑSrgmii-rgmii-clk üÑUrgmii-rgmii-bus@ü ÑVscrsdio0sdio0-bus4@üÑ\sdio0-clküÑ]sdio0-cmdüÑ^sdio1sdio1-bus4@ü Ñasdio1-clküÑbsdio1-cmdüÑcsdmmcsdmmc-bus4@üÑdsdmmc-clküÑesdmmc-cmdüÑfsdmmc-detüÑgsdmmc-vol-ctrl-hüÑtsdmmc-pwren-lüÑpspdifspi0spi1tsi0tsi1uart0uart0m0-xfer üÑ5uart1uart2uart2m1-xfer ü Ñ6uart2m1-ctsnü Ñ7uart2m1-rtsnü Ñ8uart3uart4uart5uart6uart7bluetoothbt-reg-on-hüÑ;bt-wake-host-hüÑ<host-wake-bt-hüÑ=ethernetgmac1-rstn-lü ÑWledsg-ledü Ñlr-ledü Ñmrtcrtc-int-lüÑ@usbusb20-host1-drv-hü Ñqusb20-host2-drv-hüÑrusb20-otg0-drv-hü Ñswifiwifi-reg-on-hüÑwwifi-wake-host-hüÑ`psciarm,psci-1.0arm,psci-0.2¤smcreserved-memory+Ashmem@10f000arm,scmi-shmem�ð Ñ timerarm,armv8-timer0H   clock-xin24m fixed-clockn6!xin24mêÑclock-gmac50m fixed-clockúð€!gmac0êÑsoc simple-busAüüD+pcie@fe000000*rockchip,rk3528-pcierockchip,rk3568-pcie0�þ@þOü4dbiapbconfig>ÿ(« ° ± ² ® ¯$Haclk_mstaclk_slvaclk_dbipclkaux‘pciHHœ�š›™žTsyspmcmsglegacyerrmsi�d`w…–¥¯ ´pcie-phy¡ TAüüü ü à@¾ d b Åpwrpipe+ÑokayØdefaultæ ðülegacy-interrupt-controller{  H›�Ñinterrupt-controller@fed01000 arm,gic-400@�þÐþÐ þÐ@ þÐ`  H {�Ñqos@ff200000rockchip,rk3528-qossyscon�ÿ qos@ff200080rockchip,rk3528-qossyscon�ÿ € qos@ff200100rockchip,rk3528-qossyscon�ÿ  qos@ff200200rockchip,rk3528-qossyscon�ÿ  qos@ff200280rockchip,rk3528-qossyscon�ÿ € qos@ff200300rockchip,rk3528-qossyscon�ÿ  qos@ff200380rockchip,rk3528-qossyscon�ÿ € qos@ff210000rockchip,rk3528-qossyscon�ÿ! qos@ff210080rockchip,rk3528-qossyscon�ÿ!€ qos@ff220000rockchip,rk3528-qossyscon�ÿ" Ñqos@ff220080rockchip,rk3528-qossyscon�ÿ"€ Ñqos@ff240000rockchip,rk3528-qossyscon�ÿ$ qos@ff250000rockchip,rk3528-qossyscon�ÿ% Ñqos@ff260000rockchip,rk3528-qossyscon�ÿ& Ñqos@ff270000rockchip,rk3528-qossyscon�ÿ' Ñ qos@ff270080rockchip,rk3528-qossyscon�ÿ'€ Ñ!qos@ff270100rockchip,rk3528-qossyscon�ÿ' Ñ"qos@ff270200rockchip,rk3528-qossyscon�ÿ' Ñ#qos@ff270280rockchip,rk3528-qossyscon�ÿ'€ Ñ$qos@ff270300rockchip,rk3528-qossyscon�ÿ' Ñ%qos@ff270380rockchip,rk3528-qossyscon�ÿ'€ Ñ&qos@ff270480rockchip,rk3528-qossyscon�ÿ'€ Ñ'qos@ff270500rockchip,rk3528-qossyscon�ÿ' Ñ(qos@ff280000rockchip,rk3528-qossyscon�ÿ( Ñ)qos@ff280080rockchip,rk3528-qossyscon�ÿ(€ Ñ*qos@ff280100rockchip,rk3528-qossyscon�ÿ( Ñ+qos@ff280180rockchip,rk3528-qossyscon�ÿ(€ Ñ,qos@ff280200rockchip,rk3528-qossyscon�ÿ( Ñ-qos@ff280280rockchip,rk3528-qossyscon�ÿ(€ Ñ.qos@ff280300rockchip,rk3528-qossyscon�ÿ( Ñ/qos@ff280380rockchip,rk3528-qossyscon�ÿ(€ Ñ0qos@ff280400rockchip,rk3528-qossyscon�ÿ( Ñ1syscon@ff340000rockchip,rk3528-vpu-grfsyscon�ÿ4€ÑMsyscon@ff348000$rockchip,rk3528-pipe-phy-grfsyscon�ÿ4€€Ñjsyscon@ff360000rockchip,rk3528-vo-grfsyscon�ÿ6ÑGclock-controller@ff4a0000rockchip,rk3528-cru�ÿJ˜ t          z y  LL€FÏq;šÊ;]ÁQ–æ²€Íeúð€õáðÑ€ ëÂá£Cýׄ#ÃFúð€õásY@Íe« Hxin24mgmac0ê1Ñ syscon@ff540000rockchip,rk3528-ioc-grfsyscon�ÿTÑ power-management@ff600000&rockchip,rk3528-pmusysconsimple-mfd�ÿ` power-controller!rockchip,rk3528-power-controller>+Ñ power-domain@4�« Ð ËR>power-domain@5�R> Ñdisabledpower-domain@6�R>power-domain@7�$R !"#$%&'(>power-domain@8�$R)*+,-./01>gpu@ff700000"rockchip,rk3528-maliarm,mali-450�ÿp гÜ@ᣫ Ð HbuscoreTHXYV\]Z["Tgpgpmmupppp0ppmmu0pp1ppmmu1²2¡ ¾ wÑokayY3spi@ff9c0000(rockchip,rk3528-spirockchip,rk3066-spi�ÿœ« â áHspiclkapb_pclk Hƒe44jtxrx¡ + Ñdisabledspi@ff9d0000(rockchip,rk3528-spirockchip,rk3066-spi�ÿ�« ž �Hspiclkapb_pclk H„e44jtxrx¡ + Ñdisabledserial@ff9f0000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿŸ«  kHbaudclkapb_pclk H(e4 4t�ÑokayØdefaultæ5serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿŸ€«  ëHbaudclkapb_pclk H)e4 4 ¡ t� Ñdisabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿ «   Hbaudclkapb_pclk H*e4 4 ¡ t�ÑokayjtxrxØdefault æ678‹bluetoothbrcm,bcm43438-bt« uHlpo ›9 :H Thost-wakeupØdefault æ;<= ¯:¾Ê>serial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿ €«  ìHbaudclkapb_pclk H+e44¡ t� Ñdisabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿ¡«  1Hbaudclkapb_pclk H,e44¡ t� Ñdisabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿ¡€« " ¡Hbaudclkapb_pclk H-e44¡ t� Ñdisabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿ¢« % ¢Hbaudclkapb_pclk H.e44¡ t� Ñdisabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uart�ÿ¢€« ( £Hbaudclkapb_pclk H/e44¡ t� Ñdisabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ¥« ß Þ Hi2cpclk H=¡ +ÑokayØdefaultæ?rtc@51haoyu,hym8563�Qê HØdefaultæ@×i2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ¥€« Ý Ü Hi2cpclk H>¡ + Ñdisabledi2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ¦« j i Hi2cpclk H?ØdefaultæA+ Ñdisabledi2c@ffa68000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ¦€« ¥ ¤ Hi2cpclk H@¡ + Ñdisabledi2c@ffa70000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ§« 3 2 Hi2cpclk HAØdefaultæB¡ + Ñdisabledi2c@ffa78000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ§€« § ¦ Hi2cpclk HB¡ + Ñdisabledi2c@ffa80000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ¨« © ¨ Hi2cpclk HC¡ + Ñdisabledi2c@ffa88000(rockchip,rk3528-i2crockchip,rk3399-i2c�ÿ¨€« 5 4 Hi2cpclk HDØdefaultæC¡ + Ñdisabledpwm@ffa90000(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©« o n Hpwmpclkå Ñdisabledpwm@ffa90010(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©« o n Hpwmpclkå Ñdisabledpwm@ffa90020(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ© « o n HpwmpclkåÑokayØdefaultæDÑvpwm@ffa90030(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©0« o n HpwmpclkåÑokayØdefaultæEÑupwm@ffa98000(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©€« r q Hpwmpclkå Ñdisabledpwm@ffa98010(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©€« r q Hpwmpclkå Ñdisabledpwm@ffa98020(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©€ « r q Hpwmpclkå Ñdisabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwm�ÿ©€0« r q Hpwmpclkå Ñdisabledadc@ffae0000rockchip,rk3528-saradc�ÿ®« à ÂHsaradcapb_pclk HŒ¡ ¾ o Åsaradc-apbðÑokay>Ñkethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20a�ÿ½0«      >Hstmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_macHqtTmacirqeth_wake_irqFrmii¡ ¾ ´ Åstmmaceth4G"H2CIVJi Ñdisabledmdiosnps,dwmac-mdio+ethernet-phy@2ethernet-phy-ieee802.3-c22�« "rØdefaultæKL¾ ¸ÑFstmmac-axi-config„ŽžÑHrx-queues-config®ÑIqueue0tx-queues-configÄÑJqueue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20a�ÿ¾ « ­ ¬ « ª(Hstmmacethclk_mac_refpclk_macaclk_macHy|Tmacirqeth_wake_irq¡ ¾ a Åstmmaceth4M"N2COVPiÑokayÚoutputQ rgmii-idçØdefaultæRSTUVmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22�ØdefaultæWòN †  ð ÑQstmmac-axi-config„ŽžÑNrx-queues-config®ÑOqueue0tx-queues-configÄÑPqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshc�ÿ¿ � � Œ  ëÂn6 ëÂ(« Œ � Ž � �Hcorebusaxiblocktimer Hˆ ëÂØdefaultæXYZ[¡ (¾ A B C D EÅcorebusaxiblocktimerÑokay",>MS[iu>mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc�ÿÁ@ « ¹ ¸ — ˜Hbiuciuciu-driveciu-sample‚ H‰ ëÂØdefault æ\]^¡ ¾ gÅresetÑokay"�ž«Á_ÌM[Óiu>+wifi@1brcm,bcm4329-fmac�« uHlpo :H Thost-wakeØdefaultæ`mmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc�ÿÂ@ « » º ™ šHbiuciuciu-driveciu-sample‚ HŠ ëÂØdefault æabc¡ ¾ hÅreset Ñdisabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc�ÿÃ@ « ( ' • –Hbiuciuciu-driveciu-sample‚ H…ðÑ€Ødefaultædefg¡ ¾ ½ÅresetáZÑokay",�ÿÓihuidma-controller@ffd60000arm,pl330arm,primecell�ÿÖ@« ^ Hapb_pclklH Ñ4phy@ffdc0000rockchip,rk3528-naneng-combphy�ÿÜ {õá« { ³ ´ Hrefapbpipe¡ ¾ c eÅphyapb,7MIjÑokayÑchosen_serial0:1500000n8adc-keys adc-keyskkwbuttonsˆw@¢dbutton-maskrom°MASKROM¶�Áleds gpio-ledsØdefaultælmled-0Ûáon ïheartbeat ö9  øheartbeatled-1Ûáonïstatus ö9  ødefault-onregulator-0v6-vcc-ddrregulator-fixed vcc0v6_ddr1C 'À[ 'Àsnregulator-0v9-vddregulator-fixedvdd_0v91C » [ » snregulator-1v1-vcc-ddrregulator-fixedvcc_ddr1CÈà[Èàsnregulator-1v8-vccregulator-fixedvcc_1v81Cw@[w@sÑ>regulator-1v8-vcc-ddrregulator-fixed vcc1v8_ddr1Cw@[w@snregulator-3v3-vccregulator-fixedvcc_3v31C2Z [2Z soÑregulator-3v3-vcc-sdregulator-fixed öØdefaultæp vcc3v3_sdC2Z [2Z sÑhregulator-5v0-vcc-sysregulator-fixed vcc5v0_sys1CLK@[LK@soÑnregulator-5v0-vcc-usb1-hostregulator-fixed~ ö Ødefaultæqvcc5v0_usb1_hostCLK@[LK@snregulator-5v0-vcc-usb2-hostregulator-fixed~ öØdefaultærvcc5v0_usb2_hostCLK@[LK@snregulator-5v0-vcc-usb-otgregulator-fixed~ ö: Ødefaultæsvcc5v0_usb_otgCLK@[LK@snregulator-vcc-dcinregulator-fixed vcc_dcin1Ñoregulator-vccio-sdregulator-gpio öØdefaultæt vccio_sdCw@[2Z ‘w@2Z snÑiregulator-vdd-armpwm-regulator˜uˆ�nvdd_arm1C b[Sh¨úÑregulator-vdd-logicpwm-regulator˜vˆ�n vdd_logic1C Áè[Y°¨úÑ3sdio-pwrseqmmc-pwrseq-simpleØdefaultæwxÆÈ ð:Ñ_ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4ethernet0i2c0mmc0mmc1mmc2serial0serial2cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesreg-namesbus-rangeclock-namesinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-lanesphysphy-namesresetsreset-namesstatuspinctrl-namespinctrl-0reset-gpiosvpcie3v3-supplyassigned-clocksassigned-clock-rates#reset-cells#power-domain-cellspm_qosmali-supplydmasdma-namesreg-io-widthreg-shiftuart-has-rtsctsdevice-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplywakeup-source#pwm-cells#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useclock_in_outphy-supplyreset-assert-usreset-deassert-usmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcsd-uhs-sdr104rockchip,default-sample-phasedisable-wp#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highstatespwmspwm-supplyregulator-settling-time-up-uspost-power-on-delay-ms