Ð þíëô8ßø( üßÀkobol,helios64rockchip,rk3399 +7Kobol Helios64aliases=/pinctrl/gpio@ff720000C/pinctrl/gpio@ff730000I/pinctrl/gpio@ff780000O/pinctrl/gpio@ff788000U/pinctrl/gpio@ff790000[/i2c@ff3c0000`/i2c@ff110000e/i2c@ff120000j/i2c@ff130000o/i2c@ff3d0000t/i2c@ff140000y/i2c@ff150000~/i2c@ff160000ƒ/i2c@ff3e0000ˆ/serial@ff180000�/serial@ff190000˜/serial@ff1a0000 /serial@ff1b0000¨/serial@ff370000°/spi@ff1c0000µ/spi@ff1d0000º/spi@ff1e0000¿/spi@ff350000Ä/spi@ff1f0000É/spi@ff200000Î/ethernet@fe300000Ø/mmc@fe320000Ý/mmc@fe330000cpus+cpu-mapcluster0core0âcore1âcore2âcore3âcluster1core0âcore1âcpu@0æcpuarm,cortex-a53òöpsciå-dG W€d@vƒ€�@¢€¯ À Ô ßcpu@1æcpuarm,cortex-a53òöpsciå-dG W€d@vƒ€�@¢€¯ À Ô ßcpu@2æcpuarm,cortex-a53òöpsciå-dG W€d@vƒ€�@¢€¯ À Ô ßcpu@3æcpuarm,cortex-a53òöpsciå-dG W€d@vƒ€�@¢€¯ À Ô ßcpu@100æcpuarm,cortex-a72òöpsci -´G WÀd@vƒ€�@¢¯ÀÔßthermal-idleç'óôcpu@101æcpuarm,cortex-a72òöpsci -´G WÀd@vƒ€�@¢¯ÀÔßthermal-idleç'óôl2-cache-cluster0cacheYf@xß l2-cache-cluster1cacheYf@xßidle-statespscicpu-sleeparm,idle-state*;Rxóúc„ß cluster-sleeparm,idle-state*;R�óôcÐß display-subsystemrockchip,display-subsystemtmemory-controllerrockchip,rk3399-dmcz‡¨–dmc_clk ¢disabledpmu_a53arm,cortex-a53-pmu©pmu_a72arm,cortex-a72-pmu©psci arm,psci-1.0ýsmctimerarm,armv8-timer@©   ´xin24m fixed-clockËn6Ûxin24mîߊpcie@f8000000rockchip,rk3399-pcie òøýûaxi-baseapb-baseæpci+" ÅÄG –aclkaclk-perfhclkpm0©123,syslegacyclient<`O]l t,ypcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38ƒ‚úúà�ûàûà8Š‚ƒ„…†�€(‘coremgmtmgmt-stickypipepmpclkaclk¢okay �¦°ÀÐàinterrupt-controllerðßpcie-ep@f8000000rockchip,rk3399-pcie-ep òýúûapb-basemem-base ÅÄG –aclkaclk-perfhclkpm¦8Š‚ƒ„…†�€(‘coremgmtmgmt-stickypipepmpclkaclk t,ypcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-3 1default? ¢disabledethernet@fe300000rockchip,rk3399-gmacòþ0© ,macirq8ighfjÕfM–stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macI Љ ‘stmmacethW!d¢okayo"†¦–input£rgmii¬#1default?$%· À(É ß'ÃP ô&mmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcòþ1@©@ðÑ€ îMœ�–biuciuciu-driveciu-sampleI Šy‘reset ¢disabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcòþ2@©AðÑ€†Í ë ÎLš›–biuciuciu-driveciu-sampleI Šz‘reset¢okay2< M'V1default?()*+a,m-mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1òþ3© z!†N ëÂNð–clk_xinclk_ahbÛemmc_cardclockît. yphy_arasanI �¢okay2¡°m/ߌusb@fe380000 generic-ehciòþ8©ÈÉ0t1yusb ¢disabledusb@fe3a0000 generic-ohciòþ:©ÈÉ0t1yusb ¢disabledusb@fe3c0000 generic-ehciòþ<©ÊË2t3yusb ¢disabledusb@fe3e0000 generic-ohciòþ>© ÊË2t3yusb ¢disableddebug@fe430000&arm,coresight-cpu-debugarm,primecellòþCM –apb_pclkâdebug@fe432000&arm,coresight-cpu-debugarm,primecellòþC M –apb_pclkâdebug@fe434000&arm,coresight-cpu-debugarm,primecellòþC@M –apb_pclkâdebug@fe436000&arm,coresight-cpu-debugarm,primecellòþC`M –apb_pclkâdebug@fe610000&arm,coresight-cpu-debugarm,primecellòþaL –apb_pclkâdebug@fe710000&arm,coresight-cpu-debugarm,primecellòþqL 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compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4spi0spi1spi2spi3spi4spi5ethernet0mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandleduration-usexit-latency-uscache-levelcache-unifiedentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesep-gpiosnum-lanesvpcie12v-supplyvpcie3v3-supplyvpcie1v8-supplyvpcie0v9-supplyinterrupt-controllermax-functionsrockchip,max-outbound-regionspinctrl-namespinctrl-0power-domainsrockchip,grfsnps,txpblassigned-clock-parentsassigned-clocksclock_in_outphy-modephy-supplyrx_delaytx_delaysnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiomax-frequencyfifo-depthassigned-clock-ratesbus-widthcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs200-1_8vnon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#trigger-source-cells#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsi2c-scl-rising-time-nsi2c-scl-falling-time-nsreg-shiftreg-io-widthdmasdma-namesspi-max-frequencym25p,fast-readpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supply#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsaudio-supplybt656-supplygpio1830-supplysdmmc-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daigpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltstdout-pathpwmscooling-levelslabeldefault-stateenable-active-highstartup-delay-us