Ð þíw8o (bohrockchip,r88rockchip,rk3368 + 7Rockchip R88aliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000ƒ/serial@ff690000‹/serial@ff1b0000“/serial@ff1c0000›/spi@ff110000 /spi@ff120000¥/spi@ff130000ª/ethernet@ff290000´/mmc@ff0d0000¹/mmc@ff0f0000cpus+cpu-mapcluster0core0¾core1¾core2¾core3¾cluster1core0¾core1¾core2¾core3¾ cpu@0Âcpuarm,cortex-a53ÎÒpsciàïcpu@1Âcpuarm,cortex-a53ÎÒpsciàïcpu@2Âcpuarm,cortex-a53ÎÒpsciàïcpu@3Âcpuarm,cortex-a53ÎÒpsciàï cpu@100Âcpuarm,cortex-a53ÎÒpsciàïcpu@101Âcpuarm,cortex-a53ÎÒpsciàïcpu@102Âcpuarm,cortex-a53ÎÒpsciàïcpu@103Âcpuarm,cortex-a53ÎÒpsciàïdisplay-subsystemrockchip,display-subsystem÷  ýdisabledarm-pmuarm,cortex-a53-pmu`pqrstuvw  psci arm,psci-0.2Ùsmctimerarm,armv8-timer0 ÿÿ ÿ ÿoscillator fixed-clock"n62xin24mEïEmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ @RðÑ€ ` È D r vgbiuciuciu-driveciu-samples  ~ €…reset ýdisabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ @RðÑ€ ` É E s wgbiuciuciu-driveciu-samples !~ �…resetýokay‘ E¡ ¸ÂÓàö default  '3mmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ@RðÑ€ ` Ë G u ygbiuciuciu-driveciu-samples #~ ƒ…resetýokay¸@ödefault saradc@ff100000rockchip,saradcÎÿ $R` I [gsaradcapb_pclk~ W …saradc-apbýokaydspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiÎÿ` A Rgspiclkapb_pclk ,default+ ýdisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiÎÿ` B Sgspiclkapb_pclk -default+ ýdisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiÎÿ` C Tgspiclkapb_pclk )default !"+ ýdisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ >+gi2c` Ndefault# ýdisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ ?+gi2c` Odefault$ ýdisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ @+gi2c` Pdefault% ýdisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ A+gi2c` Qdefault& ýdisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` M Ugbaudclkapb_pclk 7pz ýdisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` N Vgbaudclkapb_pclk 8pz ýdisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` P Xgbaudclkapb_pclk :pz ýdisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` Q Ygbaudclkapb_pclk ;pz ýdisableddma-controller@ff250000arm,pl330arm,primecellÎÿ%@‡’­` à gapb_pclkthermal-zonescpu-thermalÄdÚˆè'tripscpu_alert0ø$øÐÉpassiveï(cpu_alert1ø8€ÐÉpassiveï)cpu_critøsÐ Écriticalcooling-mapsmap0(0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1)0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermalÄdÚˆè'tripsgpu_alert0ø8€ÐÉpassiveï*gpu_critøÁ8Ð Écriticalcooling-mapsmap0*0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadcÎÿ( %` H Zgtsadcapb_pclk~ Ÿ …tsadc-apbinitdefaultsleep+#,-+7Msýokayd{ï'ethernet@ff290000rockchip,rk3368-gmacÎÿ) –macirq¦-8`  f g c € Å ]Mgstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac~ B …stmmacethýokay³.¾rmiiÇoutput Ô/ ä ú'B@default00mdiosnps,dwmac-mdio+usb@ff500000 generic-ehciÎÿP ` Âýokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2ÎÿX ` Ágotg!host);J€€@@ ýokaydma-controller@ff600000arm,pl330arm,primecellÎÿ`@‡’­`  gapb_pclkïFi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿe` Lgi2c <default1+ýokaysyr827@40silergy,syr827Î@Yvvdd_cpu…,¡ ß4¹ã`Ñ@æú 2rtc@51haoyu,hym8563ÎQE2xin32kï]i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿf =+gi2c` Mdefault3 ýdisabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿhdefault4` _ ýdisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿhdefault5` _ ýdisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿh ` _ ýdisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿh0default6` _ ýdisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿi` O Wgbaudclkapb_pclk 9default7pzýokaymbox@ff6b0000rockchip,rk3368-mailboxÎÿk0’“”•` E gpclk_mailbox" ýdisabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdÎÿspower-controller!rockchip,rk3368-power-controller.+ïIpower-domain@12Î ð` Ê Í Ì È Æ Ç ¾ Ô Õ Ö Ù Ñ Û c h g n o r s f d d h i l k j n m$B89:;<=>?@.power-domain@14Î ` Ð Ü o p BABC.power-domain@16Î` Á À @BD.syscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdÎÿs€ïQio-domains&rockchip,rk3368-pmu-io-voltage-domainýokayITreboot-modesyscon-reboot-mode_fRBÃrRBÀRBà �RBÃclock-controller@ff760000rockchip,rk3368-cruÎÿv`Egxin24m¦-Eœï syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdÎÿwï-io-domains"rockchip,rk3368-io-voltage-domainýokay©¶ÄÔwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtÎÿ€` p Oýokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timerÎÿ�  B` a U gpclktimerspdif@ff880000rockchip,rk3368-spdifÎÿˆ 6` S Ð gmclkhclkàFåtxdefaultGï ýdisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰ (gi2s_clki2s_hclk` T ÎàFFåtxrxï ýdisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰€ 5gi2s_clki2s_hclk` R ÏàFFåtxrxdefaultHï ýdisablediommu@ff900800rockchip,iommuÎÿ� ` Ê Ô gaclkifaceI  ýdisablediommu@ff914000rockchip,iommu Îÿ‘@ÿ‘P ` Í Õ gaclkifaceI  ýdisabledvop@ff930000rockchip,rk3368-vop Îÿ“üÿ“ ‘ Æ Ñ6ׄ ëÂ` Æ ¾ Ñgaclk_vopdclk_vophclk_vopKJI ~ d e f …axiahbdclk ýdisabledport+ï endpoint@0ÎRKïNendpoint@1ÎRLïPiommu@ff930300rockchip,iommuÎÿ“ ` Æ Ñ gaclkifaceI  ýdisabledïJdsi@ff960000*rockchip,rk3368-mipi-dsisnps,dw-mipi-dsiÎÿ–@ ` dgpclkbMgdphyI ~ s…apb¦- ýdisabledports+port@0ÎendpointRNïKport@1Îphy@ff968000rockchip,rk3368-dsi-dphyÎÿ–€@` � s grefpclkq~ r…apb ýdisabledïMhdmi@ff980000rockchip,rk3368-dw-hdmiÎÿ˜ g` h m ngiahbisfrcecdefaultOI z¦- ýdisabledports+port@0ÎendpointRPïLport@1Îiommu@ff9a0440rockchip,iommu Îÿš@@ÿš€@  ` Ð Ü gaclkiface ýdisablediommu@ff9a0800rockchip,iommuÎÿš  ` Ð Ü gaclkiface ýdisabledqos@ffad0000rockchip,rk3368-qossysconÎÿ­ ï8qos@ffad0080rockchip,rk3368-qossysconÎÿ­€ ï9qos@ffad0100rockchip,rk3368-qossysconÎÿ­ ï:qos@ffad0180rockchip,rk3368-qossysconÎÿ­€ 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$Xïgpio-keys gpio-keysdefaultYkey-power0 *Z >GPIO PowerDtgpio-leds gpio-ledsled-0 */>r88:green:leddefault[ir-receivergpio-ir-receiver */default\sdio-pwrseqmmc-pwrseq-simple`] gext_clockdefault^_$//ï regulator-vcc18regulator-fixedvvcc_18¡w@¹w@æú 2ïregulator-vcc-hostregulator-fixedO ßZdefault` vvcc_hostæú 2regulator-vcc-ioregulator-fixedvvcc_io¡2Z ¹2Z æú 2ïregulator-vcc-lanregulator-fixedvvcc_lan¡2Z ¹2Z æú ï.regulator-vcc-sysregulator-fixedvvcc_sys¡LK@¹LK@æúï2regulator-vccio-wlregulator-fixed vvccio_wl¡2Z ¹2Z æú ïregulator-vdd-10regulator-fixedvvdd_10¡B@¹B@æú 2 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleportsstatusinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesassigned-clocksassigned-clock-parentsbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeed#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qospmu-supplyvop-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsaudio-supplygpio30-supplygpio1830-supplywifi-supplydmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetassigned-clock-ratesiommusremote-endpointphysphy-names#phy-cellsinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codeenable-active-high