Ð þív¯8oÄ(ëoŒ)tronsmart,orion-r68-metarockchip,rk3368 +7Rockchip Orion R68aliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000ƒ/serial@ff690000‹/serial@ff1b0000“/serial@ff1c0000›/spi@ff110000 /spi@ff120000¥/spi@ff130000ª/ethernet@ff290000´/mmc@ff0c0000¹/mmc@ff0f0000cpus+cpu-mapcluster0core0¾core1¾core2¾core3¾cluster1core0¾core1¾core2¾core3¾ cpu@0Âcpuarm,cortex-a53ÎÒpsciàïcpu@1Âcpuarm,cortex-a53ÎÒpsciàïcpu@2Âcpuarm,cortex-a53ÎÒpsciàïcpu@3Âcpuarm,cortex-a53ÎÒpsciàï cpu@100Âcpuarm,cortex-a53ÎÒpsciàïcpu@101Âcpuarm,cortex-a53ÎÒpsciàïcpu@102Âcpuarm,cortex-a53ÎÒpsciàïcpu@103Âcpuarm,cortex-a53ÎÒpsciàïdisplay-subsystemrockchip,display-subsystem÷  ýdisabledarm-pmuarm,cortex-a53-pmu`pqrstuvw  psci arm,psci-0.2Ùsmctimerarm,armv8-timer0 ÿÿ ÿ ÿoscillator fixed-clock"n62xin24mEïGmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ @Rúð€ ` È D r vgbiuciuciu-driveciu-samples  ~ €…resetýokay‘"úð€›¬È¾defaultÌ Öâmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ @RðÑ€ ` É E s wgbiuciuciu-driveciu-samples !~ �…reset ýdisabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ@RðÑ€ ` Ë G u ygbiuciuciu-driveciu-samples #~ ƒ…resetýokay‘ï *¾default Ìsaradc@ff100000rockchip,saradcÎÿ $8` I [gsaradcapb_pclk~ W …saradc-apbýokayJspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiÎÿ` A Rgspiclkapb_pclk ,¾defaultÌ+ ýdisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiÎÿ` B Sgspiclkapb_pclk -¾defaultÌ+ ýdisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiÎÿ` C Tgspiclkapb_pclk )¾defaultÌ !"+ ýdisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ >+gi2c` N¾defaultÌ# ýdisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ ?+gi2c` O¾defaultÌ$ ýdisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ @+gi2c` P¾defaultÌ% ýdisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ A+gi2c` Q¾defaultÌ& ýdisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` M Ugbaudclkapb_pclk 7V` ýdisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` N Vgbaudclkapb_pclk 8V` ýdisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` P Xgbaudclkapb_pclk :V` ýdisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿ"n6` Q Ygbaudclkapb_pclk ;V`ýokay¾defaultÌ'dma-controller@ff250000arm,pl330arm,primecellÎÿ%@mx“` à gapb_pclkthermal-zonescpu-thermalªdÀˆÎ(tripscpu_alert0Þ$øêÐÉpassiveï)cpu_alert1Þ8€êÐÉpassiveï*cpu_critÞsêÐ Écriticalcooling-mapsmap0õ)0úÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1õ*0úÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermalªdÀˆÎ(tripsgpu_alert0Þ8€êÐÉpassiveï+gpu_critÞÁ8êÐ Écriticalcooling-mapsmap0õ+0úÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadcÎÿ( %` H Zgtsadcapb_pclk~ Ÿ …tsadc-apb¾initdefaultsleepÌ, -,3s ýdisabledï(ethernet@ff290000rockchip,rk3368-gmacÎÿ) JmacirqZ.8`  f g c € Å ]Mgstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac~ B …stmmacethýokayg w/Žinput›0¦rgmii¾defaultÌ1 ¯2 ¿ Õ'B@ê0ómdiosnps,dwmac-mdio+usb@ff500000 generic-ehciÎÿP ` Âýokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2ÎÿX ` Ágotgüotg%€€@@ ýokaydma-controller@ff600000arm,pl330arm,primecellÎÿ`@mx“`  gapb_pclkïHi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿe` Lgi2c <¾defaultÌ3+ýokaysyr827@40silergy,syr827Î@4Qvdd_cpu`,| ß4”ã`¬@ÁÕç4rtc@51haoyu,hym8563ÎQE2xin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿf =+gi2c` M¾defaultÌ5 ýdisabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿhò¾defaultÌ6` _ ýdisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿhò¾defaultÌ7` _ ýdisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿh ò` _ ýdisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmÎÿh0ò¾defaultÌ8` _ ýdisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿi` O Wgbaudclkapb_pclk 9¾defaultÌ9V`ýokaymbox@ff6b0000rockchip,rk3368-mailboxÎÿk0’“”•` E gpclk_mailboxý ýdisabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdÎÿspower-controller!rockchip,rk3368-power-controller +ïKpower-domain@12Î ð` Ê Í Ì È Æ Ç ¾ Ô Õ Ö Ù Ñ Û c h g n o r s f d d h i l k j n m$:;<=>?@AB power-domain@14Î ` Ð Ü o p CDE power-domain@16Î` Á À @F syscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdÎÿs€ïSio-domains&rockchip,rk3368-pmu-io-voltage-domain ýdisabledreboot-modesyscon-reboot-mode$+RBÃ7RBÃERBà URBÃclock-controller@ff760000rockchip,rk3368-cruÎÿv`Ggxin24mZ.Eaï syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdÎÿwï.io-domains"rockchip,rk3368-io-voltage-domain ýdisabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtÎÿ€` p Oýokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timerÎÿ�  B` a U gpclktimerspdif@ff880000rockchip,rk3368-spdifÎÿˆ 6` S Ð gmclkhclknHstx¾defaultÌI} ýdisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰ (gi2s_clki2s_hclk` T ÎnHHstxrx} ýdisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰€ 5gi2s_clki2s_hclk` R ÏnHHstxrx¾defaultÌJ} ýdisablediommu@ff900800rockchip,iommuÎÿ� ` Ê Ô gaclkifaceŽK œ ýdisablediommu@ff914000rockchip,iommu Îÿ‘@ÿ‘P ` Í Õ gaclkifaceœŽK © ýdisabledvop@ff930000rockchip,rk3368-vop Îÿ“üÿ“ g Æ ÑÄׄ ëÂ` Æ ¾ Ñgaclk_vopdclk_vophclk_vopÙLŽK ~ d e f …axiahbdclk ýdisabledport+ï endpoint@0ÎàMïPendpoint@1ÎàNïRiommu@ff930300rockchip,iommuÎÿ“ ` Æ Ñ gaclkifaceŽK œ ýdisabledïLdsi@ff960000*rockchip,rk3368-mipi-dsisnps,dw-mipi-dsiÎÿ–@ ` dgpclkðOõdphyŽK ~ s…apbZ. ýdisabledports+port@0ÎendpointàPïMport@1Îphy@ff968000rockchip,rk3368-dsi-dphyÎÿ–€@` � s grefpclkÿ~ r…apb ýdisabledïOhdmi@ff980000rockchip,rk3368-dw-hdmiÎÿ˜ g` h m ngiahbisfrcec¾defaultÌQŽK `Z. ýdisabledports+port@0ÎendpointàRïNport@1Îiommu@ff9a0440rockchip,iommu Îÿš@@ÿš€@  ` Ð Ü gaclkifaceœ ýdisablediommu@ff9a0800rockchip,iommuÎÿš  ` Ð Ü gaclkifaceœ ýdisabledqos@ffad0000rockchip,rk3368-qossysconÎÿ­ ï:qos@ffad0080rockchip,rk3368-qossysconÎÿ­€ ï;qos@ffad0100rockchip,rk3368-qossysconÎÿ­ ï<qos@ffad0180rockchip,rk3368-qossysconÎÿ­€ ï=qos@ffad0200rockchip,rk3368-qossysconÎÿ­ ï>qos@ffad0280rockchip,rk3368-qossysconÎÿ­€ ï?qos@ffad0300rockchip,rk3368-qossysconÎÿ­ ï@qos@ffad0380rockchip,rk3368-qossysconÎÿ­€ ïAqos@ffad0400rockchip,rk3368-qossysconÎÿ­ ïBqos@ffae0000rockchip,rk3368-qossysconÎÿ® ïCqos@ffae0100rockchip,rk3368-qossysconÎÿ® ïDqos@ffae0180rockchip,rk3368-qossysconÎÿ®€ ïEqos@ffaf0000rockchip,rk3368-qossysconÎÿ¯ ïFefuse@ffb00000rockchip,rk3368-efuseÎÿ° +` q gpclk_efusecpu-leakage@17Îtemp-adjust@1fÎinterrupt-controller@ffb71000 arm,gic-400 @Îÿ·ÿ· ÿ·@ ÿ·`   ÿïpinctrlrockchip,rk3368-pinctrlZ.0S+=gpio@ff750000rockchip,gpio-bankÎÿu` @ QDT ï]gpio@ff780000rockchip,gpio-bankÎÿx` A RDT gpio@ff790000rockchip,gpio-bankÎÿy` B SDT ï[gpio@ff7a0000rockchip,gpio-bankÎÿz` C TDT ï2pcfg-pull-up`ïVpcfg-pull-downmïYpcfg-pull-none|ïWpcfg-pull-none-12ma|‰ ïXemmcemmc-clk˜Tïemmc-cmd˜Uïemmc-pwr˜Vemmc-bus1˜Vemmc-bus4@˜VVVVemmc-bus8€˜UUUUUUUUïemmc-reset˜WïZgmacrgmii-pinsð˜WWWX X XXX XWWWWWWï1rmii-pins ˜WWWX X XWWWWhdmihdmi-i2c-xfer ˜WWïQi2c0i2c0-xfer ˜WWï3i2c1i2c1-xfer ˜WWï5i2c2i2c2-xfer ˜ WWï#i2c3i2c3-xfer ˜WWï$i2c4i2c4-xfer ˜WWï%i2c5i2c5-xfer ˜WWï&i2si2s-8ch-bus�˜ W WWWWWWWWïJpwm0pwm0-pin˜Wï6pwm1pwm1-pin˜Wï7pwm3pwm3-pin˜Wï8sdio0sdio0-bus1˜Vsdio0-bus4@˜VVVVsdio0-cmd˜Vsdio0-clk˜Wsdio0-cd˜Vsdio0-wp˜Vsdio0-pwr˜Vsdio0-bkpwr˜Vsdio0-int˜Vsdmmcsdmmc-clk˜ Tï sdmmc-cmd˜ Uï sdmmc-cd˜ Uïsdmmc-bus1˜Usdmmc-bus4@˜UUUUïspdifspdif-tx˜WïIspi0spi0-clk˜Vïspi0-cs0˜Vïspi0-cs1˜Vspi0-tx˜Vïspi0-rx˜Vïspi1spi1-clk˜Vïspi1-cs0˜Vïspi1-cs1˜Vspi1-rx˜Vïspi1-tx˜Vïspi2spi2-clk˜ Vïspi2-cs0˜ Vï"spi2-rx˜ Vï!spi2-tx˜ Vï tsadcotp-pin˜Wï,otp-out˜Wï-uart0uart0-xfer ˜VWuart0-cts˜Wuart0-rts˜Wuart1uart1-xfer ˜VWuart1-cts˜Wuart1-rts˜Wuart2uart2-xfer ˜VWï9uart3uart3-xfer ˜VWuart3-cts˜Wuart3-rts˜Wuart4uart4-xfer ˜VWï'uart4-cts˜Wuart4-rts˜Wpcfg-pull-none-drv-8ma|‰ïTpcfg-pull-up-drv-8ma`‰ïUkeyspwr-key˜Yï\ledsstby-pwren˜ Wï_led-ctl˜Wï^usbhost-vbus-drv˜Wï`chosen¦serial2:115200n8memory@0Âmemory΀emmc-pwrseqmmc-pwrseq-emmcÌZ¾default ²[ïexternal-gmac-clock fixed-clockE"sY@ 2ext_gmacï/gpio-keys gpio-keys¾defaultÌ\key-power¾ ¸] ÌGPIO PowerÒtgpio-leds gpio-ledsled-0 ¸2Ìorion:red:led¾defaultÌ^Ýonled-1 ¸] Ìorion:blue:led¾defaultÌ_Ýoffregulator-vcc18regulator-fixedQvcc_18|w@”w@ÁÕç4ïregulator-vcc-hostregulator-fixed º]¾defaultÌ` Qvcc_hostÁÕç4regulator-vcc-ioregulator-fixedQvcc_io|2Z ”2Z ÁÕç4ïaregulator-vcc-lanregulator-fixedQvcc_lan|2Z ”2Z ÁÕçaï0regulator-vcc-sdregulator-fixedQvcc_sd º2 |w@”2Z çaïregulator-vcc-sysregulator-fixedQvcc_sys|LK@”LK@ÁÕï4regulator-vcc-io-sdregulator-fixed Qvccio_sd|w@”2Z ÁÕçaïregulator-vccio-wlregulator-fixed Qvccio_wl|2Z ”2Z ÁÕçaregulator-vdd-10regulator-fixedQvdd_10|B@”B@ÁÕç4 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleportsstatusinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetassigned-clock-ratesiommusremote-endpointphysphy-names#phy-cellsinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state