Ð þítE8m€(ÅmH#geekbuying,geekboxrockchip,rk3368 +7GeekBoxaliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000ƒ/serial@ff690000‹/serial@ff1b0000“/serial@ff1c0000›/spi@ff110000 /spi@ff120000¥/spi@ff130000ª/ethernet@ff290000´/mmc@ff0f0000cpus+cpu-mapcluster0core0¹core1¹core2¹core3¹cluster1core0¹core1¹core2¹core3¹ cpu@0½cpuarm,cortex-a53ÉÍpsciÛêcpu@1½cpuarm,cortex-a53ÉÍpsciÛêcpu@2½cpuarm,cortex-a53ÉÍpsciÛêcpu@3½cpuarm,cortex-a53ÉÍpsciÛê cpu@100½cpuarm,cortex-a53ÉÍpsciÛêcpu@101½cpuarm,cortex-a53ÉÍpsciÛêcpu@102½cpuarm,cortex-a53ÉÍpsciÛêcpu@103½cpuarm,cortex-a53ÉÍpsciÛêdisplay-subsystemrockchip,display-subsystemò  ødisabledarm-pmuarm,cortex-a53-pmu`ÿpqrstuvw   psci arm,psci-0.2Ôsmctimerarm,armv8-timer0ÿ ÿÿ ÿ ÿoscillator fixed-clockn6-xin24m@êBmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÉÿ @MðÑ€ [ È D r vbbiuciuciu-driveciu-samplen ÿ y €€reset ødisabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÉÿ @MðÑ€ [ É E s wbbiuciuciu-driveciu-samplen ÿ!y �€reset ødisabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÉÿ@MðÑ€ [ Ë G u ybbiuciuciu-driveciu-samplen ÿ#y ƒ€resetøokayŒ–ðÑ€¨¶  Ïdefault Ýsaradc@ff100000rockchip,saradcÉÿ ÿ$ç[ I [bsaradcapb_pclky W €saradc-apb ødisabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiÉÿ[ A Rbspiclkapb_pclk ÿ,ÏdefaultÝ+ ødisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiÉÿ[ B Sbspiclkapb_pclk ÿ-ÏdefaultÝ+ ødisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiÉÿ[ C Tbspiclkapb_pclk ÿ)ÏdefaultÝ+ ødisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ÿ>+bi2c[ NÏdefaultÝ ødisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ÿ?+bi2c[ OÏdefaultÝ ødisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ÿ@+bi2c[ PÏdefaultÝ ødisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ÿA+bi2c[ QÏdefaultÝ  ødisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6[ M Ubbaudclkapb_pclk ÿ7ù ødisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6[ N Vbbaudclkapb_pclk ÿ8ù ødisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6[ P Xbbaudclkapb_pclk ÿ:ù ødisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6[ Q Ybbaudclkapb_pclk ÿ;ù ødisableddma-controller@ff250000arm,pl330arm,primecellÉÿ%@ÿ6[ à bapb_pclkthermal-zonescpu-thermalMdcˆq!tripscpu_alert0�$ø�ÐÄpassiveê"cpu_alert1�8€�ÐÄpassiveê#cpu_crit�s�Ð Äcriticalcooling-mapsmap0˜"0�ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1˜#0�ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermalMdcˆq!tripsgpu_alert0�8€�ÐÄpassiveê$gpu_crit�Á8�Ð Äcriticalcooling-mapsmap0˜$0�ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadcÉÿ( ÿ%[ H Zbtsadcapb_pclky Ÿ €tsadc-apbÏinitdefaultsleepÝ%¬&¶%ÀÖsøokayíê!ethernet@ff290000rockchip,rk3368-gmacÉÿ) ÿmacirq/'8[  f g c € Å ]Mbstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macy B €stmmacethøokay<(GrgmiiPinput] m)ÏdefaultÝ*„0�mdiosnps,dwmac-mdio+usb@ff500000 generic-ehciÉÿP ÿ[ Âøokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2ÉÿX ÿ[ Ábotg–otgž°¿€€@@ øokaydma-controller@ff600000arm,pl330arm,primecellÉÿ`@ÿ6[  bapb_pclkêCi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿe[ Lbi2c ÿ<ÏdefaultÝ++øokaypmic@1brockchip,rk808ÉÏdefaultÝ,- .ÿÎæ/ò/þ/ //"/. :/F/S/` -xin32krk808-clkout2@regulatorsDCDC_REG1m�“ ®`«ã`Ãvdd_cpuDCDC_REG2m�“ ®`«ã`Ãvdd_logDCDC_REG3m�Ãvcc_ddrDCDC_REG4m�“2Z «2Z Ãvcc_ioê LDO_REG1m�“w@«w@ Ãvcc18_flashê LDO_REG2m�“2Z «2Z  Ãvcc33_lcdLDO_REG3m�“B@«B@Ãvdd_10LDO_REG4�“w@«w@Ãvcca_18LDO_REG5m�“w@«2Z  Ãvccio_sdLDO_REG6m�“B@«B@ Ãvdd10_lcdLDO_REG7m�“w@«w@Ãvcc_18LDO_REG8m�“w@«w@ Ãvcc18_lcdSWITCH_REG1Ãvcc_sdSWITCH_REG2m�Ãvcc_lanê(i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿf ÿ=+bi2c[ MÏdefaultÝ0 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syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdÉÿwê'io-domains"rockchip,rk3368-io-voltage-domain ødisabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtÉÿ€[ p ÿOøokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timerÉÿ�  ÿB[ a U bpclktimerspdif@ff880000rockchip,rk3368-spdifÉÿˆ ÿ6[ S Ð bmclkhclkNCStxÏdefaultÝD] ødisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2sÉÿ‰ ÿ(bi2s_clki2s_hclk[ T ÎNCCStxrx] ødisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2sÉÿ‰€ ÿ5bi2s_clki2s_hclk[ R ÏNCCStxrxÏdefaultÝE] ødisablediommu@ff900800rockchip,iommuÉÿ� ÿ[ Ê Ô baclkifacenF | ødisablediommu@ff914000rockchip,iommu Éÿ‘@ÿ‘P ÿ[ Í Õ baclkiface|nF ‰ ødisabledvop@ff930000rockchip,rk3368-vop Éÿ“üÿ“ ÿ] Æ Ñ¤ׄ ëÂ[ Æ ¾ Ñbaclk_vopdclk_vophclk_vop¹GnF y d e f €axiahbdclk ødisabledport+ê endpoint@0ÉÀHêKendpoint@1ÉÀIêMiommu@ff930300rockchip,iommuÉÿ“ ÿ[ Æ Ñ baclkifacenF | ødisabledêGdsi@ff960000*rockchip,rk3368-mipi-dsisnps,dw-mipi-dsiÉÿ–@ ÿ[ dbpclkÐJÕdphynF y s€apb/' ødisabledports+port@0ÉendpointÀKêHport@1Éphy@ff968000rockchip,rk3368-dsi-dphyÉÿ–€@[ � s brefpclkßy r€apb ødisabledêJhdmi@ff980000rockchip,rk3368-dw-hdmiÉÿ˜ ÿg[ h m nbiahbisfrcecÏdefaultÝLnF /' ødisabledports+port@0ÉendpointÀMêIport@1Éiommu@ff9a0440rockchip,iommu Éÿš@@ÿš€@ ÿ [ Ð Ü baclkiface| ødisablediommu@ff9a0800rockchip,iommuÉÿšÿ  [ Ð Ü baclkiface| ødisabledqos@ffad0000rockchip,rk3368-qossysconÉÿ­ ê5qos@ffad0080rockchip,rk3368-qossysconÉÿ­€ ê6qos@ffad0100rockchip,rk3368-qossysconÉÿ­ ê7qos@ffad0180rockchip,rk3368-qossysconÉÿ­€ ê8qos@ffad0200rockchip,rk3368-qossysconÉÿ­ ê9qos@ffad0280rockchip,rk3368-qossysconÉÿ­€ ê:qos@ffad0300rockchip,rk3368-qossysconÉÿ­ ê;qos@ffad0380rockchip,rk3368-qossysconÉÿ­€ ê<qos@ffad0400rockchip,rk3368-qossysconÉÿ­ ê=qos@ffae0000rockchip,rk3368-qossysconÉÿ® ê>qos@ffae0100rockchip,rk3368-qossysconÉÿ® ê?qos@ffae0180rockchip,rk3368-qossysconÉÿ®€ ê@qos@ffaf0000rockchip,rk3368-qossysconÉÿ¯ êAefuse@ffb00000rockchip,rk3368-efuseÉÿ° +[ q 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Psdmmc-bus1xPsdmmc-bus4@xPPPPspdifspdif-txxOêDspi0spi0-clkxPêspi0-cs0xPêspi0-cs1xPspi0-txxPêspi0-rxxPêspi1spi1-clkxPêspi1-cs0xPêspi1-cs1xPspi1-rxxPêspi1-txxPêspi2spi2-clkx Pêspi2-cs0x Pêspi2-rxx Pêspi2-txx Pêtsadcotp-pinxOê%otp-outxOê&uart0uart0-xfer xPOuart0-ctsxOuart0-rtsxOuart1uart1-xfer xPOuart1-ctsxOuart1-rtsxOuart2uart2-xfer xPOê4uart3uart3-xfer xPOuart3-ctsxOuart3-rtsxOuart4uart4-xfer xPOuart4-ctsxOuart4-rtsxOirir-intxOêSkeyspwr-keyxOêTpmicpmic-sleepxOê-pmic-intxPê,chosen†serial2:115200n8memory@0½memoryÉ€gmac-clk fixed-clocksY@ -ext_gmac@ê)ir-receivergpio-ir-receiver ’RÏdefaultÝSgpio-keys gpio-keysÏdefaultÝTkey-power ’. ˜GPIO Poweržt©gpio-leds gpio-ledsled-0 ’U˜geekbox:blue:led·onled-1 ’U˜geekbox:red:led·offregulator-vcc-sysregulator-fixedÃvcc_sys“LK@«LK@m�ê/ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0cpudevice_typeregenable-method#cooling-cellsphandleportsstatusinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesbus-widthcap-mmc-highspeednon-removablevmmc-supplyvqmmc-supplypinctrl-namespinctrl-0#io-channel-cellsreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outassigned-clocksassigned-clock-parentstx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizesystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetassigned-clock-ratesiommusremote-endpointphysphy-names#phy-cellsinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathgpioslabellinux,codewakeup-sourcedefault-state