Ð þí•g8ŠÄ( £ŠŒ&firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly ROC-RK3328-CCaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000�/ethernet@ff540000‹/mmc@ff500000�/mmc@ff520000cpus+cpu@0•cpuarm,cortex-a53¡¥¬»Ëxåpsció€@&3€@@R€_p{ cpu@1•cpuarm,cortex-a53¡¥¬»Ëxåpsció€@&3€@@R€_p{ cpu@2•cpuarm,cortex-a53¡¥¬»Ëxåpsció€@&3€@@R€_p{ cpu@3•cpuarm,cortex-a53¡¥¬»Ëxåpsció€@&3€@@R€_p{ idle-statesƒpscicpu-sleeparm,idle-state�¡¸xÉúÙ„{l2-cachecacheêö @({opp-table-0operating-points-v2{opp-408000000Q–~ð$œ@5opp-600000000#ÃF~ð$œ@opp-8160000000£,B@$œ@opp-1008000000<ÜÈà$œ@opp-1200000000G†Œ±($œ@opp-1296000000M?dÖ $œ@analog-soundsimple-audio-cardAi2sZtAnalog‹okaysimple-audio-card,cpu’simple-audio-card,codec’arm-pmuarm,cortex-a53-pmu0œdefg§ display-subsystemrockchip,display-subsystemº hdmi-soundsimple-audio-cardAi2sZ€tHDMI‹okaysimple-audio-card,cpu’simple-audio-card,codec’psciarm,psci-1.0arm,psci-0.2ìsmctimerarm,armv8-timer0œ   xin24m fixed-clockÀÍn6Ýxin24m{Hi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s¡ÿ œ¥)7ði2s_clki2s_hclkü  txrx ‹okay{i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s¡ÿ œ¥*8ði2s_clki2s_hclkütxrx ‹okay{i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s¡ÿ œ¥+9ði2s_clki2s_hclkütxrx  ‹disabledspdif@ff030000rockchip,rk3328-spdif¡ÿ œ¥.: ðmclkhclkü txdefault*  ‹disabledpdm@ff040000 rockchip,pdm¡ÿ¥=Rðpdm_clkpdm_hclkürxdefaultsleep*4 ‹disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd¡ÿ{Fio-domains"rockchip,rk3328-io-voltage-domain‹okay>LZhv„’gpiorockchip,rk3328-grf-gpioŸ¯{hpower-controller!rockchip,rk3328-power-controller»+{<power-domain@1¡¥‡»power-domain@6¡¥D»power-domain@5¡ ¥‹BAB»power-domain@8¡¥�F»reboot-modesyscon-reboot-modeÏÈÖRBÃâRBÃðRBà RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart¡ÿ œ7¥&Òðbaudclkapb_pclkütxrxdefault * !"  ‹disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart¡ÿ œ8¥'Óðbaudclkapb_pclkütxrxdefault *#$%  ‹disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart¡ÿ œ9¥(Ôðbaudclkapb_pclkütxrxdefault*& ‹okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c¡ÿ œ$+¥7Í ði2cpclkdefault*' ‹disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c¡ÿ œ%+¥8Î ði2cpclkdefault*(‹okaypmic@18rockchip,rk805¡ÀÝxin32krk805-clkout2Ÿ¯default*)#;I*U*a*m*y… +œ{mregulatorsDCDC_REG1 ‘vdd_logic  ß4¸ Ðä{=regulator-state-memöB@DCDC_REG2‘vdd_arm  ß4¸ Ðä{regulator-state-memö~ðDCDC_REG3‘vcc_ddrÐäregulator-state-memöDCDC_REG4‘vcc_io 2Z ¸2Z Ðä{regulator-state-memö2Z LDO_REG1‘vcc_18 w@¸w@Ðä{regulator-state-memöw@LDO_REG2 ‘vcc18_emmc w@¸w@Ðä{regulator-state-memöw@LDO_REG3‘vdd_10 B@¸B@Ðäregulator-state-memöB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c¡ÿ œ&+¥9Ï ði2cpclkdefault*, ‹disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c¡ÿ œ'+¥:Ð ði2cpclkdefault*- ‹disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi¡ÿ œ1+¥ Ñðspiclkapb_pclkü txrxdefault*./01 ‹disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt¡ÿ œ(¥ìpwm@ff1b0000rockchip,rk3328-pwm¡ÿ¥<Ö ðpwmpclkdefault*2* ‹disabledpwm@ff1b0010rockchip,rk3328-pwm¡ÿ¥<Ö ðpwmpclkdefault*3* ‹disabledpwm@ff1b0020rockchip,rk3328-pwm¡ÿ ¥<Ö ðpwmpclkdefault*4* ‹disabledpwm@ff1b0030rockchip,rk3328-pwm¡ÿ0¥<Ö ðpwmpclkdefault*5* ‹disableddma-controller@ff1f0000arm,pl330arm,primecell¡ÿ@œ5¥† ðapb_pclkL{thermal-zonessoc-thermalWmè{è�6tripstrip-point0�p©Ðœpassivetrip-point1�L©Ðœpassive{7soc-crit�s©Ð œcriticalcooling-mapsmap0´70¹ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÈmap1´7 ¹8ÿÿÿÿÿÿÿÿÈtsadc@ff250000rockchip,rk3328-tsadc¡ÿ% œ:Õ$åÃP¥$Õðtsadcapb_pclkinitdefaultsleep*94:ú9B  tsadc-apb† .‹okay{6efuse@ff260000rockchip,rk3328-efuse¡ÿ&P+¥> ðpclk_efuseD id@7¡cpu-leakage@17¡logic-leakage@19¡cpu-version@1a¡X{Iadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc¡ÿ( œP]¥%êðsaradcapb_pclkV  saradc-apb ‹disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450¡ÿ0TœZW]XY[\"ogpgpmmupppp0ppmmu0pp1ppmmu1¥‡‡ ðbuscoreó;<f¬�={8opp-table-gpuoperating-points-v2{;opp-200000000 ëÂg8opp-300000000á£g8opp-400000000ׄg8opp-500000000ÍeŒ0 ‹disablediommu@ff330200rockchip,iommu¡ÿ3 œ`¥“Ý ðaclkiface™ ‹disablediommu@ff340800rockchip,iommu¡ÿ4@ œb¥�F ðaclkiface™ ‹disabledvideo-codec@ff350000rockchip,rk3328-vpu¡ÿ5 œ ovdpu¥�F ðaclkhclk¦><iommu@ff350800rockchip,iommu¡ÿ5@ œ ¥�F ðaclkiface™<{>video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec¡ÿ6€ œ ¥‹BABðaxiahbcabaccoreÕ‹AB åׄׄᣦ?<iommu@ff360480rockchip,iommu ¡ÿ6€@ÿ6À@ œJ¥‹B ðaclkiface™<{?vop@ff370000rockchip,rk3328-vop¡ÿ7>ü œ ¥‘x;ðaclk_vopdclk_vophclk_vop…†‡  axiahbdclk¦@‹okayport{ endpoint­A{Giommu@ff373f00rockchip,iommu¡ÿ7? œ ¥‘; ðaclkiface™‹okay{@hdmi@ff3c0000rockchip,rk3328-dw-hdmi¡ÿ<  œ#¥çFðiahbisfrcec½BÂhdmidefault *CDEÌF ‹okay{ports+port@0¡endpoint­G{Aport@1¡codec@ff410000rockchip,rk3328-codec¡ÿA¥ë* ðpclkmclkÌF ‹okay{phy@ff430000rockchip,rk3328-hdmi-phy¡ÿC œS¥äHyðsysclkrefoclkrefpclk Ýhdmi_phyÀÙI åcpu-versionö‹okay{Bclock-controller@ff440000rockchip,rk3328-cru¡ÿD¥Hðxin24mÌFÀøÕx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$zHHH|å©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€{syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd¡ÿE+usb2phy@100rockchip,rk3328-usb2phy¡¥Hðphyclk Ýusb480m_phyÀÕ{J‹okay{Jotg-portö$œ;<=ootg-bvalidotg-idlinestate‹okay{Yhost-portö œ> olinestate‹okay{Zmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¡ÿP@ œ  ¥=!JNðbiuciuciu-driveciu-sample%0ðÑ€m reset‹okay>HZkdefault*KLMNvƒ��«O·mmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¡ÿQ@ œ  ¥>"KOðbiuciuciu-driveciu-sample%0ðÑ€n reset ‹disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¡ÿR@ œ ¥?#LPðbiuciuciu-driveciu-sample%0ðÑ€o reset‹okay>HÄÑàdefault *PQR«·ethernet@ff540000rockchip,rk3328-gmac¡ÿT œomacirq8¥dWXZY–ßMðstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc  stmmacethÌFîü ‹okayÕdfSSinput"T-rgmiidefault*U6 ?+O e'ÃPz…$Žethernet@ff550000rockchip,rk3328-gmac¡ÿUÌF œomacirq8¥TSSU•ÞVIðstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb  stmmaceth-rmii—Vîü output ‹disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22¡¥Vddefault*WX¢{Vusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2¡ÿX œ¥Mðotg´host¼ÎÝ€€@ ½Y Âusb2-phy‹okayusb@ff5c0000 generic-ehci¡ÿ\ œ ¥NJ½ZÂusb‹okayusb@ff5d0000 generic-ohci¡ÿ] œ ¥NJ½ZÂusb‹okaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¡ÿ_@ œ ¥@MQðbiuciuciu-driveciu-sample%0ðÑ€h reset ‹disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3¡ÿ` œC¥`a„ðref_clksuspend_clkbus_clk´host ìutmi_wideõ  . P q Š‹okayinterrupt-controller@ff811000 arm,gic-400 £ ´@¡ÿ�ÿ� ÿ�@ ÿ�`  œ {crypto@ff060000rockchip,rk3328-crypto¡ÿ@ œ¥PQ;ðhclk_masterhclk_slavesclkD  crypto-rstpinctrlrockchip,rk3328-pinctrlÌF+ Égpio@ff210000rockchip,gpio-bank¡ÿ! œ3¥ÈŸ¯ ´ £{fgpio@ff220000rockchip,gpio-bank¡ÿ" œ4¥ÉŸ¯ ´ £{+gpio@ff230000rockchip,gpio-bank¡ÿ# œ5¥ÊŸ¯ ´ £{kgpio@ff240000rockchip,gpio-bank¡ÿ$ œ6¥ËŸ¯ ´ £pcfg-pull-up Ð{]pcfg-pull-down Ý{epcfg-pull-none ì{[pcfg-pull-none-2ma ì ù{dpcfg-pull-up-2ma Ð ùpcfg-pull-up-4ma Ð ù{^pcfg-pull-none-4ma ì ù{apcfg-pull-down-4ma Ý ùpcfg-pull-none-8ma ì ù{_pcfg-pull-up-8ma Ð ù{`pcfg-pull-none-12ma ì ù {bpcfg-pull-up-12ma Ð ù {cpcfg-output-high pcfg-output-low pcfg-input-high Ð {\pcfg-input i2c0i2c0-xfer ,[[{'i2c1i2c1-xfer ,[[{(i2c2i2c2-xfer , [[{,i2c3i2c3-xfer ,[[{-i2c3-pins ,[[hdmi_i2chdmii2c-xfer ,[[{Dpdm-0pdmm0-clk ,[{pdmm0-fsync ,[pdmm0-sdi0 ,[{pdmm0-sdi1 ,[{pdmm0-sdi2 ,[{pdmm0-sdi3 ,[{pdmm0-clk-sleep ,\{pdmm0-sdi0-sleep ,\{pdmm0-sdi1-sleep ,\{pdmm0-sdi2-sleep ,\{pdmm0-sdi3-sleep ,\{pdmm0-fsync-sleep ,\tsadcotp-pin , [{9otp-out , [{:uart0uart0-xfer , []{ uart0-cts , [{!uart0-rts , [{"uart0-rts-pin , [uart1uart1-xfer ,[]{#uart1-cts ,[{$uart1-rts ,[{%uart1-rts-pin ,[uart2-0uart2m0-xfer ,[]uart2-1uart2m1-xfer ,[]{&spi0-0spi0m0-clk ,]spi0m0-cs0 , ]spi0m0-tx , ]spi0m0-rx , ]spi0m0-cs1 , ]spi0-1spi0m1-clk ,]spi0m1-cs0 ,]spi0m1-tx ,]spi0m1-rx ,]spi0m1-cs1 ,]spi0-2spi0m2-clk ,]{.spi0m2-cs0 ,]{1spi0m2-tx ,]{/spi0m2-rx ,]{0i2s1i2s1-mclk ,[i2s1-sclk ,[i2s1-lrckrx ,[i2s1-lrcktx ,[i2s1-sdi ,[i2s1-sdo ,[i2s1-sdio1 ,[i2s1-sdio2 ,[i2s1-sdio3 ,[i2s1-sleep� ,\\\\\\\\\i2s2-0i2s2m0-mclk ,[i2s2m0-sclk ,[i2s2m0-lrckrx ,[i2s2m0-lrcktx ,[i2s2m0-sdi ,[i2s2m0-sdo ,[i2s2m0-sleep` ,\\\\\\i2s2-1i2s2m1-mclk ,[i2s2m1-sclk ,[i2sm1-lrckrx ,[i2s2m1-lrcktx ,[i2s2m1-sdi ,[i2s2m1-sdo ,[i2s2m1-sleepP ,\\\\\spdif-0spdifm0-tx ,[spdif-1spdifm1-tx ,[spdif-2spdifm2-tx ,[{sdmmc0-0sdmmc0m0-pwren ,^sdmmc0m0-pin ,^sdmmc0-1sdmmc0m1-pwren ,^sdmmc0m1-pin ,^{gsdmmc0sdmmc0-clk ,_{Ksdmmc0-cmd ,`{Lsdmmc0-dectn ,^{Msdmmc0-wrprt ,^sdmmc0-bus1 ,`sdmmc0-bus4@ ,````{Nsdmmc0-pins€ ,^^^^^^^^sdmmc0extsdmmc0ext-clk ,asdmmc0ext-cmd ,^sdmmc0ext-wrprt ,^sdmmc0ext-dectn ,^sdmmc0ext-bus1 ,^sdmmc0ext-bus4@ ,^^^^sdmmc0ext-pins€ ,^^^^^^^^sdmmc1sdmmc1-clk , _sdmmc1-cmd , `sdmmc1-pwren ,`sdmmc1-wrprt ,`sdmmc1-dectn ,`sdmmc1-bus1 ,`sdmmc1-bus4@ ,````sdmmc1-pins� , ^ ^^^^^^^^emmcemmc-clk ,b{Pemmc-cmd ,c{Qemmc-pwren ,[emmc-rstnout ,[emmc-bus1 ,cemmc-bus4@ ,ccccemmc-bus8€ ,cccccccc{Rpwm0pwm0-pin ,[{2pwm1pwm1-pin ,[{3pwm2pwm2-pin ,[{4pwmirpwmir-pin ,[{5gmac-1rgmiim1-pins` , _ aa_aaa a a_ _aa___ _a____{Urmiim1-pins ,dbdddd d db b [ [[[[[gmac2phyfephyled-speed10 ,[fephyled-duplex ,[fephyled-rxm1 ,[{Wfephyled-txm1 ,[fephyled-linkm1 ,[{Xtsadc_pintsadc-int , [tsadc-pin , [hdmi_pinhdmi-cec ,[{Chdmi-hpd ,e{Ecif-0dvp-d2d9-m0À ,[[[[[ [ [ [[[[[cif-1dvp-d2d9-m1À ,[[[[[[[[[[[[irir-int ,[{lpmicpmic-int-l ,]{)usb2usb20-host-drv ,[{ichosen :serial2:1500000n8external-gmac-clock fixed-clockÍsY@ Ýgmac_clkinÀ{Sregulator-dc-12vregulator-fixed‘dc_12vÐä ·¸·{jregulator-sdmmcregulator-fixed Jfdefault*gä‘vcc_sd 2Z ¸2Z  F{Oregulator-sdmmcioregulator-gpioÄw@2Z  ‘vcc_sdio Qvoltage w@¸2Z Ð F* `h{regulator-vcc-host1-5vregulator-fixed fdefault*i ‘vcc_host1_5vÐ F* J+regulator-vcc-sysregulator-fixed‘vcc_sysÐä LK@¸LK@ Fj{*regulator-vcc-phyregulator-fixed‘vcc_phyÐä{Tir-receivergpio-ir-receiver `k*ldefaultleds gpio-ledsled-0 yfirefly:blue:power heartbeat `m •onled-1 yfirefly:yellow:user mmc1 `m •off compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domainsmali-supply#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplyregulator-typegpiosenable-active-highlabellinux,default-triggerdefault-state