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�disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450¦ÿ0T¡ZW]XY[\"»gpgpmmupppp0ppmmu0pp1ppmmu1ª‡‡ õbuscoreø;Ë<f±€8opp-table-gpuoperating-points-v2€;opp-200000000 ëÂg8opp-300000000á£g8opp-400000000ׄg8opp-500000000ÍeŒ0 �disablediommu@ff330200rockchip,iommu¦ÿ3 ¡`ª“Ý õaclkifaceÙ �disablediommu@ff340800rockchip,iommu¦ÿ4@ ¡bª�F õaclkifaceÙ �disabledvideo-codec@ff350000rockchip,rk3328-vpu¦ÿ5 ¡ »vdpuª�F õaclkhclkæ=Ë<iommu@ff350800rockchip,iommu¦ÿ5@ ¡ ª�F õaclkifaceÙË<€=video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec¦ÿ6€ ¡ ª‹BABõaxiahbcabaccoreï‹AB ÿׄׄá£æ>Ë<iommu@ff360480rockchip,iommu ¦ÿ6€@ÿ6À@ ¡Jª‹B õaclkifaceÙË<€>vop@ff370000rockchip,rk3328-vop¦ÿ7>ü ¡ ª‘x;õaclk_vopdclk_vophclk_vop…†‡ %axiahbdclkæ? �disabledport€ endpointí@€Fiommu@ff373f00rockchip,iommu¦ÿ7? ¡ ª‘; õaclkifaceÙ �disabled€?hdmi@ff3c0000rockchip,rk3328-dw-hdmi¦ÿ< ¡#ªçFõiahbisfrcecýAhdmi!default /BCD E �disabled€ports+port@0¦endpointíF€@port@1¦codec@ff410000rockchip,rk3328-codec¦ÿAªë* õpclkmclk E �disabled€phy@ff430000rockchip,rk3328-hdmi-phy¦ÿC ¡SªäGyõsysclkrefoclkrefpclk âhdmi_phyÅH %cpu-version6 �disabled€Aclock-controller@ff440000rockchip,rk3328-cru¦ÿDªGõxin24m EÅAøïx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$NzGGG|ÿ©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd¦ÿE+usb2phy@100rockchip,rk3328-usb2phy¦ªGõphyclk âusb480m_phyÅï{NI�okay€Iotg-port6$¡;<=»otg-bvalidotg-idlinestate�okay€Vhost-port6 ¡> »linestate�okay€Wmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿP@ ¡  ª=!JNõbiuciuciu-driveciu-sampleepðÑ€m%reset�okay~ˆ™/JKLM!default¤±¾ËÙNåmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿQ@ ¡  ª>"KOõbiuciuciu-driveciu-sampleepðÑ€n%reset �disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿR@ ¡ ª?#LPõbiuciuciu-driveciu-sampleepðÑ€o%reset �disabledethernet@ff540000rockchip,rk3328-gmac¦ÿT ¡»macirq8ªdWXZY–ßMõstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc 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XZuart2-1uart2m1-xfer XZ€&spi0-0spi0m0-clk Zspi0m0-cs0  Zspi0m0-tx  Zspi0m0-rx  Zspi0m0-cs1  Zspi0-1spi0m1-clk Zspi0m1-cs0 Zspi0m1-tx Zspi0m1-rx Zspi0m1-cs1 Zspi0-2spi0m2-clk Z€.spi0m2-cs0 Z€1spi0m2-tx Z€/spi0m2-rx Z€0i2s1i2s1-mclk Xi2s1-sclk Xi2s1-lrckrx Xi2s1-lrcktx Xi2s1-sdi Xi2s1-sdo Xi2s1-sdio1 Xi2s1-sdio2 Xi2s1-sdio3 Xi2s1-sleep� YYYYYYYYYi2s2-0i2s2m0-mclk Xi2s2m0-sclk Xi2s2m0-lrckrx Xi2s2m0-lrcktx Xi2s2m0-sdi Xi2s2m0-sdo Xi2s2m0-sleep` YYYYYYi2s2-1i2s2m1-mclk Xi2s2m1-sclk Xi2sm1-lrckrx Xi2s2m1-lrcktx Xi2s2m1-sdi Xi2s2m1-sdo Xi2s2m1-sleepP YYYYYspdif-0spdifm0-tx Xspdif-1spdifm1-tx Xspdif-2spdifm2-tx X€sdmmc0-0sdmmc0m0-pwren [sdmmc0m0-pin [sdmmc0-1sdmmc0m1-pwren [sdmmc0m1-pin [€jsdmmc0sdmmc0-clk \€Jsdmmc0-cmd ]€Ksdmmc0-dectn [€Lsdmmc0-wrprt [sdmmc0-bus1 ]sdmmc0-bus4@ ]]]]€Msdmmc0-pins€ [[[[[[[[sdmmc0extsdmmc0ext-clk ^sdmmc0ext-cmd [sdmmc0ext-wrprt [sdmmc0ext-dectn [sdmmc0ext-bus1 [sdmmc0ext-bus4@ [[[[sdmmc0ext-pins€ [[[[[[[[sdmmc1sdmmc1-clk  \sdmmc1-cmd  ]sdmmc1-pwren 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–vcc_io_sdio¥Ëw@ã2Z  mˆ ˆvoltage —ÐÉw@2Z  ¨€regulator-sdmmcregulator-fixed ³d/j!default–vcc_sd¹Ë2Z ã2Z  ¨€Nregulator-vdd-5vregulator-fixed–vdd_5v¥¹ËLK@ãLK@€+regulator-vdd-5v-lanregulator-fixed Z ³h/k!default –vdd_5v_lan¥¹ ¨+ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domains#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplytx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-modephy-supplyphy-handletx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio