Ð þí˜é8�˜( Q�`,friendlyarm,nanopi-r2c-plusrockchip,rk3328 +7FriendlyElec NanoPi R2C Plusaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000�/ethernet@ff540000‹/usb@ff600000/device@2•/mmc@ff500000š/mmc@ff520000cpus+cpu@0Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… cpu@1Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… cpu@2Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… cpu@3Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… idle-states�pscicpu-sleeparm,idle-stateš«ÂxÓúã„…l2-cachecacheô @2…opp-table-0operating-points-v2…opp-408000000Q– ~ð.œ@?opp-600000000#ÃF ~ð.œ@opp-8160000000£, B@.œ@opp-1008000000<Ü Èà.œ@opp-1200000000G†Œ ±(.œ@opp-1296000000M?d Ö .œ@analog-soundsimple-audio-cardKi2sd~Analog •disabledsimple-audio-card,cpuœsimple-audio-card,codecœarm-pmuarm,cortex-a53-pmu0¦defg± display-subsystemrockchip,display-subsystemÄ  •disabledhdmi-soundsimple-audio-cardKi2sd€~HDMI •disabledsimple-audio-card,cpuœsimple-audio-card,codecœpsciarm,psci-1.0arm,psci-0.2ösmctimerarm,armv8-timer0¦   xin24m fixed-clockÊ×n6çxin24m…Gi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s«ÿ ¦¯)7úi2s_clki2s_hclk   txrx •disabled…i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s«ÿ ¦¯*8úi2s_clki2s_hclk txrx •disabled…i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s«ÿ ¦¯+9úi2s_clki2s_hclk txrx •disabledspdif@ff030000rockchip,rk3328-spdif«ÿ ¦¯.: úmclkhclk  tx&default4 •disabledpdm@ff040000 rockchip,pdm«ÿ¯=Rúpdm_clkpdm_hclk rx&defaultsleep4> •disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd«ÿ…Eio-domains"rockchip,rk3328-io-voltage-domain•okayHUcq�›gpiorockchip,rk3328-grf-gpio©¹power-controller!rockchip,rk3328-power-controllerÅ+…<power-domain@1«¯‡Åpower-domain@6«¯DÅpower-domain@5« ¯‹BABÅpower-domain@8«¯�FÅreboot-modesyscon-reboot-modeÙÈàRBÃìRBÃúRBà  RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart«ÿ ¦7¯&Òúbaudclkapb_pclk txrx&default 4 !"# •disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart«ÿ ¦8¯'Óúbaudclkapb_pclk txrx&default 4#$%# •disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart«ÿ ¦9¯(Ôúbaudclkapb_pclk txrx&default4&#•okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦$+¯7Í úi2cpclk&default4' •disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦%+¯8Î úi2cpclk&default4(•okaypmic@18rockchip,rk805« )¦Êçxin32krk805-clkout2©¹4*&default-ES+_+k+w+ƒ�+regulatorsDCDC_REG1›vdd_logª¾Ð ß4è 0Ôregulator-state-mem-B@DCDC_REG2›vdd_armª¾Ð ß4è 0Ô…regulator-state-mem-~ðDCDC_REG3›vcc_ddrª¾regulator-state-memDCDC_REG4 ›vcc_io_33ª¾Ð2Z è2Z …regulator-state-mem-2Z LDO_REG1›vcc_18ª¾Ðw@èw@…regulator-state-mem-w@LDO_REG2 ›vcc18_emmcª¾Ðw@èw@…regulator-state-mem-w@LDO_REG3›vdd_10ª¾ÐB@èB@regulator-state-mem-B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦&+¯9Ï úi2cpclk&default4, •disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦'+¯:Ð úi2cpclk&default4- •disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi«ÿ ¦1+¯ Ñúspiclkapb_pclk  txrx&default4./01 •disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt«ÿ ¦(¯ìpwm@ff1b0000rockchip,rk3328-pwm«ÿ¯<Ö úpwmpclk&default42I •disabledpwm@ff1b0010rockchip,rk3328-pwm«ÿ¯<Ö úpwmpclk&default43I •disabledpwm@ff1b0020rockchip,rk3328-pwm«ÿ ¯<Ö úpwmpclk&default44I•okaypwm@ff1b0030rockchip,rk3328-pwm«ÿ0¯<Ö úpwmpclk&default45I •disableddma-controller@ff1f0000arm,pl330arm,primecell«ÿ@¦T¯† úapb_pclkk…thermal-zonessoc-thermalvŒèšè¬6tripstrip-point0¼pÈЦpassivetrip-point1¼LÈЦpassive…7soc-crit¼sÈÐ ¦criticalcooling-mapsmap0Ó70Ø ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿçmap1Ó7 Ø8ÿÿÿÿÿÿÿÿçtsadc@ff250000rockchip,rk3328-tsadc«ÿ% ¦:ô$ÃP¯$Õútsadcapb_pclk&initdefaultsleep49>:9#B *tsadc-apb6† M•okaycz…6efuse@ff260000rockchip,rk3328-efuse«ÿ&P+¯> úpclk_efuse• id@7«cpu-leakage@17«logic-leakage@19«cpu-version@1a«©…Hadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc«ÿ( ¦P®¯%êúsaradcapb_pclk#V *saradc-apb •disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450«ÿ0T¦ZW]XY[\"Àgpgpmmupppp0ppmmu0pp1ppmmu1¯‡‡ úbuscoreý;Ð<#f¶…8opp-table-gpuoperating-points-v2…;opp-200000000 ë g8opp-300000000ᣠg8opp-400000000ׄ g8opp-500000000Íe Œ0 •disablediommu@ff330200rockchip,iommu«ÿ3 ¦`¯“Ý úaclkifaceÞ •disablediommu@ff340800rockchip,iommu«ÿ4@ ¦b¯�F úaclkifaceÞ •disabledvideo-codec@ff350000rockchip,rk3328-vpu«ÿ5 ¦ Àvdpu¯�F úaclkhclkë=Ð<iommu@ff350800rockchip,iommu«ÿ5@ ¦ ¯�F úaclkifaceÞÐ<…=video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec«ÿ6€ ¦ ¯‹BABúaxiahbcabaccoreô‹AB ׄׄá£ë>Ð<iommu@ff360480rockchip,iommu «ÿ6€@ÿ6À@ ¦J¯‹B úaclkifaceÞÐ<…>vop@ff370000rockchip,rk3328-vop«ÿ7>ü ¦ ¯‘x;úaclk_vopdclk_vophclk_vop#…†‡ *axiahbdclkë? •disabledport… endpointò@…Fiommu@ff373f00rockchip,iommu«ÿ7? ¦ ¯‘; úaclkifaceÞ •disabled…?hdmi@ff3c0000rockchip,rk3328-dw-hdmi«ÿ< ¦#¯çFúiahbisfrcecAhdmi&default 4BCDE •disabled…ports+port@0«endpointòF…@port@1«codec@ff410000rockchip,rk3328-codec«ÿA¯ë* úpclkmclkE •disabled…phy@ff430000rockchip,rk3328-hdmi-phy«ÿC ¦S¯äGyúsysclkrefoclkrefpclk çhdmi_phyÊH *cpu-version; •disabled…Aclock-controller@ff440000rockchip,rk3328-cru«ÿD¯Gúxin24mEÊFøôx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$SzGGG|©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€…syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd«ÿE+usb2phy@100rockchip,rk3328-usb2phy«¯Gúphyclk çusb480m_phyÊô{SI•okay…Iotg-port;$¦;<=Àotg-bvalidotg-idlinestate•okay…Yhost-port; ¦> Àlinestate•okay…Zmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿP@ ¦  ¯=!JNúbiuciuciu-driveciu-samplejuðÑ€#m*reset•okayƒ�ž4JKLM&default©¶ÃÐÞNêmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿQ@ ¦  ¯>"KOúbiuciuciu-driveciu-samplejuðÑ€#n*reset •disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿR@ ¦ ¯?#LPúbiuciuciu-driveciu-samplejuðÑ€#o*reset•okayƒ÷ %&default 4OPQÞêethernet@ff540000rockchip,rk3328-gmac«ÿT ¦Àmacirq8¯dWXZY–ßMústmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac#c *stmmacethE3AO•okayôdfSRRZinputgrgmiip4S&default{T†"�mdiosnps,dwmac-mdio+ethernet-phy@3ethernet-phy-ieee802.3-c22«˜sY@·Ò4U&defaultð' ÃP )…Tethernet@ff550000rockchip,rk3328-gmac«ÿUE ¦Àmacirq8¯TSSU•ÞVIústmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy#b *stmmacethgrmii{V3AOZoutput •disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22«¯V#d&default4WX …Vusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2«ÿX ¦¯Múotg 0host 8 J Y€€@ Y usb2-phy•okayusb@ff5c0000 generic-ehci«ÿ\ ¦ ¯NIZusb•okayusb@ff5d0000 generic-ohci«ÿ] ¦ ¯NIZusb•okaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿ_@ ¦ ¯@MQúbiuciuciu-driveciu-samplejuðÑ€#h*reset •disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3«ÿ` ¦C¯`a„úref_clksuspend_clkbus_clk 0host hutmi_wide q ’ ª Ì í •okay+device@2 usbbda,8153«interrupt-controller@ff811000 arm,gic-400  0@«ÿ�ÿ� ÿ�@ ÿ�`  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[…:uart0uart0-xfer ¨ []… uart0-cts ¨ […!uart0-rts ¨ […"uart0-rts-pin ¨ [uart1uart1-xfer ¨[]…#uart1-cts ¨[…$uart1-rts ¨[…%uart1-rts-pin ¨[uart2-0uart2m0-xfer ¨[]uart2-1uart2m1-xfer ¨[]…&spi0-0spi0m0-clk ¨]spi0m0-cs0 ¨ ]spi0m0-tx ¨ ]spi0m0-rx ¨ ]spi0m0-cs1 ¨ ]spi0-1spi0m1-clk ¨]spi0m1-cs0 ¨]spi0m1-tx ¨]spi0m1-rx ¨]spi0m1-cs1 ¨]spi0-2spi0m2-clk ¨]….spi0m2-cs0 ¨]…1spi0m2-tx ¨]…/spi0m2-rx ¨]…0i2s1i2s1-mclk ¨[i2s1-sclk ¨[i2s1-lrckrx ¨[i2s1-lrcktx ¨[i2s1-sdi ¨[i2s1-sdo ¨[i2s1-sdio1 ¨[i2s1-sdio2 ¨[i2s1-sdio3 ¨[i2s1-sleep� ¨\\\\\\\\\i2s2-0i2s2m0-mclk ¨[i2s2m0-sclk ¨[i2s2m0-lrckrx ¨[i2s2m0-lrcktx ¨[i2s2m0-sdi ¨[i2s2m0-sdo ¨[i2s2m0-sleep` ¨\\\\\\i2s2-1i2s2m1-mclk ¨[i2s2m1-sclk ¨[i2sm1-lrckrx ¨[i2s2m1-lrcktx ¨[i2s2m1-sdi ¨[i2s2m1-sdo ¨[i2s2m1-sleepP ¨\\\\\spdif-0spdifm0-tx ¨[spdif-1spdifm1-tx ¨[spdif-2spdifm2-tx ¨[…sdmmc0-0sdmmc0m0-pwren ¨^sdmmc0m0-pin ¨^sdmmc0-1sdmmc0m1-pwren ¨^sdmmc0m1-pin ¨^…msdmmc0sdmmc0-clk ¨_…Jsdmmc0-cmd ¨`…Ksdmmc0-dectn ¨^…Lsdmmc0-wrprt ¨^sdmmc0-bus1 ¨`sdmmc0-bus4@ ¨````…Msdmmc0-pins€ ¨^^^^^^^^sdmmc0extsdmmc0ext-clk ¨asdmmc0ext-cmd ¨^sdmmc0ext-wrprt ¨^sdmmc0ext-dectn ¨^sdmmc0ext-bus1 ¨^sdmmc0ext-bus4@ ¨^^^^sdmmc0ext-pins€ ¨^^^^^^^^sdmmc1sdmmc1-clk ¨ _sdmmc1-cmd ¨ `sdmmc1-pwren ¨`sdmmc1-wrprt ¨`sdmmc1-dectn ¨`sdmmc1-bus1 ¨`sdmmc1-bus4@ ¨````sdmmc1-pins� ¨ ^ ^^^^^^^^emmcemmc-clk ¨b…Oemmc-cmd ¨c…Pemmc-pwren ¨[emmc-rstnout ¨[emmc-bus1 ¨cemmc-bus4@ ¨ccccemmc-bus8€ ¨cccccccc…Qpwm0pwm0-pin ¨[…2pwm1pwm1-pin ¨[…3pwm2pwm2-pin ¨[…4pwmirpwmir-pin ¨[…5gmac-1rgmiim1-pins` ¨ _ aa_aaa a a_ _aa___ _a____…Srmiim1-pins ¨dbdddd d db b [ [[[[[gmac2phyfephyled-speed10 ¨[fephyled-duplex ¨[fephyled-rxm1 ¨[…Wfephyled-txm1 ¨[fephyled-linkm1 ¨[…Xtsadc_pintsadc-int ¨ [tsadc-pin ¨ [hdmi_pinhdmi-cec ¨[…Bhdmi-hpd ¨e…Dcif-0dvp-d2d9-m0À ¨[[[[[ [ [ [[[[[cif-1dvp-d2d9-m1À ¨[[[[[[[[[[[[buttonreset-button-pin ¨[…fgmac2ioeth-phy-reset-pin ¨e…Uledslan-led-pin ¨[…hsys-led-pin ¨[…iwan-led-pin ¨[…jlanlan-vdd-pin ¨[…npmicpmic-int-l ¨]…*sdsdio-vcc-pin ¨]…lchosen ¶serial2:1500000n8gmac-clock fixed-clock×sY@ çgmac_clkinÊ…Rkeys gpio-keys4f&defaultkey-reset Âreset g Ș Ó2leds gpio-leds 4hij&defaultled-0 k Ânanopi-r2s:green:lanled-1 g Ânanopi-r2s:red:sys åonled-2 k Ânanopi-r2s:green:wanregulator-sdmmcioregulator-gpio ó )4l&default ›vcc_io_sdioªÐw@è2Z  ˆ !voltage 0ÐÎw@2Z  A…regulator-sdmmcregulator-fixed Lg4m&default›vcc_sd¾Ð2Z è2Z  A…Nregulator-vdd-5vregulator-fixed›vdd_5vª¾ÐLK@èLK@…+regulator-vdd-5v-lanregulator-fixed ó Lk4n&default ›vdd_5v_lanª¾ A+ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domains#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-modephy-supplyphy-handletx_delayrx_delaymotorcomm,clk-out-frequency-hzmotorcomm,keep-pll-enabledmotorcomm,auto-sleep-disabledreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio