Ð þí�™8†0( i…ø$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000�/ethernet@ff550000‹/mmc@ff500000�/mmc@ff510000•/mmc@ff520000cpus+cpu@0šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ cpu@1šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ cpu@2šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ cpu@3šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ idle-statesˆpscicpu-sleeparm,idle-state•¦½xÎúÞ„€l2-cachecacheïû@-€opp-table-0operating-points-v2 €opp-408000000Q–~ð)œ@:opp-600000000#ÃF~ð)œ@opp-8160000000£,B@)œ@opp-1008000000<ÜÈà)œ@opp-1200000000G†Œ±()œ@opp-1296000000M?dÖ )œ@analog-soundsimple-audio-cardFi2s_yAnalog �disabledsimple-audio-card,cpu—simple-audio-card,codec—arm-pmuarm,cortex-a53-pmu0¡defg¬ display-subsystemrockchip,display-subsystem¿ hdmi-soundsimple-audio-cardFi2s_€yHDMI �disabledsimple-audio-card,cpu—simple-audio-card,codec—psciarm,psci-1.0arm,psci-0.2ñsmctimerarm,armv8-timer0¡   xin24m fixed-clockÅÒn6âxin24m€Di2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s¦ÿ ¡ª)7õi2s_clki2s_hclk  txrx �disabled€i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s¦ÿ ¡ª*8õi2s_clki2s_hclktxrx �disabled€i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s¦ÿ ¡ª+9õi2s_clki2s_hclktxrx �disabledspdif@ff030000rockchip,rk3328-spdif¦ÿ ¡ª.: õmclkhclk tx!default/ �disabledpdm@ff040000 rockchip,pdm¦ÿª=Rõpdm_clkpdm_hclkrx!defaultsleep/9 �disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd¦ÿ€Bio-domains"rockchip,rk3328-io-voltage-domain �disabledgpiorockchip,rk3328-grf-gpioCSpower-controller!rockchip,rk3328-power-controller_+€9power-domain@1¦ª‡_power-domain@6¦ªD_power-domain@5¦ ª‹BAB_power-domain@8¦ª�F_reboot-modesyscon-reboot-modesÈzRBÆRBÔRBà ¤RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart¦ÿ ¡7ª&Òõbaudclkapb_pclktxrx!default /°½ �disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart¦ÿ ¡8ª'Óõbaudclkapb_pclktxrx!default / !°½ �disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart¦ÿ ¡9ª(Ôõbaudclkapb_pclktxrx!default/"°½�okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡$+ª7Í õi2cpclk!default/# �disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡%+ª8Î õi2cpclk!default/$�okaypmic@18rockchip,rk805¦ %¡Åâxin32krk805-clkout2CS!default/&Çßí'ù'''()(regulatorsDCDC_REG1 5vdd_logicD ß4\ tˆregulator-state-memš²B@DCDC_REG25vdd_armD ß4\ tˆ€regulator-state-memš²~ðDCDC_REG35vcc_ddrtˆregulator-state-memšDCDC_REG45vcc_ioD2Z \2Z tˆ€(regulator-state-memš²2Z LDO_REG15vcc_18Dw@\w@tˆregulator-state-memš²w@LDO_REG2 5vcc18_emmcDw@\w@tˆregulator-state-memš²w@LDO_REG35vdd_10DB@\B@tˆregulator-state-memš²B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡&+ª9Ï õi2cpclk!default/) �disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡'+ª:Ð õi2cpclk!default/* �disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi¦ÿ ¡1+ª Ñõspiclkapb_pclk txrx!default/+,-. �disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt¦ÿ ¡(ªìpwm@ff1b0000rockchip,rk3328-pwm¦ÿª<Ö õpwmpclk!default//Î �disabledpwm@ff1b0010rockchip,rk3328-pwm¦ÿª<Ö õpwmpclk!default/0Î �disabledpwm@ff1b0020rockchip,rk3328-pwm¦ÿ ª<Ö õpwmpclk!default/1Î �disabledpwm@ff1b0030rockchip,rk3328-pwm¦ÿ0ª<Ö õpwmpclk!default/2Î �disableddma-controller@ff1f0000arm,pl330arm,primecell¦ÿ@¡Ùª† õapb_pclkð€thermal-zonessoc-thermalûèè13tripstrip-point0ApMСpassivetrip-point1ALMСpassive€4soc-critAsMÐ ¡criticalcooling-mapsmap0X40] ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlmap1X4 ]5ÿÿÿÿÿÿÿÿltsadc@ff250000rockchip,rk3328-tsadc¦ÿ% ¡:y$‰ÃPª$Õõtsadcapb_pclk!initdefaultsleep/697ž6¨B ¯tsadc-apb»† Ò�okay€3efuse@ff260000rockchip,rk3328-efuse¦ÿ&P+ª> õpclk_efuseè id@7¦cpu-leakage@17¦logic-leakage@19¦cpu-version@1a¦ü€Eadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc¦ÿ( ¡Pª%êõsaradcapb_pclk¨V ¯saradc-apb �disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450¦ÿ0T¡ZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1ª‡‡ õbuscoreø8#9¨f±€5opp-table-gpuoperating-points-v2€8opp-200000000 ëÂg8opp-300000000á£g8opp-400000000ׄg8opp-500000000ÍeŒ0 �disablediommu@ff330200rockchip,iommu¦ÿ3 ¡`ª“Ý õaclkiface1 �disablediommu@ff340800rockchip,iommu¦ÿ4@ ¡bª�F õaclkiface1 �disabledvideo-codec@ff350000rockchip,rk3328-vpu¦ÿ5 ¡ vdpuª�F õaclkhclk>:#9iommu@ff350800rockchip,iommu¦ÿ5@ ¡ ª�F õaclkiface1#9€:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec¦ÿ6€ ¡ ª‹BABõaxiahbcabaccorey‹AB ‰ׄׄá£>;#9iommu@ff360480rockchip,iommu ¦ÿ6€@ÿ6À@ ¡Jª‹B õaclkiface1#9€;vop@ff370000rockchip,rk3328-vop¦ÿ7>ü ¡ ª‘x;õaclk_vopdclk_vophclk_vop¨…†‡ ¯axiahbdclk>< �disabledport€ endpointE=€Ciommu@ff373f00rockchip,iommu¦ÿ7? ¡ ª‘; õaclkiface1 �disabled€<hdmi@ff3c0000rockchip,rk3328-dw-hdmi¦ÿ<° ¡#ªçFõiahbisfrcecU>Zhdmi!default /?@AdB �disabled€ports+port@0¦endpointEC€=port@1¦codec@ff410000rockchip,rk3328-codec¦ÿAªë* õpclkmclkdB �disabled€phy@ff430000rockchip,rk3328-hdmi-phy¦ÿC ¡SªäDyõsysclkrefoclkrefpclk âhdmi_phyÅqE }cpu-versionŽ �disabled€>clock-controller@ff440000rockchip,rk3328-cru¦ÿDªDõxin24mdBÅ™øyx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$¦zDDD|‰©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd¦ÿE+usb2phy@100rockchip,rk3328-usb2phy¦ªDõphyclk âusb480m_phyÅy{¦F�okay€Fotg-portŽ$¡;<=otg-bvalidotg-idlinestate�okay€Whost-portŽ ¡> linestate�okay€Xmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿP@ ¡  ª=!JNõbiuciuciu-driveciu-sample½ÈðÑ€¨m¯reset�okayÖàò!default/GHIJKmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿQ@ ¡  ª>"KOõbiuciuciu-driveciu-sample½ÈðÑ€¨n¯reset�okayÖò'=LH!default /MNOmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿR@ ¡ ª?#LPõbiuciuciu-driveciu-sample½ÈðÑ€¨o¯reset�okayÖàH!default /PQRethernet@ff540000rockchip,rk3328-gmac¦ÿT ¡macirq8ªdWXZY–ßMõstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac¨c ¯stmmacethdBVdr �disabledethernet@ff550000rockchip,rk3328-gmac¦ÿUdB ¡macirq8ªTSSU•ÞVIõstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy¨b ¯stmmaceth}rmii†SVdr‘output�okayžT‰úð€ye¦Tmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22¦ªV¨d!default/UV©€Susb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2¦ÿX ¡ªMõotg»otgÃÕ䀀@ UW Zusb2-phy�okayusb@ff5c0000 generic-ehci¦ÿ\ ¡ ªNFUXZusb�okayusb@ff5d0000 generic-ohci¦ÿ] ¡ ªNFUXZusb�okaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿ_@ ¡ ª@MQõbiuciuciu-driveciu-sample½ÈðÑ€¨h¯reset �disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3¦ÿ` ¡Cª`a„õref_clksuspend_clkbus_clk»otg óutmi_wideü5Wx‘ �disabledinterrupt-controller@ff811000 arm,gic-400ª»@¦ÿ�ÿ� ÿ�@ ÿ�`  ¡ €crypto@ff060000rockchip,rk3328-crypto¦ÿ@ ¡ªPQ;õhclk_masterhclk_slavesclk¨D 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3Y€!uart1-rts-pin 3Yuart2-0uart2m0-xfer 3Y[uart2-1uart2m1-xfer 3Y[€"spi0-0spi0m0-clk 3[spi0m0-cs0 3 [spi0m0-tx 3 [spi0m0-rx 3 [spi0m0-cs1 3 [spi0-1spi0m1-clk 3[spi0m1-cs0 3[spi0m1-tx 3[spi0m1-rx 3[spi0m1-cs1 3[spi0-2spi0m2-clk 3[€+spi0m2-cs0 3[€.spi0m2-tx 3[€,spi0m2-rx 3[€-i2s1i2s1-mclk 3Yi2s1-sclk 3Yi2s1-lrckrx 3Yi2s1-lrcktx 3Yi2s1-sdi 3Yi2s1-sdo 3Yi2s1-sdio1 3Yi2s1-sdio2 3Yi2s1-sdio3 3Yi2s1-sleep� 3ZZZZZZZZZi2s2-0i2s2m0-mclk 3Yi2s2m0-sclk 3Yi2s2m0-lrckrx 3Yi2s2m0-lrcktx 3Yi2s2m0-sdi 3Yi2s2m0-sdo 3Yi2s2m0-sleep` 3ZZZZZZi2s2-1i2s2m1-mclk 3Yi2s2m1-sclk 3Yi2sm1-lrckrx 3Yi2s2m1-lrcktx 3Yi2s2m1-sdi 3Yi2s2m1-sdo 3Yi2s2m1-sleepP 3ZZZZZspdif-0spdifm0-tx 3Yspdif-1spdifm1-tx 3Yspdif-2spdifm2-tx 3Y€sdmmc0-0sdmmc0m0-pwren 3\sdmmc0m0-pin 3\sdmmc0-1sdmmc0m1-pwren 3\sdmmc0m1-pin 3\€gsdmmc0sdmmc0-clk 3]€Gsdmmc0-cmd 3^€Hsdmmc0-dectn 3\€Isdmmc0-wrprt 3\sdmmc0-bus1 3^sdmmc0-bus4@ 3^^^^€Jsdmmc0-pins€ 3\\\\\\\\sdmmc0extsdmmc0ext-clk 3_sdmmc0ext-cmd 3\sdmmc0ext-wrprt 3\sdmmc0ext-dectn 3\sdmmc0ext-bus1 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^h€'regulator-vcc-phyregulator-fixed5vcc_phytˆ€T compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domains#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblphy-modephy-handleclock_in_outphy-supplyphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply