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Wdisabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2Áÿ@  BÓžÐotg ïperipheral÷ €€@ '@ ,usb2-phyWokayusb@ff440000 generic-ehciÁÿD  GÓŸ  'A,usbWokayusb@ff450000 generic-ohciÁÿE  HÓŸ  'A,usbWokaymmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcÁÿH@  L6 Óš012Ðbiuciuciu-driveciu-sample@KðÑ€÷defaultBCDEWokayYk|‡ mmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcÁÿI@  M6 Óœ:;<Ðbiuciuciu-driveciu-sample@KðÑ€WokayY™mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcÁÿJ@  N6 Ó›567Ðbiuciuciu-driveciu-sample@KðÑ€÷default FGHWokay+k§´ÊI™ÕÜwifi@1%brcm,bcm43455-fmacbrcm,bcm4329-fmacÁ J  Ühost-wake÷defaultKnand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcÁÿK@  QÓ™-Ðahbnfc©-âðÑ€LMNOPQR÷default Wdisabledethernet@ff4e0000rockchip,rk3308-gmacÁÿN  @Ümacirq@Ó@BBA@†ÃC[Ðstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed÷rmii÷defaultST¡} ¨stmmacethâ: Wdisabledspi@ff4c0000 rockchip,sfcÁÿL@  RÓ=�Ðclk_sfchclk_sfc UVW÷default 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`pwm11pwm11-pinØ\C0pwm11-pin-pull-downØ`rtcrtc-32kØ\CYsdmmcsdmmc-clkØaCBsdmmc-cmdØbCCsdmmc-detØbCDsdmmc-pwrenØasdmmc-bus1Øbsdmmc-bus4@ØbbbbCEsdiosdio-clkØZCHsdio-cmdØ[CGsdio-pwrenØZsdio-wrptØZsdio-intnØZsdio-bus1Ø[sdio-bus4@Ø[[[[CFspdif_inspdif-inØ\spdif_outspdif-outØ\C?spi0spi0-clkØbC spi0-csn0ØbC!spi0-misoØbC"spi0-mosiØbC#spi1spi1-clkØ bC$spi1-csn0Ø bC%spi1-misoØ bC&spi1-mosiØ bC'spi1-m1spi1m1-misoØbspi1m1-mosiØbspi1m1-clkØbspi1m1-csn0Ø bspi2spi2-clkØbC)spi2-csn0ØbC*spi2-misoØbC+spi2-mosiØbC,tsadctsadc-otp-pinØ \tsadc-otp-outØ \uart0uart0-xfer ØccCuart0-ctsØ\Cuart0-rtsØ\Cuart0-rts-pinØ\uart1uart1-xfer ØccCuart1-ctsØ\Cuart1-rtsØ\Cuart2-m0uart2m0-xfer ØccCuart2-m1uart2m1-xfer Øccuart3uart3-xfer Ø c cCuart3-m1uart3m1-xfer Øccuart4uart4-xfer Ø ccCuart4-ctsØ\Cuart4-rtsØ\Cuart4-rts-pinØ\bluetoothbt-reg-onØ \Cbt-wake-hostØ \Chost-wake-btØ \Csdio-pwrseqwifi-enable-hØ\Chusbotg-vbus-drvØ\Cgwifiwifi-host-wakeØ`CKchosenæserial2:1500000n8regulator-vcc5v0-sysregulator-fixed òvcc5v0_sys'LK@?LK@Ceregulator-vdd-corepwm-regulatorWdˆ òvdd_core' žx?r`\úzeCregulator-vdd-logregulator-fixedòvdd_log'�?�…eregulator-vcc-ddrregulator-fixedòvcc_ddr'ã`?ã`…eregulator-vcc-1v8regulator-fixedòvcc_1v8'w@?w@…fC9regulator-vcc-ioregulator-fixedòvcc_io'2Z ?2Z …eCfregulator-vcc-phy-regulatorregulator-fixedòvcc_phyregulator-vcc5v0-otgregulator-fixed� £J÷defaultg òvcc5v0_otg…esdio-pwrseqmmc-pwrseq-simpleh÷default ¨JCI compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsstatusoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosmax-speeddmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeeddisable-wpcard-detect-delaynon-removablecap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdassigned-clock-ratesphy-mode#reset-cells#sound-dai-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltpwmsregulator-settling-time-up-uspwm-supplyvin-supplyenable-active-highgpioreset-gpios