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¢qreboot-reason@48VH [š%gpio@b800!2qcom,pmk8550-gpioqcom,spmi-gpioV¸c¯sAVš¯pmic@a2qcom,pmr735dqcom,spmi-pmicV  temp-alarm@a002qcom,spmi-temp-alarmV „ Üš gpio@8800!2qcom,pmr735d-gpioqcom,spmi-gpioVˆc°sAVš°pmic@32qcom,pm8550veqcom,spmi-pmicV temp-alarm@a002qcom,spmi-temp-alarmV „ Üš!gpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpioVˆc±sAVš±pmic@52qcom,pm8550veqcom,spmi-pmicV temp-alarm@a002qcom,spmi-temp-alarmV „ Üš"gpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpioVˆc²sAVš²pmic@62qcom,pm8550veqcom,spmi-pmicV temp-alarm@a002qcom,spmi-temp-alarmV „ Üš#gpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpioVˆc³sAVš³pmic@92qcom,pm8550vsqcom,spmi-pmicV  temp-alarm@a002qcom,spmi-temp-alarmV „ Üš$gpio@8800"2qcom,pm8550vs-gpioqcom,spmi-gpioVˆc´sAVš´pinctrl@f1000002qcom,sm8750-tlmmV  „ÐcsAV�Ø `w n$Jš�hub-i2c0-data-clk-state‹gpio64gpio65 �i2chub0_se0™ lšKhub-i2c1-data-clk-state‹gpio66gpio67 �i2chub0_se1™ lšLhub-i2c2-data-clk-state‹gpio68gpio69 �i2chub0_se2™ lšMhub-i2c3-data-clk-state‹gpio70gpio71 �i2chub0_se3™ lšNhub-i2c4-data-clk-state‹gpio72gpio73 �i2chub0_se4™ lšOhub-i2c5-data-clk-state‹gpio74gpio75 �i2chub0_se5™ lšPhub-i2c6-data-clk-state‹gpio76gpio77 �i2chub0_se6™ lšQhub-i2c7-data-clk-state‹gpio82gpio83 �i2chub0_se7™ lšRhub-i2c8-data-clk-state‹gpio206gpio207 �i2chub0_se8™ lšShub-i2c9-data-clk-state‹gpio80gpio81 �i2chub0_se9™ lšTpcie0-default-statešþperst-pins‹gpio102�gpio™ ƒclkreq-pins‹gpio103�pcie0_clk_req_n™ lwake-pins‹gpio104�gpio™ lqup-i2c0-data-clk-state‹gpio32gpio33 �qup1_se0™ lšWqup-i2c1-data-clk-state‹gpio36gpio37 �qup1_se1™ lšZqup-i2c2-data-clk-state‹gpio40gpio41 �qup1_se2™ lš]qup-i2c3-data-clk-state‹gpio44gpio45 �qup1_se3™ lš`qup-i2c4-data-clk-state‹gpio48gpio49 �qup1_se4™ lšcqup-i2c5-data-clk-state‹gpio52gpio53 �qup1_se5™ lšfqup-i2c6-data-clk-state‹gpio56gpio57 �qup1_se6™ lšiqup-i2c8-data-clk-state ‹gpio0gpio1 �qup2_se0™ lš.qup-i2c9-data-clk-state ‹gpio4gpio5 �qup2_se1™ lš1qup-i2c10-data-clk-state ‹gpio8gpio9 �qup2_se2™ lš4qup-i2c11-data-clk-state‹gpio12gpio13 �qup2_se3™ lš7qup-i2c12-data-clk-state‹gpio16gpio17 �qup2_se4™ lš:qup-i2c13-data-clk-state‹gpio20gpio21 �qup2_se5™ lš=qup-i2c15-data-clk-state‹gpio28gpio29 �qup2_se7™ lšHqup-spi0-cs-state‹gpio35 �qup1_se0™²šYqup-spi0-data-clk-state‹gpio32gpio33gpio34 �qup1_se0™²šXqup-spi1-cs-state‹gpio39 �qup1_se1™²š\qup-spi1-data-clk-state‹gpio36gpio37gpio38 �qup1_se1™²š[qup-spi2-cs-state‹gpio43 �qup1_se2™²š_qup-spi2-data-clk-state‹gpio40gpio41gpio42 �qup1_se2™²š^qup-spi3-cs-state‹gpio47 �qup1_se3™²šbqup-spi3-data-clk-state‹gpio44gpio45gpio46 �qup1_se3™²šaqup-spi4-cs-state‹gpio51 �qup1_se4™²šequp-spi4-data-clk-state‹gpio48gpio49gpio50 �qup1_se4™²šdqup-spi5-cs-state‹gpio55 �qup1_se5™²šhqup-spi5-data-clk-state‹gpio52gpio53gpio54 �qup1_se5™²šgqup-spi6-cs-state‹gpio59 �qup1_se6™²škqup-spi6-data-clk-state‹gpio56gpio57gpio58 �qup1_se6™²šjqup-spi8-cs-state‹gpio3 �qup2_se0™²š0qup-spi8-data-clk-state‹gpio0gpio1gpio2 �qup2_se0™²š/qup-spi9-cs-state‹gpio7 �qup2_se1™²š3qup-spi9-data-clk-state‹gpio4gpio5gpio6 �qup2_se1™²š2qup-spi10-cs-state‹gpio11 �qup2_se2™²š6qup-spi10-data-clk-state‹gpio8gpio9gpio10 �qup2_se2™²š5qup-spi11-cs-state‹gpio15 �qup2_se3™²š9qup-spi11-data-clk-state‹gpio12gpio13gpio14 �qup2_se3™²š8qup-spi12-cs-state‹gpio19 �qup2_se4™²š<qup-spi12-data-clk-state‹gpio16gpio17gpio18 �qup2_se4™²š;qup-spi13-cs-state‹gpio23 �qup2_se5™ lš?qup-spi13-data-clk-state‹gpio20gpio21gpio22 �qup2_se5™²š>qup-spi15-cs-state‹gpio31 �qup2_se7™²šJqup-spi15-data-clk-state‹gpio28gpio29gpio30 �qup2_se7™²šIqup-uart7-default-state‹gpio62gpio63 �qup1_se7™²šlqup-uart14-default-state‹gpio26gpio27 �qup2_se6™ lš@qup-uart14-cts-rts-state‹gpio24gpio25 �qup2_se6™ ƒsdc2-sleep-stateš•clk-pins ‹sdc2_clk™²cmd-pins ‹sdc2_cmd™ ldata-pins ‹sdc2_data™ lsdc2-default-stateš“clk-pins ‹sdc2_clk™²cmd-pins ‹sdc2_cmd™  ldata-pins ‹sdc2_data™  lbt-default-stateš6sw-ctrl-pins‹gpio18�gpio ƒsd-card-det-n-state‹gpio55�gpio™ lš”wcd-reset-n-active-state‹gpio101�gpio™²æš&wlan-en-state‹gpio16�gpio™ ƒš5clock-controller@f2040082qcom,sm8750-tcsrsysconV @0rmy†š˜stm@10002000 2arm,coresight-stmarm,primecell V 7( Istm-basestm-stimulus-baseru Öapb_pclkout-portsportendpoint𵚻tpda@10004000"2qcom,coresight-tpdaarm,primecellV@ru Öapb_pclkin-ports port@1Vendpoint𶚸out-portsportendpoint𷚺tpdm@1000f000"2qcom,coresight-tpdmarm,primecellVðru Öapb_pclk ’@ ¨ out-portsportendpoint𸚶funnel@10041000+2arm,coresight-dynamic-funnelarm,primecellVru Öapb_pclkin-ports port@0Vendpointð¹šéport@6Vendpoint𺚷port@7Vendpoint𻚵out-portsportendpointð¼šìtpdm@10800000"2qcom,coresight-tpdmarm,primecellV€ru Öapb_pclk º  Ð out-portsportendpoint𽚾tpda@10803000"2qcom,coresight-tpdaarm,primecellV€0ru Öapb_pclkin-ports port@0Vendpoint𾚽port@1Vendpointð¿šout-portsportendpointðÀšÁfunnel@10804000+2arm,coresight-dynamic-funnelarm,primecellV€@ru Öapb_pclkin-portsportendpointðÁšÀout-portsportendpointðšÜcti@1080b000 2arm,coresight-ctiarm,primecellV€°ru Öapb_pclktpdm@1082c000"2qcom,coresight-tpdmarm,primecellV‚Àru Öapb_pclk Ð out-portsportendpointðÚÞtpdm@10841000"2qcom,coresight-tpdmarm,primecellV„ru Öapb_pclk ¨ out-portsportendpointðÄšßtpdm@1084e000"2qcom,coresight-tpdmarm,primecellV„àru Öapb_pclk ’  ¨ out-portsportendpointðÅšÈtpdm@1084f000"2qcom,coresight-tpdmarm,primecellV„ðru Öapb_pclk ’  ¨ out-portsportendpointðÆšÉtpdm@10850000"2qcom,coresight-tpdmarm,primecellV…ru Öapb_pclk ’@ ¨ out-portsportendpointðÇšÊtpda@10851000"2qcom,coresight-tpdaarm,primecellV…ru Öapb_pclkin-ports port@0VendpointðÈšÅport@1VendpointðÉšÆport@2VendpointðÊšÇout-portsportendpointðËšÛtpdm@10980000"2qcom,coresight-tpdmarm,primecellV˜ru Öapb_pclk º  Ð out-portsportendpointðÌšÍtpda@10986000"2qcom,coresight-tpdaarm,primecellV˜`ru Öapb_pclkin-ports port@0VendpointðÍšÌport@1VendpointðΚport@2VendpointðÏšout-portsportendpointðКÑfunnel@10987000+2arm,coresight-dynamic-funnelarm,primecellV˜pru Öapb_pclkin-portsportendpointðÑšÐout-portsportendpointðÒšÝcti@1098b000 2arm,coresight-ctiarm,primecellV˜°ru Öapb_pclktpdm@109a3000"2qcom,coresight-tpdmarm,primecellVš0ru Öapb_pclk ¨  Ð out-portsportendpointðÓšåtpdm@109a4000"2qcom,coresight-tpdmarm,primecellVš@ru Öapb_pclk ¨ out-portsportendpointðÔšätpdm@109a5000"2qcom,coresight-tpdmarm,primecellVšPru Öapb_pclk Ð out-portsportendpointðÕšátpdm@109a6000"2qcom,coresight-tpdmarm,primecellVš`ru Öapb_pclk Ð out-portsportendpointðÖšâtpdm@109a7000"2qcom,coresight-tpdmarm,primecellVšpru Öapb_pclk Ð out-portsportendpointðךãtpdm@109a8000"2qcom,coresight-tpdmarm,primecellVš€ru Öapb_pclk ¨ out-portsportendpointðØšætpdm@109a9000"2qcom,coresight-tpdmarm,primecellVš�ru Öapb_pclk ¨ out-portsportendpointðÙšçtpdm@109aa000"2qcom,coresight-tpdmarm,primecellVš ru Öapb_pclk ¨ out-portsportendpointðÚšètn@109ab000"2qcom,coresight-tnocarm,primecellVš°Bru Öapb_pclkin-ports port@4VendpointðÛšËport@dV endpointðÜšÂport@10VendpointðÝšÒport@11VendpointðÞšÃport@12VendpointðßšÄport@13Vendpointðàšêport@19VendpointðášÕport@1aVendpointðâšÖport@1bVendpointðãš×port@1cVendpointðäšÔport@1dVendpointðåšÓport@1eVendpointðæšØport@1fVendpointðçšÙport@20V endpointðèšÚout-portsportendpointðéš¹tpdm@109d0000"2qcom,coresight-tpdmarm,primecellV�ru Öapb_pclk Ð out-portsportendpointðêšàfunnel@10b04000+2arm,coresight-dynamic-funnelarm,primecellV°@ru Öapb_pclkin-ports port@6Vendpointðëšôport@7Vendpointðìš¼out-portsportendpointðíšîtmc@10b05000 2arm,coresight-tmcarm,primecellV°Pru Öapb_pclkin-portsportendpointðîšítpda@10b08000"2qcom,coresight-tpdaarm,primecellV°€ru Öapb_pclkin-ports port@0Vendpointðïšõport@1Vendpointððšöport@2Vendpointðñš÷port@3Vendpointðòšøport@4Vendpointðóšùout-portsportendpointðôšëtpdm@10b09000"2qcom,coresight-tpdmarm,primecellV°�ru Öapb_pclk ’@ ¨ out-portsportendpointðõšïtpdm@10b0a000"2qcom,coresight-tpdmarm,primecellV° ru Öapb_pclk ’@ ¨ out-portsportendpointðöšðtpdm@10b0b000"2qcom,coresight-tpdmarm,primecellV°°ru Öapb_pclk ’@ ¨ out-portsportendpointð÷šñtpdm@10b0c000"2qcom,coresight-tpdmarm,primecellV°Àru Öapb_pclk ’@ ¨ out-portsportendpointðøšòtpdm@10b0d000"2qcom,coresight-tpdmarm,primecellV°Ðru Öapb_pclk º  Ð out-portsportendpointðùšóiommu@15000000/2qcom,sm8750-smmu-500qcom,smmu-500arm,mmu-500VL„Aabcdefghijklmnopqrstuvµ¶·¸¹º»¼½¾¿À;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXY‹Œ�Ž��‘’“”•–—˜™¢£œ¥Ã§¨©²³´µ¶·¸¹šèéêëìíîïðñòóôõö â ï`š(interrupt-controller@16000000 2arm,gic-v3 V  „ VA   ¢šmsi-controller@160400002arm,gic-v3-itsV . =šúpcie@1c00000Jpci"2qcom,pcie-sm8750qcom,pcie-sm8550`VÀ0@@ ¨@@À0 Iparfdbielbiatuconfigmhi T¢@ @0@0#Ð Hÿ` R cúú kÿ xl„�Ž��‘’“”Œ/ßmsi0msi1msi2msi3msi4msi5msi6msi7globalV ‚  ••–—˜@r)%)')()-).))) IÖauxcfgbus_masterbus_slaveslave_q2addrss_sf_tbunoc_aggrcnoc_sf_axi0&û+üâpcie-memcpu-pcie £((<)±pciy)ñýÏokayþdefaultopp-table2operating-points-v2šýopp-2500000~&% …– ­Ð�opp-5000000~LK@…– ­¡ opp-10000000~˜–€…– ­B@opp-8000000~z…ž ­´opp-16000000~ô$…ž ­ hpcie@0JpciV Hÿ ¢¬& »�h Æ�fwifi@0 2pci17cb,1107VA-B;CJDYEjF{G Òÿ äphy@1c06000 2qcom,sm8750-qmp-gen3x2-pcie-phyVÀ` (r)%)'˜)))+Öauxcfg_ahbrefrchngpipe))õá<)±phyy)y®pcie0_pipe_clk“ÏokayÐàšš&phy@1d800002qcom,sm8750-qmp-ufs-phyVØ rm)�˜Örefref_auxqref<±ufsphyy)y“ÏokayÐàššufs@1d84000+2qcom,sm8750-ufshcqcom,ufshcjedec,ufs-2.0VØ@0 „ @r)Š))‰)™m)—)“)•nÖcore_clkbus_aggr_clkiface_clkcore_clk_uniproref_clktx_lane0_sync_clkrx_lane0_sync_clkrx_lane1_sync_clkñ<)±rst0&U+,âufs-ddrcpu-ufsy)…ž È(`` ö¬%ufsphy†Ïokay Æ�×  Ö  & 2O€šopp-table2operating-points-v2šopp-100000000@~õáõá…–opp-403000000@~JÀJÀ…žmailbox@1643000002qcom,sm8750-cpucp-mboxqcom,x1e80100-cpucp-mbox VC€ƒ€ „“šrsc@165000002qcom,rpmh-rsc0VPQR Idrv-0drv-1drv-2$„ D  T ` ;apps_rscy bcm-voter2qcom,bcm-voteršclock-controller2qcom,sm8750-rpmh-clkrÖxoyšmpower-controller2qcom,sm8750-rpmhpdñ Lšpopp-table2operating-points-v2š opp-16 popp-48 p0opp-50 p2opp-52 p4opp-56 p8š§opp-60 p<opp-64 p@š–opp-80 pPopp-128 p€š¦opp-144 p�opp-192 pÀš—opp-224 pàopp-256 pšžopp-320 p@š¨opp-336 pPopp-384 p€š©opp-416 p opp-432 p°opp-448 pÀopp-452 pÄopp-480 pàregulators-02qcom,pm8550-rpmh-regulators z  Š  š  ¯  Å  Ó  å  ö      %  4 Cbbob1 Pvreg_bob1 _-æ w=  �š bob2 Pvreg_bob2 _)B€ w-æ �šldo1 Pvreg_l1b_1p8 _w@ ww@ � ¦ ¿šŽldo2 Pvreg_l2b_3p0 _-æ w.‚@ � ¦ ¿ldo4 Pvreg_l4b_1p8 _w@ ww@ � ¦ ¿ldo5 Pvreg_l5b_3p1 _/M` w0à � ¦ ¿š®ldo6 Pvreg_l6b_1p8 _w@ w-æ � ¦ ¿ldo7 Pvreg_l7b_1p8 _w@ w-æ � ¦ ¿ldo8 Pvreg_l8b_1p8 _w@ w-æ � ¦ ¿š’ldo9 Pvreg_l9b_2p9 _-*€ w-æ � ¦ ¿š‘ldo10 Pvreg_l10b_1p8 _w@ ww@ � ¦ ¿ldo11 Pvreg_l11b_1p0 _<@ w¶à � ¦ ¿ldo12 Pvreg_l12b_1p8 _O€ ww@ � ¦ ¿ldo13 Pvreg_l13b_3p0 _-ÆÀ w-ÆÀ � ¦ ¿ldo14 Pvreg_l14b_3p2 _0Ô w0Ô � ¦ ¿ldo15 Pvreg_l15b_1p8 _w@ ww@ � ¦ ¿šˆldo16 Pvreg_l16b_2p8 _*¹€ w*¹€ � ¦ ¿ldo17 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BIAS1TX SWR_INPUT1ADC2_OUTPUTwcd-playback-dai-link  WCD Playbackcodec+,‚cpu-qplatform.wcd-capture-dai-link  WCD Capturecodec+/Šcpu-xplatform.wsa-dai-link  WSA Playbackcodec012„cpu-iplatform.va-dai-link  VA Capturecodeccpu-nplatform.pmic-glink>2qcom,sm8750-pmic-glinkqcom,sm8550-pmic-glinkqcom,pmic-glink  �=connector@02usb-c-connectorV0dual;dualports port@0Vendpointð3š port@1Vendpointð4šœport@2Vendpointvph-pwr-regulator2regulator-fixed Pvph_pwr _8u  w8u EYš wcn7850-pmu2qcom,wcn7850-pmudefault56 k� }²ò7�8š9-:ªj { rmregulatorsldo0 Pvreg_pmu_rfa_cmnšAldo1 Pvreg_pmu_aon_0p59šBldo2 Pvreg_pmu_wlcx_0p8šCldo3 Pvreg_pmu_wlmx_0p85šDldo4 Pvreg_pmu_btcmx_0p85ldo5 Pvreg_pmu_rfa_0p8šEldo6 Pvreg_pmu_rfa_1p2šFldo7 Pvreg_pmu_rfa_1p8šGldo8 Pvreg_pmu_pcie_0p9šÿldo9 Pvreg_pmu_pcie_1p8š interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typedevice_typeregenable-methodnext-level-cachepower-domainspower-domain-namesphandlecache-levelcache-unifiedcpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usinterconnectsmboxesmbox-namesshmem#power-domain-cells#interconnect-cellsqcom,bcm-votersinterruptsdomain-idle-statesrangesno-maphwlocksalloc-rangesalignmentsizereusableinterrupts-extendedqcom,smemqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-rangesclocks#clock-cells#reset-cells#mbox-cellsdma-channelsdma-channel-mask#dma-cellsiommusstatusclock-namesinterconnect-namesdmasdma-namespinctrl-0pinctrl-namesvddrfacmn-supplyvddaon-supplyvddwlcx-supplyvddwlmx-supplyvddrfa0p8-supplyvddrfa1p2-supplyvddrfa1p8-supplymax-speedqcom,eeqcom,num-eesnum-channelsqcom,controlled-remotely#hwlock-cellsinterrupt-namesmemory-regionqcom,qmpqcom,smem-statesqcom,smem-state-namesfirmware-namelabelqcom,glink-channelsqcom,vmidsdma-coherentqcom,domainqcom,intents#sound-dai-cellsqcom,protection-domainclock-output-namesqcom,din-portsqcom,dout-portsqcom,ports-sintervalqcom,ports-offset1qcom,ports-offset2qcom,ports-hstartqcom,ports-hstopqcom,ports-word-lengthqcom,ports-block-pack-modeqcom,ports-block-group-countqcom,ports-lane-controlqcom,rx-port-mappingpowerdown-gpiossound-name-prefix#thermal-sensor-cellsvdd-supplyqcom,port-mappingqcom,ports-sinterval-lowqcom,tx-port-mappingvdd-micb-supplyqcom,dmic-sample-rategpio-controller#gpio-cellsgpio-rangespinsfunctiondrive-strengthslew-ratebias-disablebias-bus-holdoutput-highinput-enableoutput-lowoperating-points-v2qcom,dll-configqcom,ddr-configbus-widthmax-sd-hs-hzresetscd-gpiosvmmc-supplyvqmmc-supplyno-sdiono-mmcpinctrl-1opp-hzrequired-opps#phy-cellsvdda12-supplyphysreset-namesorientation-switchvdda-phy-supplyvdda-pll-supplyremote-endpointassigned-clocksassigned-clock-ratesphy-namessnps,hird-thresholdsnps,usb2-gadget-lpm-disablesnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,is-utmi-l1-suspendsnps,usb3_lpm_capablesnps,usb2-lpm-disablesnps,has-lpm-erratumtx-fifo-resizeusb-role-switchqcom,pdc-rangesreg-namesqcom,channelqcom,bus-idbias-pull-uppower-sourcecolorled-sourcesled-max-microampflash-max-microampflash-max-timeout-usfunction-enumerator#pwm-cellsqcom,tune-usb2-preemqcom,tune-usb2-amplitudeqcom,squelch-detector-bpvdd18-supplyvdd3-supplylinux,codebitswakeup-parentgpio-reserved-rangesbias-pull-downqcom,cmb-element-bitsqcom,cmb-msrs-numqcom,dsb-element-bitsqcom,dsb-msrs-num#iommu-cells#global-interrupts#redistributor-regionsredistributor-stridemsi-controller#msi-cellsbus-rangelinux,pci-domainmsi-mapmsi-map-masknum-lanesinterrupt-map-maskinterrupt-mapiommu-mapopp-peak-kBpswake-gpiosreset-gpiosvddpcie0p9-supplyvddpcie1p8-supplylanes-per-directionvcc-supplyvcc-max-microampvccq-supplyvccq-max-microampqcom,tcs-offsetqcom,drv-idqcom,tcs-configopp-levelvdd-bob1-supplyvdd-bob2-supplyvdd-l1-l4-l10-supplyvdd-l2-l13-l14-supplyvdd-l3-supplyvdd-l5-l16-supplyvdd-l6-l7-supplyvdd-l8-l9-supplyvdd-l11-supplyvdd-l12-supplyvdd-l15-supplyvdd-l17-supplyqcom,pmic-idregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-allow-set-loadregulator-allowed-modesvdd-l1-supplyvdd-l2-supplyvdd-s1-supplyvdd-s3-supplyvdd-s4-supplyvdd-s5-supplyvdd-s7-supplyvdd-s8-supplyvdd-s2-supplyvdd-l1-l2-supplyvdd-l3-l4-supplyvdd-l5-supplyvdd-l6-supplyvdd-l7-supplyframe-numbernonposted-mmioqcom,non-secure-domainpolling-delay-passivethermal-sensorstemperaturehysteresisnvmem-cellsnvmem-cell-namesmode-recoverymode-bootloaderserial0qcom,micbias1-microvoltqcom,micbias2-microvoltqcom,micbias3-microvoltqcom,micbias4-microvoltqcom,mbhc-buttons-vthreshold-microvoltqcom,mbhc-headset-vthreshold-microvoltqcom,mbhc-headphone-vthreshold-microvoltqcom,rx-deviceqcom,tx-devicevdd-buck-supplyvdd-rxtx-supplyvdd-io-supplyvdd-mic-bias-supplyvdd-px-supplystdout-pathclock-frequencyclock-multclock-divdebounce-intervallinux,can-disablewakeup-sourceaudio-routinglink-namesound-daiorientation-gpiospower-roledata-roleregulator-always-onregulator-boot-onwlan-enable-gpiosbt-enable-gpiosvddio-supplyvddio1p2-supplyvdddig-supply