Ð þíwB8pt(Îp< ,Xiaomi Redmi Note 82xiaomi,ginkgoqcom,sm6125=handsetJŠchosen Vframebuffer@5c0000002simple-framebuffer]\š?€a8g $nà ua8r8g8b8clocksxo-board 2fixed-clock|‰$ø™sleep-clk 2fixed-clock|‰ü ¡sleep_clk™cpus cpu@0´cpu 2qcom,kryo260]ÀpsciÎá™l2-cache2cacheòþ™cpu@1´cpu 2qcom,kryo260]ÀpsciÎá™cpu@2´cpu 2qcom,kryo260]ÀpsciÎá™cpu@3´cpu 2qcom,kryo260]ÀpsciÎá™cpu@100´cpu 2qcom,kryo260]ÀpsciÎfá™l2-cache2cacheòþ™cpu@101´cpu 2qcom,kryo260]ÀpsciÎfá™ cpu@102´cpu 2qcom,kryo260]ÀpsciÎfá™ cpu@103´cpu 2qcom,kryo260]ÀpsciÎfá™ cpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1 core2 core3 firmwarescm2qcom,scm-sm6125qcom,scmmemory@40000000]@´memorypmu2arm,armv8-pmuv3 psci 2arm,psci-1.0Çsmcremoteproc#2qcom,sm6125-rpm-procqcom,rpm-procglink-edge2qcom,glink-rpm Â( 9 rpm-requests#2qcom,rpm-sm6125qcom,glink-smd-rpm @rpm_requestsclock-controller2qcom,rpmcc-sm6125qcom,rpmcc|T[xo™power-controller2qcom,sm6125-rpmpdg{™opp-table2operating-points-v2™opp1�™Topp2� opp3�0opp4�@™Lopp5�€™Mopp6�À™Nopp7�™Oopp8�@opp9�€™Popp10� regulators-02qcom,rpm-pm6125-regulatorss6™H@±²°l1™O€±*@l2™B@±l3™B@±<@l4™ N@±ä€Él5™%€±-pÉ™"l6™Ê± €l7™ N@±ä€™l8™€± Àl9™w@±î@l10™w@±î@É™l11™w@±ÉÉ™l12™w@±tàl13™w@±ô@l14™w@± €l15™/]±1Q™l16™w@± €l17™ ±åÀl18™O€±I€Él19™%€±- @l20™%€±- @l21™'¬@±+”@l22™,ì±-pÉ™!l23™-ÆÀ±3á@l24™,ì±-pÉ™reserved-memory Vmemory@45700000]Ep`âmemory@45e00000]Eàâmemory@45fff000]Eÿðâmemory@46000000]F â™memory@46200000]F Ðâmemory@4ab00000]J°Pâmemory@4b000000]Kàâmemory@52e00000]RàPâmemory@53300000]S0 âmemory@53500000]SPàâmemory@5cf00000]\ðâmemory@5f800000]_€àâmemory@5e400000]^@@âmemory@f3000000]ó@âmemory@f3400000]ó@€âmemory@13fc00000]?À@âadsp_pil_mem@55300000]U0 âipa_fw_mem@57500000]WPâipa_gsi_mem@57510000]WQPâgpu_mem@57515000]WQP âframebuffer@5c000000]\š?€âramoops@616000002ramoops]a`@éõ ÿsmem 2qcom,smem soc@0 Vÿÿÿÿ 2simple-bushwlock@3400002qcom,tcsr-mutex]4"™pinctrl@5000002qcom,sm6125-tlmm]P@�@Ð@0westsoutheast ã:J†Vbwˆ™sdc2-off-state™ clk-pins �sdc2_clk¢±cmd-pins �sdc2_cmd¢¾data-pins �sdc2_data¢¾sd-cd-pins�gpio98Ëgpio¢±sdc2-on-state™clk-pins �sdc2_clk¢±cmd-pins �sdc2_cmd¢ ¾data-pins �sdc2_data¢ ¾sd-cd-pins�gpio98Ëgpio¢¾qup-i2c0-default-state �gpio0gpio1Ëqup00¢±™%qup-i2c0-sleep-state �gpio0gpio1Ëgpio¢¾™&qup-i2c1-default-state �gpio4gpio5Ëqup01¢±™*qup-i2c1-sleep-state �gpio4gpio5Ëgpio¢¾™+qup-i2c2-default-state �gpio6gpio7Ëqup02¢±™,qup-i2c2-sleep-state �gpio6gpio7Ëgpio¢¾™-qup-i2c3-default-state�gpio14gpio15Ëqup03¢±™0qup-i2c3-sleep-state�gpio14gpio15Ëgpio¢¾™1qup-i2c4-default-state�gpio16gpio17Ëqup04¢±™2qup-i2c4-sleep-state�gpio16gpio17Ëgpio¢¾™3qup-i2c5-default-state�gpio22gpio23Ëqup10¢±™4qup-i2c5-sleep-state�gpio22gpio23Ëgpio¢¾™5qup-i2c6-default-state�gpio30gpio31Ëqup11¢±™9qup-i2c6-sleep-state�gpio30gpio31Ëgpio¢¾™:qup-i2c7-default-state�gpio28gpio29Ëqup12¢±™=qup-i2c7-sleep-state�gpio28gpio29Ëgpio¢¾™>qup-i2c8-default-state�gpio18gpio19Ëqup13¢±™?qup-i2c8-sleep-state�gpio18gpio19Ëgpio¢¾™@qup-i2c9-default-state�gpio10gpio11Ëqup14¢±™Cqup-i2c9-sleep-state�gpio10gpio11Ëgpio¢¾™Dqup-spi0-default-state�gpio0gpio1gpio2gpio3Ëqup00¢±™(qup-spi0-sleep-state�gpio0gpio1gpio2gpio3Ëgpio¢±™)qup-spi2-default-state�gpio6gpio7gpio8gpio9Ëqup02¢±™.qup-spi2-sleep-state�gpio6gpio7gpio8gpio9Ëgpio¢±™/qup-spi5-default-state�gpio22gpio23gpio24gpio25Ëqup10¢±™7qup-spi5-sleep-state�gpio22gpio23gpio24gpio25Ëgpio¢±™8qup-spi6-default-state�gpio30gpio31gpio32gpio33Ëqup11¢±™;qup-spi6-sleep-state�gpio30gpio31gpio32gpio33Ëgpio¢±™<qup-spi8-default-state�gpio18gpio19gpio20gpio21Ëqup13¢±™Aqup-spi8-sleep-state�gpio18gpio19gpio20gpio21Ëgpio¢±™Bqup-spi9-default-state�gpio10gpio11gpio12gpio13Ëqup14¢±™Equp-spi9-sleep-state�gpio10gpio11gpio12gpio13Ëgpio¢±™Fclock-controller@14000002qcom,gcc-sm6125]@|g[bi_tcxosleep_clk T™phy@16130002qcom,msm8996-qusb2-phy]a0€ÔT [cfg_ahbrefßæokayíø™Gspmi@1c400002qcom,spmi-pmic-arb(]Äààð À `0corechnlsobsrvrintrcnfg periph_irq ·-5 bwpmic@02qcom,pm6125qcom,spmi-pmic] pon@8002qcom,pm8998-pon]BRpwrkey2qcom,pm8941-pwrkey`= it¾æokayresin2qcom,pm8941-resin`= ¾æokayirtemp-alarm@24002qcom,spmi-temp-alarm]$$t€thermal‘™Uadc@31002qcom,spmi-adc5]1 1§™channel@0]¹Êref_gndchannel@1]¹ Êvref_1p25channel@6]¹ Êdie_tempchannel@83]ƒ¹Êvph_pwrchannel@85]…¹Êvcoinchannel@4c]L¹ÐÈä Êxo_thermadc-tm@35002qcom,spmi-adc-tm5]55 ‘ ædisabledrtc@60002qcom,pm8941-rtc]`a 0rtcalarma ædisabledgpio@c000 2qcom,pm6125-gpioqcom,spmi-gpio]À:J Vbw™vol-up-n-state�gpio6Ënormalõ¾™Vpmic@12qcom,pm6125qcom,spmi-pmic]sram@45f00002qcom,rpm-msg-ram]_p™ mmc@4744000$2qcom,sm6125-sdhciqcom,sdhci-msm-v5]t@tP 0hccqhci\`hc_irqpwr_irqT£¤[ifacecorexo `$d,4€sDN\æokayiummc@4784000$2qcom,sm6125-sdhciqcom,sdhci-msm-v5]x@0hc^ahc_irqpwr_irqT¨©[ifacecorexo €‚Œ –defaultsleep$d,4€sDæokay ¤bi!u"­µufshc@4804000+2qcom,sm6125-ufshcqcom,ufshcjedec,ufs-2.0]€@0�€0stdice d@T¯¬®·¶µ±i[core_clkbus_aggr_clkiface_clkcore_clk_uniproref_clktx_lane0_sync_clkrx_lane0_sync_clkice_core_clk@¼úð€N<4`ðÑ€xhÀá£ßÊrstÖ#Ûufsphyå  ædisabled™$phy@48070002qcom,sm6125-qmp-ufs-phy]€p ¸T³Ð[refref_auxqrefß$ÊufsphyÔ ædisabled™#dma-controller@4a00000(2qcom,sm6125-gpi-dmaqcom,sdm845-gpi-dma] `OPQRSTUVù 6 ædisabled™'geniqup@4ac00002qcom,geni-se-qup]¬ TŸ  [m-ahbs-ahb # V ædisabledi2c@4a800002qcom,geni-i2c]¨@T…[se G‚%Œ&–defaultsleep "'''txrx  ædisabledspi@4a800002qcom,geni-spi]¨@T…[se G‚(Œ)–defaultsleep "'''txrx  ædisabledi2c@4a840002qcom,geni-i2c]¨@@T‡[se H‚*Œ+–defaultsleep "'''txrx  ædisabledi2c@4a880002qcom,geni-i2c]¨€@T‰[se I‚,Œ-–defaultsleep "'''txrx  ædisabledspi@4a880002qcom,geni-spi]¨€@T‰[se I‚.Œ/–defaultsleep "'''txrx  ædisabledi2c@4a8c0002qcom,geni-i2c]¨À@T‹[se J‚0Œ1–defaultsleep "'''txrx  ædisabledi2c@4a900002qcom,geni-i2c]©@T�[se K‚2Œ3–defaultsleep "'''txrx  ædisableddma-controller@4c00000(2qcom,sm6125-gpi-dmaqcom,sdm845-gpi-dma]À`:;<=>?@Aù V ædisabled™6geniqup@4cc00002qcom,geni-se-qup]Ì T¡¢ [m-ahbs-ahb C V ædisabledi2c@4c800002qcom,geni-i2c]È@T“[se 4‚4Œ5–defaultsleep "66'txrx  ædisabledspi@4c800002qcom,geni-spi]È@T“[se 4‚7Œ8–defaultsleep "66'txrx  ædisabledi2c@4c840002qcom,geni-i2c]È@@T•[se 5‚9Œ:–defaultsleep "66'txrx  ædisabledspi@4c840002qcom,geni-spi]È@@T•[se 5‚;Œ<–defaultsleep "66'txrx  ædisabledi2c@4c880002qcom,geni-i2c]È€@T—[se 6‚=Œ>–defaultsleep "66'txrx  ædisabledi2c@4c8c0002qcom,geni-i2c]ÈÀ@T™[se 7‚?Œ@–defaultsleep "66'txrx  ædisabledspi@4c8c0002qcom,geni-spi]ÈÀ@T™[se 7‚AŒB–defaultsleep "66'txrx  ædisabledi2c@4c900002qcom,geni-i2c]É@T›[se 8‚CŒD–defaultsleep "66'txrx  ædisabledspi@4c900002qcom,geni-spi]É@T›[se 8‚EŒF–defaultsleep "66'txrx  ædisabledusb@4ef88002qcom,sm6125-dwc3qcom,dwc3]ïˆ V0Td¹­½»Í&[cfg_noccoreifacesleepmock_utmixo1»¹A$øù@«0.þ¦*pwr_eventqusb2_phyhs_phy_irqss_phy_irqVæokayusb@4e00000 2snps,dwc3]àÍ ÿ ÖG Ûusb2-physŒ¤¼ Ôhigh-speed âperipheralsram@46900002qcom,rpm-stats]idisplay-subsystem@5e000002qcom,sm6125-mdss]à0mdss ºbwTfHH[ifaceahbcoreH  V ædisabled™Idisplay-controller@5e010002qcom,sm6125-dpu]à2ë0 0mdpvbifI8ThHHHHHi&[busifacerotlutcorevsyncthrottle1HA$ø{Jports port@0]endpointêK™Sopp-table2operating-points-v2™Jopp-192000000ú q°Lopp-256000000úB@Mopp-307200000úO€Nopp-384000000úã`Oopp-400000000úׄPdsi@5e94000(2qcom,sm6125-dsi-ctrlqcom,mdss-dsi-ctrl]é@ 0dsi_ctrlI0THHHHHh$[bytebyte_intfpixelcoreifacebus1HHQQ{RÖQÛdsi  ædisabledports port@0]endpointêS™Kport@1]endpointopp-table2operating-points-v2™Ropp-164000000ú ÆqLopp-187500000ú -àMphy@5e944002qcom,sm6125-dsi-phy-14nm]éDéEéHˆ0dsi_phydsi_phy_lanedsi_pll|ÔTH [ifacerefO ædisabled™Qclock-controller@5f000002qcom,sm6125-dispcc]ð4TQQfg£[bi_tcxodsi0_phy_pll_out_byteclkdsi0_phy_pll_out_dsiclkdsi1_phy_pll_out_dsiclkdp_phy_pll_link_clkdp_phy_pll_vco_div_clkcfg_ahb_clkgcc_disp_gpll0_div_clk_srcT|g™Hiommu@c600000/2qcom,sm6125-smmu-500qcom,smmu-500arm,mmu-500] ` QXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€�‚ƒ„…†‡ˆ‰Š‹Œ�Ž��‘’“”•–—&9™mailbox@f111000;2qcom,sm6125-apcs-hmss-globalqcom,msm8994-apcs-kpss-global]F™ timer@f1200002arm,armv7-timer-mem V]‰$øframe@f121000R] frame@f123000R  ]0 ædisabledframe@f124000R  ]@ ædisabledframe@f125000R  ]P ædisabledframe@f126000R  ]` ædisabledframe@f127000R  ]p ædisabledframe@f128000R ]€ ædisabledinterrupt-controller@f200000 2arm,gic-v3] 0wb  ™timer2arm,armv8-timer0‰$øthermal-zonespm6125-thermal_duUtripstrip0…s‘Epassivetrip1…Á8‘Ehottrip2…6h‘ Ecriticalgpio-keys 2gpio-keys‚V–defaultkey-volume-up ÊVolume Up §isœ®À interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typeqcom,msm-idrangesregwidthheightstrideformat#clock-cellsclock-frequencyphandleclock-output-namesdevice_typeenable-methodcapacity-dmips-mhznext-level-cachecache-levelcache-unifiedcpu#reset-cellsinterruptsqcom,rpm-msg-rammboxesqcom,glink-channelsclocksclock-names#power-domain-cellsoperating-points-v2opp-levelregulator-min-microvoltregulator-max-microvoltregulator-allow-set-loadno-maprecord-sizepmsg-sizeconsole-sizememory-regionhwlocks#hwlock-cellsreg-namesgpio-controllergpio-ranges#gpio-cellsinterrupt-controller#interrupt-cellsgpio-reserved-rangespinsdrive-strengthbias-disablebias-pull-upfunction#phy-cellsresetsstatusvdd-supplyvdda-pll-supplyvdda-phy-dpdm-supplyinterrupt-namesqcom,eeqcom,channelmode-bootloadermode-recoverydebouncelinux,codeio-channelsio-channel-names#thermal-sensor-cells#io-channel-cellsqcom,pre-scalinglabelqcom,hw-settle-timeqcom,ratiometricpower-sourceinput-enableiommuspower-domainsqcom,dll-configqcom,ddr-configbus-widthnon-removablesupports-cqevmmc-supplyvqmmc-supplypinctrl-0pinctrl-1pinctrl-namescd-gpiosno-sdiono-mmcfreq-table-hzreset-namesphysphy-nameslanes-per-directiondma-channelsdma-channel-mask#dma-cellsdmasdma-namesassigned-clocksassigned-clock-ratesqcom,select-utmi-as-pipe-clksnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirkmaximum-speeddr_moderemote-endpointopp-hzrequired-oppsassigned-clock-parents#global-interrupts#iommu-cells#mbox-cellsframe-numberpolling-delay-passivethermal-sensorstemperaturehysteresisdebounce-intervallinux,can-disablewakeup-source