Ð þíi�8]D( I] 6kontron,3-5-sbc-i1200mediatek,mt8395mediatek,mt8195 +7Kontron 3.5"-SBC-i1200aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000€/soc/vpp-merge@1c10d000‡/soc/vpp-merge@1c10e000Ž/soc/vpp-merge@1c10f000•/soc/vpp-merge@1c110000œ/soc/dma-controller@1c104000§/soc/dma-controller@1c105000²/soc/dma-controller@1c106000½/soc/dma-controller@1c107000È/soc/dma-controller@1c108000Ó/soc/dma-controller@1c109000Þ/soc/dma-controller@1c10a000é/soc/dma-controller@1c10b000ô/soc/mmc@11230000ù/soc/mmc@11240000þ/soc/serial@11001200/soc/serial@11001300/soc/serial@11001400/soc/serial@11001500/soc/serial@11001100cpus+cpu@0&cpuarm,cortex-a5526psciDXec3@h4{‹€˜@ª€·€Ä@Ö€ãô cpu@100&cpuarm,cortex-a5526psciDXec3@h4{‹€˜@ª€·€Ä@Ö€ãô cpu@200&cpuarm,cortex-a5526psciDXec3@h4{‹€˜@ª€·€Ä@Ö€ãô cpu@300&cpuarm,cortex-a5526psciDXec3@h4{‹€˜@ª€·€Ä@Ö€ãô cpu@400&cpuarm,cortex-a7826psciDX�fÔÀh{‹˜@ª·Ä@Öãô cpu@500&cpuarm,cortex-a7826psciDX�fÔÀh{‹˜@ª·Ä@Öãôcpu@600&cpuarm,cortex-a7826psciDX�fÔÀh{‹˜@ª·Ä@Öãôcpu@700&cpuarm,cortex-a7826psciDX�fÔÀh{‹˜@ª·Ä@Öãôcpu-mapcluster0core0 core1 core2 core3 core4 core5 core6 core7 idle-statespscicpu-retention-larm,idle-state3D2U_eDcpu-retention-barm,idle-state3D-UŒeäcpu-off-larm,idle-state3D7U›eHcpu-off-barm,idle-state3D2UÈeèl2-cache0cachev�š@¬ã‚l2-cache1cachev�š@¬ã‚l3-cachecachev� š@¬‚dsu-pmu arm,dsu-pmu� ›  faildmic-codec dmic-codec§´2mt8195-soundÄ  disabledfixed-factor-clock-13mfixed-factor-clockÖãêôÿclk13m(oscillator-26m fixed-clockÖXŒº€ÿclk26moscillator-32k fixed-clockÖX€ÿclk32kperformance-controller@11bc10mediatek,cpufreq-hw 2¼ ½0 opp-table-gpuoperating-points-v2,nopp-3900000007>í€> ‰hopp-4100000007p€> ¡Òopp-4310000007°‰À> ¡Òopp-47300000071h@> º<opp-5150000007²FÀ> º<opp-5560000007!#ã> Ò¦opp-5980000007#¤Á€> ëopp-6400000007&% > ëopp-6700000007'ïc€> äopp-7000000007)¹'> L¸opp-7300000007+‚ê€> }Œopp-7600000007-L®> ®`opp-7900000007/q€> ß4opp-82000000070à5> opp-85000000072©ø€> @Üopp-88000000074s¼> q°pmu-a55arm,cortex-a55-pmu �pmu-a78arm,cortex-a78-pmu �psci arm,psci-1.0=smctimerarm,armv8-timer @�   soc+ simple-busLSinterrupt-controller@c000000 arm,gic-v3^o † 2   � ppi-partitionsinterrupt-partition-0› interrupt-partition-1› syscon@10000000 mediatek,mt8195-topckgensyscon2Ösyscon@10001000#mediatek,mt8195-infracfg_aosyscon2Ö¤syscon@10003000mediatek,mt8195-pericfgsyscon20ÖApinctrl@10005000mediatek,mt8195-pinctrl€2PÑÓÔâëô°B±iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint»Ë×�†�ë^eth-default-pins=pins-txdãMNOPêpins-rxdãQRSTpins-ccãUVWXêpins-mdioãYZùpins-powerã[\pins-resetã]pins-interruptã^ùeth-sleep-pins>pins-txdãMNOPpins-ccãUXWVpins-rxdãQRSTpins-mdioãYZ gpio-keys-pins¾pinsãjùi2c0-pins[pinsã -Ï:èi2c1-pins\pinsã  -Ï:èi2c2-default-pins]pins-busã  -Ï:èi2c3-pins^pinsã-Ï:èi2c4-pins_pinsã-Ï:èi2c6-pinsXpinsã-:èmmc0-default-pinsCpins-clkãzêRfpins-cmd-dat$ã~}|{wvutyùê-epins-rstãxê-emmc0-uhs-pinsDpins-clkãzêRfpins-cmd-dat$ã~}|{wvutyùê-epins-dsãêRfpins-rstãxê-emmc1-default-pinsGpins-clkãoêRfpins-cmd-datãnpqrsùê-emmc1-detect-pinsHpins-insertã�-nor-default-pinsVpins-ck-io ãŽ��êRpins-csãŒê-pcie0-default-pinsRpins-bus ã-pcie1-default-pinsUpins-bus ã-eled-pins¿pins-power-enãkspi0-default-pins4pins-cs-mosi-clk ㄆ… pins-misoã‡Rspi1-default-pins8pins-cs-mosi-clk ㈊‰ pins-misoã‹Ruart0-pins/pins-rxãcù-pins-txãbuart1-pins0pins-rxãgù-pins-txãfpins-rtsãdpins-ctsãeùuart2-pins1pins-rxãDù-pins-txãCpins-rtsãBpins-ctsãAùuart3-pins2pins-rxãù-epins-txãuart4-pins3pins-rxãù-pins-txãsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd2`power-controller!mediatek,mt8195-power-controller+a+power-domain@82+apower-domain@92 ãumfgalt�+apower-domain@102 apower-domain@112 apower-domain@122 apower-domain@132 apower-domain@142apower-domain@152Øã @AKà   uvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18�+apower-domain@1628ãâ$%&'()Duvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5�+apower-domain@172ãáuvppsys1vppsys1-0vppsys1-1�apower-domain@222 ã$uwepsys-0wepsys-1wepsys-2wepsys-3�apower-domain@232ãuvdec0-0�+apower-domain@242ãuvdec1-0�apower-domain@252ã uvdec2-0�apower-domain@262ã! uvenc0-larb�+apower-domain@272ã" uvenc1-larb�apower-domain@182 ãã###&uvdosys1vdosys1-0vdosys1-1vdosys1-2�+apower-domain@192�apower-domain@202�apower-domain@212ãQuhdmi_txapower-domain@282ã$$  uimg-0img-1�+apower-domain@292apower-domain@302ã$%uipeipe-0ipe-1�apower-domain@312(ã&&&&&ucam-0cam-1cam-2cam-3cam-4�+apower-domain@322 apower-domain@332!apower-domain@342"apower-domain@02�apower-domain@12�apower-domain@22apower-domain@32apower-domain@42ã57ucsi_rx_topcsi_rx_top1apower-domain@52ã' uetherapower-domain@62ãXn uadspadsp1+�apower-domain@72 ãg"n2uaudioaudio1audio2audio3�awatchdog@10007000mediatek,mt8195-wdt“2p¤.syscon@1000c000"mediatek,mt8195-apmixedsyssyscon2ÀÖtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timer2p� ã(pwrap@10024000mediatek,mt8195-pwrapsyscon2@±pwrap�óã uspiwrap«$»Ëpmicmediatek,mt6359†^Ò ãÞadcmediatek,mt6359-auxadc÷audio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1 vs1 50!‘ÀHdbuck_vgpu11 vgpu11€07xˆHÈ �dbuck_vmodem vmodem€0Èàx*HÈbuck_vpu vpu€07xˆHÈ �dbuck_vcore vcore€0Ö xˆHÈ �dbuck_vs2 vs2 50jHdbuck_vpa vpa¡ 07±ÐH,buck_vproc2 vproc2€07xLHÈ �dbuck_vproc1 vproc1€07xLHÈ �dbuck_vcore_sshub  vcore_sshub€07buck_vgpu11_sshub  vgpu11_sshub€07ldo_vaud18 vaud18w@0w@Hðldo_vsim1 vsim1ð 0/M`ldo_vibr vibrO€02Z ldo_vrf12 vrf12Èà0Ö dldo_vusb vusb-ÆÀ0-ÆÀHÀdBldo_vsram_proc2  vsram_proc2¡ 0½¶xLHðdldo_vio18 vio18ð 0ýàHÀdldo_vcamio vcamioð 0ýàldo_vcn18 vcn18w@0w@Hðldo_vfe28 vfe28*¹€0*¹€Hxldo_vcn13 vcn13 » 0Ö ldo_vcn33_1_bt  vcn33_1_bt*¹€05gàldo_vcn33_1_wifi  vcn33_1_wifi*¹€05gàldo_vaux18 vaux18w@0w@Hðdldo_vsram_others  vsram_others¡ 0½¶xˆHðdldo_vefuse vefuseð 0„€ldo_vxo22 vxo22w@0!‘Àdldo_vrfck vrfckã`0ð ldo_vrfck_1 vrfckëÀ0jldo_vbif28 vbif28*¹€0*¹€Hðldo_vio28 vio28*¹€02Z dldo_vemc vemc,@ 02Z ldo_vemc_1 vemc&% 02Z Eldo_vcn33_2_bt  vcn33_2_bt*¹€05gàldo_vcn33_2_wifi  vcn33_2_wifi*¹€05gàldo_va12 va12O€0Ö dldo_va09 va09 50O€ldo_vrf18 vrf18ð 0žPldo_vsram_md  vsram_md¡ 0½¶x*Hðdldo_vufs vufsð 0ýàFldo_vm18 vm18ð 0ýàdldo_vbbck vbbckÈà0O€dldo_vsram_proc1  vsram_proc1¡ 0½¶xLHðdldo_vsim2 vsim2ð 0/M`ldo_vsram_others_sshub vsram_others_sshub¡ 0½¶rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi 2p� ±pmifspmimstãE(upmif_sys_ckpmif_tmr_ckspmimst_clk_mux«$»Ë+mt6315@6mediatek,mt6315-regulator2regulatorsvbuck1 Vbcpu“à07Hxj �dmt6315@7mediatek,mt6315-regulator2regulatorsvbuck1 Vgpu ‰h07Hxj �doinfra-iommu@10315000mediatek,mt8195-iommu-infra21PPP�¥Omailbox@10320000mediatek,mt8195-gce22@�â²ã’mailbox@10330000mediatek,mt8195-gce23@�ä²ãpscp@10500000mediatek,mt8195-scp02Prp€±sramcfgl1tcm�Πokay¾)Ìmediatek/mt8195/scp.imgqclock-controller@10720000mediatek,mt8195-scp_adsp2rÖ*dsp@10803000mediatek,mt8195-dsp 2€0„ ±cfgsram,ãXnŠ*#Kuadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_hÚ+èrxtxó,-  disabledmailbox@10816000mediatek,mt8195-adsp-mbox²2�`�¾,mailbox@10817000mediatek,mt8195-adsp-mbox²2�p�¿-mt8195-afe-pcm@10890000mediatek,mt8195-audio2‰úÚ+�6 . audiosys”ãÚÛÜÝßg"#neabcd2*óuclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp  disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart2�� ã ubaudbus okaydefault-/serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart2�Ž ã ubaudbus okaydefault-07serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart2�� ã ubaudbus okaydefault-17serial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart2�Ó ã ubaudbus okaydefault-2serial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart2�Ô ã ubaudbus okaydefault-3serial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart2�Õ ã ubaudbus  disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc2 ãumain÷ okayÀsyscon@11003000"mediatek,mt8195-pericfg_aosyscon20Ö'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+2 �¿ã™uparent-clksel-clkspi-clk okaydefault-4Gtpm@0!infineon,slb9670tcg,tpm_tis-spi2[I thermal-sensor@1100b000mediatek,mt8195-lvts-ap2° �©ã m56$ylvts-calib-data-1lvts-calib-data-2Šºsvs@1100bc00mediatek,mt8195-svs2¼�Çãumainm75(ysvs-calibration-datat-calibration-data svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm2à�ËÚ+ ã*0umainmm  disabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm2ð� ã+Numainmm  disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+2�Àã™3uparent-clksel-clkspi-clk okaydefault-8Gspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+2 �Áã™4uparent-clksel-clkspi-clk  disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+20�Âã™5uparent-clksel-clkspi-clk  disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+2€�Ãã™<uparent-clksel-clkspi-clk  disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+2��Äã™=uparent-clksel-clkspi-clk  disabledspi@1101d000mediatek,mt8195-spi-slave2Ð�ÅãRuspi«»˜  disabledspi@1101e000mediatek,mt8195-spi-slave2à�ÆãSuspi«»˜  disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a2@�Ì«macirq.uaxiapbmac_mainptp_refrmii_internalmac_cg0ã''RST' «RST»ÂÃÄÚ+»Ì9Ü:ï;  okay %rgmii-id.<defaultsleep-=9>Cmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c9162 ã^T'd8€ v]<stmmac-axi-config‚’¢9rx-queues-config¬Â:queue0Óæqueue1Óæqueue2Óæqueue3Óætx-queues-configþ;queue0&Ó2queue1&Ó2queue2&Ó2queue3&Ó2usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 2 -ÿ > ±macippcL ?+�€ã/íBusys_ckref_ckmcu_ck@?@E SAg okayjhostrBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci2±mac��«,-»––$ã/íB$usys_ckref_ckmcu_ckdma_ckxhci_ck okaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc 2#õ�ƒãusourcehclksource_cg okaydefaultstate_uhs-C9D€_ ëŠL™«¼ËÚâèöE Fmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc 2$Ç�‡ã$usourcehclksource_cg«»¿ okaydefaultstate_uhs-GH9G �€_ ë  ) 6 DöI Jmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc 2%æ�ˆã Iusourcehclksource_cg« »¿  disabledufshci@11270000mediatek,mt8195-ufshci2'#�‰@K@ã?@A678Z]Xuufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@ K Y  disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu2'€�ªã m56$ylvts-calib-data-1lvts-calib-data-2бusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci 2))> ±macippc�@L«./»––$ã'ï'$usys_ckref_ckmcu_ckdma_ckxhci_ck SAhE okayrB rusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 2*-ÿ*> ±macippcL*?+�«0»–ã'ñ'usys_ckref_ckmcu_ck@ME SAi okayrBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci2±mac�«1»–ã'usys_ck okayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 2+-ÿ+> ±macippcL+?+�«2»–ã'ó' usys_ckref_ckmcu_ck@NE SAj okayrBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci2±mac�«3»–ã' usys_ck okaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie&pci+2/@ ±pcie-mac� ‡ÿ8L� ‚ à ‘O ›0ãV#&+K'/upl_250mtl_26mtl_96mtl_32kperi_26mperi_mem«G»@P ªpcie-phyÚ+^ ´` ÇQQQQ okaydefault-Rinterrupt-controller†^Qpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie&pci+2/€@ ±pcie-mac� ‡ÿ8L�$$ ‚$ $ à ‘O ›(ãWXQ'/upl_250mtl_26mtl_96mtl_32kperi_26mperi_mem«H»@S ªpcie-phyÚ+^ ´` ÇTTTT okaydefault-Uinterrupt-controller†^Tspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor22À�9ão'' uspisfaxi+ okaydefault-Vflash@0jedec,spi-nor2[u Õ æefuse@11c10000%mediatek,mt8195-efusemediatek,efuse2Á+usb3-tx-imp@184,12„ ÷eusb3-rx-imp@184,22„ ÷dusb3-intr@1852… ÷cusb3-tx-imp@186,12† ÷busb3-rx-imp@186,22† ÷ausb3-intr@1872‡ ÷`usb2-intr-p0@188,12ˆ ÷usb2-intr-p1@188,22ˆ ÷usb2-intr-p2@189,12‰ ÷usb2-intr-p3@189,22‰ ÷pciephy-rx-ln1@190,12� ÷lpciephy-tx-ln1-nmos@190,22� ÷kpciephy-tx-ln1-pmos@191,12‘ ÷jpciephy-rx-ln0@191,22‘ ÷ipciephy-tx-ln0-nmos@192,12’ ÷hpciephy-tx-ln0-pmos@192,22’ ÷gpciephy-glb-intr@1932“ ÷fdp-data@1ac2¬°lvts1-calib@1bc2¼5lvts2-calib@1d02Ð86svs-calib@5802€d7socinfo-data1@7a02 t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+LÄ okayusb-phy@02ãòuref üMt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+LÅ okayusb-phy@02ãôuref üNdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx2Èã ÿmipi_tx0_pllÖ ü  disabledŸdsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx2Éã ÿmipi_tx1_pllÖ ü  disabled i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2Ð"€€�šêãW; umaindma+  disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2Ð"€�›êãW; umaindma+ okayX€-Xdefaultpmic@34mediatek,mt636024† ãe«IRQB^regulatormediatek,mt6360-regulator Y Y 'Ybuck1  emi_vdd2 'À0w@ �dbuck2  emi_vddq“à0Ö  �dldo1  mt6360_ldo1O€06î€�ldo2  panel1_p1v8w@0w@�ldo3 vmc_pmuw@02Z �Jldo5  vmch_pmu2Z 02Z �Ildo6  mt6360_ldo6¡ 0 �ldo7  emi_vmddr_enw@0w@�di2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2Ð "€€�œêãW; umaindma+  disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s2Ð0ÖWhdmi-phy@11d5f000mediatek,mt8195-hdmi-phy2Õð ãP  upll_ref26mpll1pll2 ÿhdmi_txpllÖ ü 7  F  disabled¯i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2à"€€��êãZ; umaindma+ okaydefault-[X† i2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2à"€�“êãZ; umaindma+ okaydefault-\X† i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2à "€€�–êãZ; umaindma+ okaydefault-]X€i2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2à0"€€�˜êãZ; umaindma+ okaydefault-^X† i2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2à@"€�™êãZ; umaindma+ okayX† -_defaultclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w2àPÖZt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+LãÚ+ okayusb-phy@02 ãð urefda_ref üLusb-phy@7002ãð urefda_ref m`abyintrrx_imptx_imp üSt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Lä okayusb-phy@02 ãî urefda_ref ü?usb-phy@7002ãî urefda_ref mcdeyintrrx_imptx_imp ü@phy@11e80000mediatek,mt8195-pcie-phy2è±sifmfghijklGyglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1Ú+ ü okayPufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy2úÀã uunipromp ü  disabledKgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm2@ãm0��Œ‹ «jobmmugpu Xn(Ú+ + + + + lcore0core1core2core3core4 okay oclock-controller@13fbf000mediatek,mt8195-mfgcfg2ûðÖmsyscon@14000000mediatek,mt8195-vppsys0syscon2Ö ‹pdma-controller@14001000mediatek,mt8195-mdp3-rdma2 ‹p £  ·qÚ+ Är€ã<óp p ppp Ëdisplay@14002000mediatek,mt8195-mdp3-fg2  ‹p ãdisplay@14003000mediatek,mt8195-mdp3-stitch20 ‹p0ãdisplay@14004000mediatek,mt8195-mdp3-hdr2@ ‹p@ã"display@14005000mediatek,mt8195-mdp3-aal2P�F ‹pPã Ú+display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2` ‹p` £%ã display@14007000mediatek,mt8195-mdp3-tdshp2p ‹ppã#display@14008000mediatek,mt8195-mdp3-color2€�I ‹p€ã$Ú+display@14009000mediatek,mt8195-mdp3-ovl2��J ‹p�ã%Ú+ Är‚display@1400a000mediatek,mt8195-mdp3-padding2  ‹p ãÚ+display@1400b000mediatek,mt8195-mdp3-tcc2° ‹p°ãdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot2À ‹pÀ £ +ã ÄrƒÚ+ Ëmutex@1400f000mediatek,mt8195-vpp-mutex2ð�P ‹pðãÚ+smi@14010000mediatek,mt8195-smi-sub-common2ãuapbsmigals0 ÖsÚ+tsmi@14011000mediatek,mt8195-smi-sub-common2ãuapbsmigals0 ÖsÚ+‘smi@14012000mediatek,mt8195-smi-common-vpp2  ãuapbsmigals0gals1Ú+slarb@14013000mediatek,mt8195-smi-larb20 ã ÖtãuapbsmiÚ+wiommu@14018000mediatek,mt8195-iommu-vpp2€8 ôuvwxyz{|}~€�‚�Rãubclk¥Ú+rclock-controller@14e00000mediatek,mt8195-wpesys2àÖclock-controller@14e02000mediatek,mt8195-wpesys_vpp02à Öclock-controller@14e03000mediatek,mt8195-wpesys_vpp12à0Ölarb@14e04000mediatek,mt8195-smi-larb2à@ ã ÖƒãuapbsmiÚ+¤larb@14e05000mediatek,mt8195-smi-larb2àP ã Ösã uapbsmigalsÚ+ysyscon@14f00000mediatek,mt8195-vppsys1syscon2ðÖ ‹p mutex@14f01000mediatek,mt8195-vpp-mutex2ð�{ ‹p ã'Ú+larb@14f02000mediatek,mt8195-smi-larb2ð  ã Öƒã uapbsmigalsÚ+£larb@14f03000mediatek,mt8195-smi-larb2ð0 ã Ötã uapbsmigalsÚ+xdisplay@14f06000mediatek,mt8195-mdp3-split2ð` ‹p `ã+,Ú+display@14f07000mediatek,mt8195-mdp3-tcc2ðp ‹p pãdma-controller@14f08000mediatek,mt8195-mdp3-rdma2ð€ ‹p € £„¨ã Ä„ Ú+ Ëdma-controller@14f09000mediatek,mt8195-mdp3-rdma2ð� ‹p � £…©ã  Ä„¤Ú+ Ëdma-controller@14f0a000mediatek,mt8195-mdp3-rdma2ð  ‹p   £†ªã  ÄrÀÚ+ Ëdisplay@14f0b000mediatek,mt8195-mdp3-fg2ð° ‹p °ã display@14f0c000mediatek,mt8195-mdp3-fg2ðÀ ‹p Àã display@14f0d000mediatek,mt8195-mdp3-fg2ðÐ ‹p Ðã display@14f0e000mediatek,mt8195-mdp3-hdr2ðà ‹p àãdisplay@14f0f000mediatek,mt8195-mdp3-hdr2ðð ‹p ðãdisplay@14f10000mediatek,mt8195-mdp3-hdr2ñ ‹p ã display@14f11000mediatek,mt8195-mdp3-aal2ñ�i ‹p ãÚ+display@14f12000mediatek,mt8195-mdp3-aal2ñ �j ‹p ãÚ+display@14f13000mediatek,mt8195-mdp3-aal2ñ0�k ‹p 0ã!Ú+display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2ñ@ ‹p @ £�¯ãdisplay@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2ñP ‹p P £‘°ã$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2ñ` ‹p ` £’±ã%display@14f17000mediatek,mt8195-mdp3-tdshp2ñp ‹p pãdisplay@14f18000mediatek,mt8195-mdp3-tdshp2ñ€ ‹p €ã(display@14f19000mediatek,mt8195-mdp3-tdshp2ñ� ‹p �ã)display@14f1a000mediatek,mt8195-mdp3-merge2ñ  ‹p  ãÚ+display@14f1b000mediatek,mt8195-mdp3-merge2ñ° ‹p °ãÚ+display@14f1c000mediatek,mt8195-mdp3-color2ñÀ�t ‹p ÀãÚ+display@14f1d000mediatek,mt8195-mdp3-color2ñÐ ‹p Ð�uãÚ+display@14f1e000mediatek,mt8195-mdp3-color2ñà�v ‹p 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Ö…ã$†uapbsmiÚ+¦clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr2Öclock-controller@15220000mediatek,mt8195-imgsys1_wpe2"Ö‡larb@15230000mediatek,mt8195-smi-larb2# ã  Ö…ã$‡uapbsmiÚ+§clock-controller@15330000mediatek,mt8195-ipesys23Ö%larb@15340000mediatek,mt8195-smi-larb24 ã  Öˆã%%uapbsmiÚ+zclock-controller@16000000mediatek,mt8195-camsys2Ö&larb@16001000mediatek,mt8195-smi-larb2 ã  Ö‰ã&&& uapbsmigalsÚ+¨larb@16002000mediatek,mt8195-smi-larb2  ã ÖŠã&&uapbsmiÚ+{smi@16004000mediatek,mt8195-smi-sub-common2@ã&&&uapbsmigals0 ÖƒÚ+‰smi@16005000mediatek,mt8195-smi-sub-common2Pã&&uapbsmigals0 ÖsÚ+Šlarb@16012000mediatek,mt8195-smi-larb2  ã ÖŠã‹‹uapbsmiÚ+ |larb@16013000mediatek,mt8195-smi-larb20 ã Ö‰㌌uapbsmiÚ+ ©larb@16014000mediatek,mt8195-smi-larb2@ ã ÖŠã��uapbsmiÚ+!‚larb@16015000mediatek,mt8195-smi-larb2P ã Ö‰㎎uapbsmiÚ+!®clock-controller@1604f000mediatek,mt8195-camsys_rawa2ðÖ‹clock-controller@1606f000mediatek,mt8195-camsys_yuva2ðÖŒclock-controller@1608f000mediatek,mt8195-camsys_rawb2ðÖ�clock-controller@160af000mediatek,mt8195-camsys_yuvb2 ðÖŽclock-controller@16140000mediatek,mt8195-camsys_mraw2Ö�larb@16141000mediatek,mt8195-smi-larb2 ã Ö‰ã&�& uapbsmigalsÚ+"­larb@16142000mediatek,mt8195-smi-larb2  ã ÖŠã��uapbsmiÚ+"�clock-controller@17200000mediatek,mt8195-ccusys2 Ö�larb@17201000mediatek,mt8195-smi-larb2  ã ÖŠã��uapbsmiÚ+}video-codec@18000000mediatek,mt8195-vcodec-dec ·q Ä„ + 2@L`video-codec@2000mediatek,mtk-vcodec-lat-soc2  Äràrá ãA�uselvdeclattop«A»�Ú+video-codec@10000mediatek,mtk-vcodec-lat2�Ä0 Ä„„„„„„ ãA�uselvdeclattop«A»�Ú+video-codec@25000mediatek,mtk-vcodec-core2P�ÃP Ä„ „¡„¢„£„¤„¥„¦„§„¨„© ãA�uselvdeclattop«A»�Ú+larb@1800d000mediatek,mt8195-smi-larb2Ð ã ÖƒãuapbsmiÚ+¬larb@1800e000mediatek,mt8195-smi-larb2à ã Ö‘ãuapbsmiÚ+€clock-controller@1800f000mediatek,mt8195-vdecsys_soc2ðÖlarb@1802e000mediatek,mt8195-smi-larb2à ã ÖƒãuapbsmiÚ+«clock-controller@1802f000mediatek,mt8195-vdecsys2ðÖlarb@1803e000mediatek,mt8195-smi-larb2à ã Ö‘ã uapbsmiÚ+clock-controller@1803f000mediatek,mt8195-vdecsys_core12ðÖ clock-controller@190f3000mediatek,mt8195-apusys_pll20Öclock-controller@1a000000mediatek,mt8195-vencsys2Ö!larb@1a010000mediatek,mt8195-smi-larb2 ã Öƒã!!uapbsmiÚ+ªvideo-codec@1a020000mediatek,mt8195-vcodec-enc2H Ä„`„a„b„c„d„v„w„x„y�U ·qã! uvenc_sel«@»�Ú++jpeg-decoder@1a040000mediatek,mt8195-jpgdecÚ+0 Ä„m„n„r„s„t„u+0Ljpgdec@0,0mediatek,mt8195-jpgdec-hw20 Ä„m„n„r„s„t„u�Wã!ujpgdecÚ+jpgdec@0,10000mediatek,mt8195-jpgdec-hw20 Ä„m„n„r„s„t„u�Xã!ujpgdecÚ+jpgdec@1,0mediatek,mt8195-jpgdec-hw20 Är�rŽr’r“r”r•�\ã"ujpgdecÚ+clock-controller@1b000000mediatek,mt8195-vencsys_core12Ö"syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon2  ó’Ö ‹’ jpeg-encoder@1a030000mediatek,mt8195-jpgencÚ+ Är‡rˆr‰rŒ+0Ljpgenc@0,0mediatek,mt8195-jpgenc-hw2 Ä„g„h„i„l�Vã!ujpgencÚ+jpgenc@1,0mediatek,mt8195-jpgenc-hw2 Är‡rˆr‰rŒ�[ã"ujpgencÚ+larb@1b010000mediatek,mt8195-smi-larb2 ã Ösã""  uapbsmigalsÚ+~ovl@1c000000mediatek,mt8195-disp-ovl2�|Ú+ã Ä„ ‹’ports+port@02endpointport@12endpoint “”rdma@1c002000mediatek,mt8195-disp-rdma2 �~Ú+ã Ä„ ‹’ ports+port@02endpoint ”“port@12endpoint •–color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color20�Ú+ã ‹’0ports+port@02endpoint –•port@12endpoint —˜ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr2@�€Ú+ã ‹’@ports+port@02endpoint ˜—port@12endpoint ™šaal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal2P��Ú+ã ‹’Pports+port@02endpoint š™port@12endpoint ›œgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma2`�‚Ú+ã ‹’`ports+port@02endpoint œ›port@12endpoint �ždither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither2p�ƒÚ+ã  ‹’pports+port@02endpoint ž�port@12endpointdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi2€�„Ú+ã*Ÿuenginedigitalhs@Ÿ ªdphy  disableddsc@1c009000mediatek,mt8195-disp-dsc2��…Ú+ã ‹’�dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi2 �ŽÚ+ã+ uenginedigitalhs@  ªdphy  disabledmerge@1c014000mediatek,mt8195-disp-merge2@��Ú+ã ‹’@dp-intf@1c015000mediatek,mt8195-dp-intf2P�‘Ú+ã,upixelenginepll  disabledmutex@1c016000mediatek,mt8195-disp-mutex2`�’Ú+ã ‹’` £Ularb@1c018000mediatek,mt8195-smi-larb2€ ã Öƒã((  uapbsmigalsÚ+¡larb@1c019000mediatek,mt8195-smi-larb2� ã Ösã(  uapbsmigalsÚ+usyscon@1c100000mediatek,mt8195-vdosys1syscon2 ó’ ‹’Ö¤#smi@1c01b000mediatek,mt8195-smi-common-vdo2° ã%&)$uapbsmigals0gals1Ú+ƒiommu@1c01f000mediatek,mt8195-iommu-vdo2ð8 ô¡¢£¤¥¦§¨©ª«¬­®��¥ã'ubclkÚ+„mutex@1c101000mediatek,mt8195-disp-mutex2�îÚ+ã# ‹’ £Àlarb@1c102000mediatek,mt8195-smi-larb2  ã Öƒã### uapbsmigalsÚ+¢larb@1c103000mediatek,mt8195-smi-larb20 ã Ösã##  uapbsmigalsÚ+vdma-controller@1c104000mediatek,mt8195-vdo1-rdma2@�ïã#Ú+ Ä„@ ‹’@ Ëdma-controller@1c105000mediatek,mt8195-vdo1-rdma2P�ðã#Ú+ Är` ‹’P Ëdma-controller@1c106000mediatek,mt8195-vdo1-rdma2`�ñã#Ú+ Ä„A ‹’` Ëdma-controller@1c107000mediatek,mt8195-vdo1-rdma2p�òã#Ú+ Ära ‹’p Ëdma-controller@1c108000mediatek,mt8195-vdo1-rdma2€�óã#Ú+ Ä„B ‹’€ Ëdma-controller@1c109000mediatek,mt8195-vdo1-rdma2��ôã#Ú+ Ärb ‹’� Ëdma-controller@1c10a000mediatek,mt8195-vdo1-rdma2 �õã#Ú+ Ä„C ‹’  Ëdma-controller@1c10b000mediatek,mt8195-vdo1-rdma2°�öã#Ú+ Ärc ‹’° Ëvpp-merge@1c10c000mediatek,mt8195-disp-merge2À�÷ã# #umergemerge_asyncÚ+ ‹’À  #vpp-merge@1c10d000mediatek,mt8195-disp-merge2Ð�øã# #umergemerge_asyncÚ+ ‹’Ð  #vpp-merge@1c10e000mediatek,mt8195-disp-merge2à�ùã# #umergemerge_asyncÚ+ ‹’à  #vpp-merge@1c10f000mediatek,mt8195-disp-merge2ð�úã# #umergemerge_asyncÚ+ ‹’ð  #vpp-merge@1c110000mediatek,mt8195-disp-merge2�ûã# #umergemerge_asyncÚ+ ‹’ ' #dpi@1c112000mediatek,mt8195-dpi2 ã#-##2upixelenginepll�Ú+ #  disabledports+port@02endpointport@12endpointdp-intf@1c113000mediatek,mt8195-dp-intf20�Ú+ã#/#upixelenginepll  disabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp2@Pp� °À4±mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp ‹’@’P’p’�’ ’°’Àhã#%# ###!#$#"#1#&#'#(#)#*ƒumixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_topÚ+ Ärdre�( #3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asynchdmi-tx@1c300000mediatek,mt8195-hdmi-txÒ20 ãQLM,ubushdcphdcp24mhdmi-split«L»“�¥Ú+@¯ ªhdmi  disabledi2cmediatek,mt8195-hdmi-ddcãports+port@02endpointport@12endpointedp-tx@1c500000mediatek,mt8195-edp-tx2P€m°ydp_calibration_dataÚ+�¤ >¤  disableddp-tx@1c600000mediatek,mt8195-dp-tx2`€m°ydp_calibration_dataÚ+�Ê >¤  disabledthermal-zonescpu0-thermal Oè ]ú s±tripstrip-alert ƒL �Ð-passive²trip-crit ƒ†  �Ð -criticalcooling-mapsmap0 š²0 Ÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu1-thermal Oè ]ú s±tripstrip-alert ƒL �Ð-passive³trip-crit ƒ†  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compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7mmc0mmc1serial0serial1serial2serial3serial4device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxdrive-strengthinput-enableoutput-highinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsmemory-regionfirmware-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0uart-has-rtsctsmediatek,pad-selectspi-max-frequencynvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplybus-widthhs400-ds-delaycap-mmc-highspeedcap-mmc-hw-resetmmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplycd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcfreq-table-hzmediatek,ufs-disable-mcqmediatek,u3p-dis-mskbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsLDO_VIN1-supplyLDO_VIN2-supplyLDO_VIN3-supplymediatek,ibiasmediatek,ibias_upoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathlabellinux,codedebounce-intervaldefault-statefunctioncolorregulator-boot-onno-mapio-channelsio-channel-namestemperature-lookup-table