Ð þíw8i( ñhÜ4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000€/soc/vpp-merge@1c10d000‡/soc/vpp-merge@1c10e000Ž/soc/vpp-merge@1c10f000•/soc/vpp-merge@1c110000œ/soc/dma-controller@1c104000§/soc/dma-controller@1c105000²/soc/dma-controller@1c106000½/soc/dma-controller@1c107000È/soc/dma-controller@1c108000Ó/soc/dma-controller@1c109000Þ/soc/dma-controller@1c10a000é/soc/dma-controller@1c10b000ô/soc/serial@11001100ü/soc/ethernet@11021000cpus+cpu@0cpuarm,cortex-a55psci$8ec3@H4[k€x@Š€—€¤@¶€ÃÔãî cpu@100cpuarm,cortex-a55psci$8ec3@H4[k€x@Š€—€¤@¶€ÃÔãî cpu@200cpuarm,cortex-a55psci$8ec3@H4[k€x@Š€—€¤@¶€ÃÔãî cpu@300cpuarm,cortex-a55psci$8ec3@H4[k€x@Š€—€¤@¶€ÃÔãîcpu@400cpuarm,cortex-a78psci$8�fÔÀH[kx@Š—¤@¶à Ôã îcpu@500cpuarm,cortex-a78psci$8�fÔÀH[kx@Š—¤@¶à Ôã îcpu@600cpuarm,cortex-a78psci$8�fÔÀH[kx@Š—¤@¶à Ôã îcpu@700cpuarm,cortex-a78psci$8�fÔÀH[kx@Š—¤@¶à Ôã îcpu-mapcluster0core0ö core1ö core2ö core3öcore4öcore5öcore6öcore7öidle-statesúpscicpu-retention-larm,idle-state/2@_PDîcpu-retention-barm,idle-state/-@ŒPäîcpu-off-larm,idle-state/7@›PHîcpu-off-barm,idle-state/2@ÈPèîl2-cache0cacheamz@ŒÃmîl2-cache1cacheamz@ŒÃmî l3-cachecacheam z@Œmîdsu-pmu arm,dsu-pmu{ † ‹faildmic-codec dmic-codec’ŸÈmt8195-sound¯‹okaymediatek,mt8195_mt6359 7mt8395-evkÁdefaultÏ,ÙHeadphoneHeadphone LHeadphoneHeadphone Rçheadphone-dai-link õDL_SRC_BEcodecÿhdmi-dai-link õETDM3_OUT_BEcodecÿfixed-factor-clock-13mfixed-factor-clock '2clk13mî0oscillator-26m fixed-clock 8Œº€2clk26mîoscillator-32k fixed-clock 8€2clk32kperformance-controller@11bc10mediatek,cpufreq-hw ¼ ½0 Eîopp-table-gpuoperating-points-v2_îƒopp-390000000j>í€q ‰hopp-410000000jp€q ¡Òopp-431000000j°‰Àq ¡Òopp-473000000j1h@q º<opp-515000000j²FÀq º<opp-556000000j!#ãq Ò¦opp-598000000j#¤Á€q ëopp-640000000j&% q ëopp-670000000j'ïc€q äopp-700000000j)¹'q L¸opp-730000000j+‚ê€q }Œopp-760000000j-L®q ®`opp-790000000j/q€q ß4opp-820000000j0à5q opp-850000000j2©ø€q @Üopp-880000000j4s¼q q°pmu-a55arm,cortex-a55-pmu {pmu-a78arm,cortex-a78-pmu {psci arm,psci-1.0smctimerarm,armv8-timer @{   soc+ simple-bus†interrupt-controller@c000000 arm,gic-v3‘¢ ¹    { îppi-partitionsinterrupt-partition-0Î îinterrupt-partition-1Îîsyscon@10000000 mediatek,mt8195-topckgensyscon îsyscon@10001000#mediatek,mt8195-infracfg_aosyscon ×î syscon@10003000mediatek,mt8195-pericfgsyscon0 îLpinctrl@10005000mediatek,mt8195-pinctrl€PÑÓÔâëô°Bäiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintîþ �¹{ë‘îaudio-default-pinsîpins-cmd-dat4=>ABCDEFGHIJKdisp-pwm1-default-pinspins1hedp-panel-12v-en-pinsîèpins1`edp-panel-3v3-en-pinsîçpins1eth-default-pinsîHpins-ccUVWX)pins-mdioYZ8pins-power[\pins-rxdQRSTpins-txdMNOP)eth-sleep-pinsîIpins-ccUVWXpins-mdioYZESpins-rxdQRSTpins-txdMNOPgpio-keys-pinspinsj`8hdmi-vreg-pinsîlpins-pwrShdmi-pinsîÕpins-hotplug mpins-ddc"#) pins-cec!Si2c0-pinsînpins `Ï|èi2c1-pinsîopins  `Ï|èi2c2-pinsîrpins  `Ï)i2c6-pinsîfpins`mmc0-default-pinsîQpins-clkz)mfpins-cmd-dat$~}|{wvuty8)`epins-rstx)`emmc0-uhs-pinsîRpins-clkz)mfpins-cmd-dat$~}|{wvuty8)`epins-ds)mfpins-rstx)`emmc1-default-pinsîUpins-clko)mfpins-cmd-datnpqrs8)`emmc1-uhs-pinsîVpins-clko)mfpins-cmd-datnpqrs8)`emt6360-pinsîgpins€8`dsi0-vreg-en-pinsîépins-pwr-en/”panel-default-pinsîºpins-rstlpins-en0”pcie0-default-pinsîapins `pcie0-idle-pinsîbpinsS”pcie1-default-pinsîdpins `disp-pwm0-pinsî?pins-disp-pwmaspi1-pinsî@pinsˆ‰Š‹Sspi-pinsîCpinsŒ�Ž�Stouch-pinsîqpins-irq„8Spins-reset…u3-p0-vbus-default-pinsîMpins-vbus?8uart0-pinsî:pinsbcuart1-pinsî;pinsdefgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+Ÿî3power-domain@8+Ÿ³power-domain@9 ÁmfgaltÍ +Ÿ³!power-domain@10 Ÿpower-domain@11 Ÿpower-domain@12 Ÿpower-domain@13 Ÿpower-domain@14Ÿpower-domain@15Ø @AKà" " """"""""""""""""" Ávppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18Í +Ÿpower-domain@168â#$#%#&#'#(#)DÁvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5Í +Ÿpower-domain@17á$$Ávppsys1vppsys1-0vppsys1-1Í Ÿpower-domain@22 %%%%$Áwepsys-0wepsys-1wepsys-2wepsys-3Í Ÿpower-domain@23&Ávdec0-0Í +Ÿpower-domain@24'Ávdec1-0Í Ÿpower-domain@25(Ávdec2-0Í Ÿpower-domain@26) Ávenc0-larbÍ +Ÿpower-domain@27* Ávenc1-larbÍ Ÿpower-domain@18 ã+++&Ávdosys1vdosys1-0vdosys1-1vdosys1-2Í +Ÿpower-domain@19Í Ÿpower-domain@20Í Ÿpower-domain@21QÁhdmi_txŸpower-domain@28,,  Áimg-0img-1Í +Ÿpower-domain@29Ÿpower-domain@30,-Áipeipe-0ipe-1Í Ÿpower-domain@31(.....Ácam-0cam-1cam-2cam-3cam-4Í +Ÿpower-domain@32 Ÿpower-domain@33!Ÿpower-domain@34"Ÿpower-domain@0Í Ÿpower-domain@1Í Ÿpower-domain@2Ÿpower-domain@3Ÿpower-domain@457Ácsi_rx_topcsi_rx_top1Ÿpower-domain@5/ ÁetherŸpower-domain@6Xn Áadspadsp1+Í Ÿpower-domain@7 g"n 2Áaudioaudio1audio2audio3Í Ÿwatchdog@10007000mediatek,mt8195-wdtßp×î8syscon@1000c000"mediatek,mt8195-apmixedsyssysconÀ îtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerp{ 0pwrap@10024000mediatek,mt8195-pwrapsyscon@äpwrap{ó   Áspiwrap÷$Ëpmicmediatek,mt6359¹‘ /Þîadcmediatek,mt6359-auxadcCaudio-codecmediatek,mt6359-codecUi}regulatorsmediatek,mt6359-regulatorbuck_vs1‘vs1  5¸!‘ÀÐìbuck_vgpu11‘vgpu11 €¸7ˆÐÈ ìbuck_vmodem‘vmodem €¸Èà*ÐÈbuck_vpu‘vpu €¸7ˆÐÈ ìbuck_vcore‘vcore €¸Ö ˆÐÈ ìîbuck_vs2‘vs2  5¸jÐìbuck_vpa‘vpa ¡ ¸7±ÐÐ,buck_vproc2‘vproc2 €¸7LÐÈ buck_vproc1‘vproc1 €¸7LÐÈ buck_vcore_sshub ‘vcore_sshub €¸7buck_vgpu11_sshub ‘vgpu11_sshub €¸7ldo_vaud18‘vaud18 w@¸w@Ððìldo_vsim1‘vsim1 ð ¸/M`ldo_vibr‘vibr O€¸2Z îsldo_vrf12‘vrf12 Èà¸Ö ìldo_vusb‘vusb -ÆÀ¸-ÆÀÐÀìîNldo_vsram_proc2 ‘vsram_proc2 ¡ ¸½¶LÐðìldo_vio18‘vio18 ð ¸ýàÐÀìldo_vcamio‘vcamio ð ¸ýàìldo_vcn18‘vcn18 w@¸w@Ððldo_vfe28‘vfe28 *¹€¸*¹€Ðxldo_vcn13‘vcn13  » ¸Ö ldo_vcn33_1_bt ‘vcn33_1_bt *¹€¸5gàldo_vcn33_1_wifi ‘vcn33_1_wifi *¹€¸5gàldo_vaux18‘vaux18 w@¸w@Ððìldo_vsram_others ‘vsram_others  q°¸ q°ˆÐðî!ldo_vefuse‘vefuse ð ¸„€ldo_vxo22‘vxo22 w@¸!‘Àìldo_vrfck‘vrfck ã`¸ð ldo_vrfck_1‘vrfck ëÀ¸jldo_vbif28‘vbif28 *¹€¸*¹€Ððldo_vio28‘vio28 *¹€¸2Z ìldo_vemc‘vemc ,@ ¸2Z ldo_vemc_1‘vemc &% ¸2Z îSldo_vcn33_2_bt ‘vcn33_2_bt 2Z ¸2Z îBldo_vcn33_2_wifi ‘vcn33_2_wifi *¹€¸5gàldo_va12‘va12 O€¸Ö ìldo_va09‘va09  5¸O€ldo_vrf18‘vrf18 ð ¸žPldo_vsram_md ‘vsram_md ¡ ¸½¶*Ððldo_vufs‘vufs ð ¸ýàîTldo_vm18‘vm18 ð ¸ýàìldo_vbbck‘vbbck Èà¸O€ìldo_vsram_proc1 ‘vsram_proc1 ¡ ¸½¶LÐðìldo_vsim2‘vsim2 ð ¸/M`ldo_vsram_others_sshub‘vsram_others_sshub ¡ ¸½¶rtcmediatek,mt6358-rtckeysmediatek,mt6359-keys-Fpower-keyYthhomeYfspmi@10027000mediatek,mt8195-spmi p� äpmifspmimst  E(Ápmif_sys_ckpmif_tmr_ckspmimst_clk_mux÷$Ë+pmic@6mediatek,mt6315-regulatorregulatorsvbuck1‘Vbcpu “à¸7Ð ìî pmic@7mediatek,mt6315-regulatorregulatorsvbuck1‘Vgpu Tи 8Ð îinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPP{vî^mailbox@10320000mediatek,mt8195-gce2@{⃠î¦mailbox@10330000mediatek,mt8195-gce3@{äƒ î„scp@10500000mediatek,mt8195-scp0Prp€äsramcfgl1tcm{΋okay�1�mediatek/mt8195/scp.imgî…clock-controller@10720000mediatek,mt8195-scp_adspr î2dsp@10803000mediatek,mt8195-dsp €0„ äcfgsram,XnŠ2#KÁadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h«3¹rxtxÄ45‹okay�67îmailbox@10816000mediatek,mt8195-adsp-mboxƒ�`{¾î4mailbox@10817000mediatek,mt8195-adsp-mboxƒ�p{¿î5mt8195-afe-pcm@10890000mediatek,mt8195-audio‰Ë«3{6Ý8 äaudiosys”ÚÛÜÝßg"#neabcd 22óÁclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp‹okay�9îserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart{�   Ábaudbus‹okayÏ:Ádefaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart{Ž   Ábaudbus‹okayÏ;Ádefaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart{�   Ábaudbus ‹disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart{Ó   Ábaudbus ‹disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart{Ô   Ábaudbus ‹disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart{Õ   Ábaudbus ‹disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc  ÁmainC ‹disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0 î/spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ {¿™ Áparent-clksel-clkspi-clk ‹disabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap° {© Ý ð<=$ülvts-calib-data-1lvts-calib-data-2 îâsvs@1100bc00mediatek,mt8195-svs¼{Ç Ámainð><(üsvs-calibration-datat-calibration-dataÝ äsvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmà{Ë«3#* 0Ámainmm‹okayÁdefaultÏ?îåpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmð{#+ NÁmainmm ‹disabledîæspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+{À™ 3Áparent-clksel-clkspi-clk‹okayÏ@Ádefault. B@can@0microchip,mcp2518fdAK1- /]BhBspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ {Á™ 4Áparent-clksel-clkspi-clk‹okayÏCÁdefault.spi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0{™ 5Áparent-clksel-clkspi-clk ‹disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+€{Ù <Áparent-clksel-clkspi-clk ‹disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+�{Ä™ =Áparent-clksel-clkspi-clk ‹disabledspi@1101d000mediatek,mt8195-spi-slaveÐ{Å RÁspi÷˜ ‹disabledspi@1101e000mediatek,mt8195-spi-slaveà{Æ SÁspi÷˜ ‹disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@{Ìwmacirq.Áaxiapbmac_mainptp_refrmii_internalmac_cg0//RST/ ÷RSTÂÃÄ«3‡ ˜D¨E»FÎÙä‹okay ñrgmii-rxidúG ] ''*î?ÁdefaultsleepÏHPImdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916îGstmmac-axi-configZjzîDrx-queues-config„šîEqueue0«¾queue1«¾queue2«¾queue3«¾tx-queues-configÖìîFqueue0þ« queue1þ« queue2þ« queue3þ« usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  -ÿ > ämacippc ?+{€ /í BÁsys_ckref_ckmcu_ck JKh Lg‹okay 4otgÁdefaultÏM < LNusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciämac{�÷,-––$ /í B$Ásys_ckref_ckmcu_ckdma_ckxhci_ck‹okayports+port@0endpoint ZOîiport@1endpoint ZPîjmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #õ{ƒ  Ásourcehclksource_cg‹okayÁdefaultstate_uhsÏQPR jO ë t † • ¤ µ ½ ÃL ÒS ÞT ëmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $Ç{‡  $Ásourcehclksource_cg÷¿‹okayÁdefaultstate_uhsÏUPV jO ë ù   % µ ÒW ÞX ëmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %æ{ˆ  IÁsourcehclksource_cg÷ ¿ ‹disabledufshci@11270000mediatek,mt8195-ufshci'#{‰ Y@ ? @ A 6 7 8 Z ]XÁufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@ , : ‹disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'€{ª Ý ð<=$ülvts-calib-data-1lvts-calib-data-2 îÙusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> ämacippc{ Z[÷./––$/ï/$Ásys_ckref_ckmcu_ckdma_ckxhci_ck Lhh‹okay LNusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-ÿ*> ämacippc*?+{÷0–/ñ/Ásys_ckref_ckmcu_ck \h Li‹okay LNusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciämac{÷1–/Ásys_ck‹okayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-ÿ+> ämacippc+?+{÷2–/ó/ Ásys_ckref_ckmcu_ck ]h Lj‹okay LNusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciämac{÷3–/ Ásys_ck‹okaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ äpcie-mac{ Sÿ8� ‚ à ]^ g0 V # & + K//Ápl_250mtl_26mtl_96mtl_32kperi_26mperi_mem÷G _ vpcie-phy«3‘ €` “````‹okay ÁdefaultidleÏaPbinterrupt-controller¹‘î`pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/€@ äpcie-mac{ Sÿ8�$$ ‚$ $ à ]^ g( W X Q//Ápl_250mtl_26mtl_96mtl_32kperi_26mperi_mem÷H [ vpcie-phy«3‘ €` “cccc ‹disabledÁdefaultÏdinterrupt-controller¹‘îcspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2À{9o// Áspisfaxi+ ‹disabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuseÁ+usb3-tx-imp@184,1„ ¡îzusb3-rx-imp@184,2„ ¡îyusb3-intr@185… ¡îxusb3-tx-imp@186,1† ¡îwusb3-rx-imp@186,2† ¡îvusb3-intr@187‡ ¡îuusb2-intr-p0@188,1ˆ ¡usb2-intr-p1@188,2ˆ ¡usb2-intr-p2@189,1‰ ¡usb2-intr-p3@189,2‰ ¡pciephy-rx-ln1@190,1� ¡î�pciephy-tx-ln1-nmos@190,2� ¡î€pciephy-tx-ln1-pmos@191,1‘ ¡îpciephy-rx-ln0@191,2‘ ¡î~pciephy-tx-ln0-nmos@192,1’ ¡î}pciephy-tx-ln0-pmos@192,2’ ¡î|pciephy-glb-intr@193“ ¡î{dp-data@1ac¬îØlvts1-calib@1bc¼î<lvts2-calib@1d0Ð8î=svs-calib@580€dî>socinfo-data1@7a0 t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Ä‹okayusb-phy@0òÁref ¦î\t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Å‹okayusb-phy@0ôÁref ¦î]dsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txÈ 2mipi_tx0_pll  ¦‹okayî¶dsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txÉ 2mipi_tx1_pll  ¦ ‹disabledî¾i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€€{še ; Ámaindma+ ‹disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€{›e ; Ámaindma+‹okay8€ÏfÁdefaultpmic@34mediatek,mt63604 {€wIRQB¹‘Ïgchargermediatek,mt6360-chg ±Ý@ usb-otg-vbus-regulator ‘usb-otg-vbus C…(¸Xáèregulatormediatek,mt6360-regulator Êhbuck1 ‘emi_vdd2 “à¸Ö  ìbuck2 ‘emi_vddq “à¸Ö  ìîhldo1 ‘tp1_p3v0 2Z ¸2Z ìîpldo2 ‘panel1_p1v8 w@¸w@îêldo3‘vmc_pmu O€¸6î€îXldo5 ‘vmch_pmu )2à¸6î€îWldo6 ‘mt6360_ldo1 ¡ ¸ ldo7 ‘emi_vmddr_en ¡ ¸ ìtcpcmediatek,mt6360-tcpc /wPD_IRQBconnectorusb-c-connector ÚUSB-C àdual ꘖ€ üdual sink "�d ""�È ,altmodesdisplayport 8ÿ =Fports+port@0endpoint ZiîOport@1endpoint ZjîPport@2endpoint Zkîti2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð "€€{œe ; Ámaindma+ ‹disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_sÐ0 îehdmi-phy@11d5f000mediatek,mt8195-hdmi-phyÕð P   Ápll_ref26mpll1pll2 2hdmi_txpll  ¦ A  P‹okayÁdefaultÏlîÔi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c à"€€{�m ; Ámaindma+‹okay8€ÏnÁdefaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c à"€{“m ; Ámaindma+‹okay8€ÏoÁdefaulttouchscreen@5dgoodix,gt9271] /„ b„ l… xpÁdefaultÏqi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c à "€€{–m ; Ámaindma+‹okay8€ÏrÁdefaulttypec-mux@48 ite,it5205H †s ‘ �‹okayportendpoint Ztîki2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c à0"€€{˜m ; Ámaindma+ ‹disabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c à@"€{™m ; Ámaindma+ ‹disabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wàP îmt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+ã«3‹okayusb-phy@0 ð Árefda_ref ¦îZusb-phy@700ð Árefda_ref ðuvwüintrrx_imptx_imp ¦ °î[t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+ä‹okayusb-phy@0 î Árefda_ref ¦îJusb-phy@700î Árefda_ref ðxyzüintrrx_imptx_imp ¦îKphy@11e80000mediatek,mt8195-pcie-phyèäsifð{|}~€�Güglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1«3 ¦‹okayî_ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphyúÀ Áunipromp ¦ ‹disabledîYgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@‚0{�Œ‹ wjobmmugpu ă(«3 3 3 3 3 Øcore0core1core2core3core4‹okay ëclock-controller@13fbf000mediatek,mt8195-mfgcfgûð î‚syscon@14000000mediatek,mt8195-vppsys0syscon  ÷„î"dma-controller@14001000mediatek,mt8195-mdp3-rdma ÷„   #…«3 0†€"<Ä„ „ „„„ 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`‰Š‹Œ�Ž��‘’“”•–{R"Ábclkv«3î†clock-controller@14e00000mediatek,mt8195-wpesysà î%clock-controller@14e02000mediatek,mt8195-wpesys_vpp0à  clock-controller@14e03000mediatek,mt8195-wpesys_vpp1à0 larb@14e04000mediatek,mt8195-smi-larbà@ O B—%%Áapbsmi«3îÃlarb@14e05000mediatek,mt8195-smi-larbàP O B‡%%" Áapbsmigals«3î�syscon@14f00000mediatek,mt8195-vppsys1sysconð  ÷„ î$mutex@14f01000mediatek,mt8195-vpp-mutexð{{ ÷„ $'«3larb@14f02000mediatek,mt8195-smi-larbð  O B—$$" Áapbsmigals«3îÂlarb@14f03000mediatek,mt8195-smi-larbð0 O Bˆ$$" Áapbsmigals«3îŒdisplay@14f06000mediatek,mt8195-mdp3-splitð` ÷„ `$$+$,«3display@14f07000mediatek,mt8195-mdp3-tccðp ÷„ p$dma-controller@14f08000mediatek,mt8195-mdp3-rdmað€ ÷„ € „¨$ 0˜ «3 7dma-controller@14f09000mediatek,mt8195-mdp3-rdmað� ÷„ � …©$  0˜¤«3 7dma-controller@14f0a000mediatek,mt8195-mdp3-rdmað  ÷„   †ª$  0†À«3 7display@14f0b000mediatek,mt8195-mdp3-fgð° ÷„ °$ display@14f0c000mediatek,mt8195-mdp3-fgðÀ ÷„ À$ display@14f0d000mediatek,mt8195-mdp3-fgðÐ ÷„ Ð$ display@14f0e000mediatek,mt8195-mdp3-hdrðà ÷„ à$display@14f0f000mediatek,mt8195-mdp3-hdrðð ÷„ ð$display@14f10000mediatek,mt8195-mdp3-hdrñ ÷„ $ display@14f11000mediatek,mt8195-mdp3-aalñ{i ÷„ $«3display@14f12000mediatek,mt8195-mdp3-aalñ {j ÷„ $«3display@14f13000mediatek,mt8195-mdp3-aalñ0{k ÷„ 0$!«3display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszñ@ ÷„ @ �¯$display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszñP ÷„ P ‘°$$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszñ` ÷„ ` ’±$%display@14f17000mediatek,mt8195-mdp3-tdshpñp ÷„ p$display@14f18000mediatek,mt8195-mdp3-tdshpñ€ ÷„ €$(display@14f19000mediatek,mt8195-mdp3-tdshpñ� ÷„ �$)display@14f1a000mediatek,mt8195-mdp3-mergeñ  ÷„  $«3display@14f1b000mediatek,mt8195-mdp3-mergeñ° ÷„ °$«3display@14f1c000mediatek,mt8195-mdp3-colorñÀ{t ÷„ À$«3display@14f1d000mediatek,mt8195-mdp3-colorñÐ ÷„ Ð{u$«3display@14f1e000mediatek,mt8195-mdp3-colorñà{v ÷„ à$«3display@14f1f000mediatek,mt8195-mdp3-ovlñð{w ÷„ ð$«3 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î)larb@1a010000mediatek,mt8195-smi-larb O B—))Áapbsmi«3îÉvideo-codec@1a020000mediatek,mt8195-vcodec-encH 0˜`˜a˜b˜c˜d˜v˜w˜x˜y{U #…) Ávenc_sel÷@�«3+jpeg-decoder@1a040000mediatek,mt8195-jpgdec«30 0˜m˜n˜r˜s˜t˜u+0jpgdec@0,0mediatek,mt8195-jpgdec-hw0 0˜m˜n˜r˜s˜t˜u{W)Ájpgdec«3jpgdec@0,10000mediatek,mt8195-jpgdec-hw0 0˜m˜n˜r˜s˜t˜u{X)Ájpgdec«3jpgdec@1,0mediatek,mt8195-jpgdec-hw0 0†�†ކ’†“†”†•{\*Ájpgdec«3clock-controller@1b000000mediatek,mt8195-vencsys_core1 î*syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon  Ħ  ÷¦ î#port+endpoint@0 Z§î¨jpeg-encoder@1a030000mediatek,mt8195-jpgenc«3 0†‡†ˆ†‰†Œ+0jpgenc@0,0mediatek,mt8195-jpgenc-hw 0˜g˜h˜i˜l{V)Ájpgenc«3jpgenc@1,0mediatek,mt8195-jpgenc-hw 0†‡†ˆ†‰†Œ{[*Ájpgenc«3larb@1b010000mediatek,mt8195-smi-larb O B‡**"  Áapbsmigals«3î’ovl@1c000000mediatek,mt8195-disp-ovl{|«3# 0˜ ÷¦ports+port@0endpoint Z¨î§port@1endpoint Z©îªrdma@1c002000mediatek,mt8195-disp-rdma {~«3# 0˜ ÷¦ ports+port@0endpoint Zªî©port@1endpoint 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‹disabledmerge@1c014000mediatek,mt8195-disp-merge@{�«3# ÷¦@dp-intf@1c015000mediatek,mt8195-dp-intfP{‘«3#,#Ápixelenginepll ‹disabledmutex@1c016000mediatek,mt8195-disp-mutex`{’«3# ÷¦` Ularb@1c018000mediatek,mt8195-smi-larb€ O B—#(#("  Áapbsmigals«3îÀlarb@1c019000mediatek,mt8195-smi-larb� O B‡#(" " Áapbsmigals«3î‰syscon@1c100000mediatek,mt8195-vdosys1syscon Ħ ÷¦ ×î+port+endpoint@1 Z¿îÒsmi@1c01b000mediatek,mt8195-smi-common-vdo° #%#&#)#$Áapbsmigals0gals1«3î—iommu@1c01f000mediatek,mt8195-iommu-vdoð8 `ÀÁÂÃÄÅÆÇÈÉÊËÌÍ{�v#'Ábclk«3î˜mutex@1c101000mediatek,mt8195-disp-mutex{î«3+ ÷¦ Àlarb@1c102000mediatek,mt8195-smi-larb  O B—+++ Áapbsmigals«3îÁlarb@1c103000mediatek,mt8195-smi-larb0 O B‡++"  Áapbsmigals«3îŠdma-controller@1c104000mediatek,mt8195-vdo1-rdma@{ï+«3 0˜@ ÷¦@ 7dma-controller@1c105000mediatek,mt8195-vdo1-rdmaP{ð+«3 0†` ÷¦P 7dma-controller@1c106000mediatek,mt8195-vdo1-rdma`{ñ+«3 0˜A ÷¦` 7dma-controller@1c107000mediatek,mt8195-vdo1-rdmap{ò+«3 0†a ÷¦p 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+#+!+$+"+1+&+'+(+)+*ƒÁmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top«3 0†d†e{(Ý+3+4+5+6+7Eävdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncports+port@0+endpoint@1 ZÒî¿port@1+endpoint@1 ZÓîÎhdmi-tx@1c300000mediatek,mt8195-hdmi-tx0 QLM$,Ábushdcphdcp24mhdmi-split÷L“{¥«3 Ô vhdmi‹okayÁdefaultÏÕîi2cmediatek,mt8195-hdmi-ddcîãports+port@0endpoint ZÖîÑport@1endpoint Z×îäedp-tx@1c500000mediatek,mt8195-edp-txP€ðØüdp_calibration_data«3{¤ ¾¤ ‹disableddp-tx@1c600000mediatek,mt8195-dp-tx`€ðØüdp_calibration_data«3{Ê ¾¤ ‹disabledthermal-zonescpu0-thermal Ïè Ýú óÙtripstrip-alert L Ð passiveîÚtrip-crit †  Ð  criticalcooling-mapsmap0 Ú0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu1-thermal Ïè Ýú óÙtripstrip-alert L Ð passiveîÛtrip-crit †  Ð  criticalcooling-mapsmap0 Û0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu2-thermal Ïè Ýú óÙtripstrip-alert L Ð passiveîÜtrip-crit †  Ð  criticalcooling-mapsmap0 Ü0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ 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Ð  criticalimg-thermal Ïè Ýú óâ tripstrip-alert L Ð passivetrip-crit †  Ð  criticalinfra-thermal Ïè Ýú óâtripstrip-alert L Ð passivetrip-crit †  Ð  criticalcam0-thermal Ïè Ýú óâtripstrip-alert L Ð passivetrip-crit †  Ð  criticalcam1-thermal Ïè Ýú óâtripstrip-alert L Ð passivetrip-crit †  Ð  criticalchosen .serial0:921600n8connectorhdmi-connector Úhdmi a :ã FÔportendpoint Zäî×firmwareopteelinaro,optee-tzsmcmemory@40000000memory@reserved-memory+optee@43200000 VC Àmemory@50000000shared-dma-poolP� Vî1memory@53000000shared-dma-poolS@memory@54600000 VT` memory@60000000shared-dma-pool`ð Vî7memory@60f00000shared-dma-pool`ð Vî9memory@61000000shared-dma-poola Vî6memory@62000000shared-dma-poolb@backlight-lcm0pwm-backlight ]ÿ o@ ˆÿ Ÿå¡ î·backlight-lcd1pwm-backlight Ÿæ¡  y. ]ÿ ˆÿ o@ ‹disabledcan-clk fixed-clock 81-2can-clkîAregulator-0regulator-fixed‘edp_panel_3v3 2Z ¸2Z  ¤ ÁdefaultÏçregulator-1regulator-fixed‘edp_backlight_12v ·¸· ¤ `ÁdefaultÏègpio-keys gpio-keysbutton-volume-uph ·d Ej Úvolume_up Ésregulator-vio18-lcm0regulator-fixed ‘vio18_lcm0 ¤ /ÁdefaultÏé Ôêî¸regulator-vsys-lcm0regulator-fixed ‘vsys_lcm0ì ß Ôpî¹regulator-2regulator-fixed ‘wifi_3v3 2Z ¸2Z  ‡ ¤ì compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0ethernet0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformpinctrl-namespinctrl-0audio-routingmediatek,adsplink-namesound-dai#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-upbias-pull-downdrive-strength-microampoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-source#iommu-cells#mbox-cellsmemory-regionfirmware-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectcs-gpiosspi-max-frequencyvdd-supplyxceiver-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-usmediatek,tx-delay-psmediatek,mac-wolpinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupdr_modeusb-role-switchvusb33-supplyremote-endpointbus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcfreq-table-hzmediatek,ufs-disable-mcqbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolesource-pdossink-pdospd-revisionsvidvdomediatek,ibiasmediatek,ibias_upirq-gpiosreset-gpiosAVDD28-supplyvcc-supplymode-switchorientation-switchmediatek,force-modeoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsbacklightenable-gpiosiovcc-supplymediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathddc-i2c-bushdmi-pwr-supplyno-mapbrightness-levelsdefault-brightness-levelnum-interpolated-stepspwmsenable-active-highdebounce-intervallinux,codevin-supplyregulator-boot-on