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?h}zport@1¡endpoint ?i}|i2c@2¡³† +codec@1a wlf,wm8962¡3%M Oj [j hk uj ‚k �j žl ­l ¼€�€•i2c@3¡³† +i2c@11281000mediatek,mt8188-i2c ¡("€€[’ )3c&7 :maindma+xokaypdefault~m³€i2c-mux@73 nxp,pca9546¡spdefault~n 3"+i2c@0¡³† +i2c@1¡³† +i2c@2¡³† +bridge@2c ti,sn65dsi84¡,pdefault~o Å"ports+port@0¡endpoint ?p Ò}¥port@2¡endpoint ?q}³touchscren@5d goodix,gt911¡]pdefault~r ™"’ Ý"’ 3"i2c@3¡³† +i2c@11282000mediatek,mt8188-i2c ¡( "€€[“ )3c&7 :maindma+xokaypdefault~s³€clock-controller@11283000mediatek,mt8188-imp-iic-wrap-c¡(0 }cusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 ¡*-ÿ*> Vmacippcâ*?+[%-"%v35%Ë5:sys_ckref_ckmcu_ck+t 0KpxokayGhost çhigh-speedOLusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci¡Vmac[%."%v35:sys_ckxokay]uOL+ethernet@1 usb424,7850¡+mdio+ethernet-phy@1¡ õusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 ¡+-ÿ+> Vmacippcâ+?+[%,"%v35%É5:sys_ckref_ckmcu_ck+v 0K`xokayGotg çhigh-speed OL~wpdefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci¡Vmac[%+"%v35:sys_ckxokay]xOLconnectorusb-c-connector USB-C dualports+port@0¡endpoint ?y}{port@1¡endpoint ?z}hports+port@0¡endpoint ?{}yport@1¡endpoint ?|}ipcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie¡/  Vpcie-macâ‚  )ÿ•pci 3+03&L&#&&&+&C5 /:pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem[` D}}}} R e~ÿÿ o+ ~pcie-phy”;¢<©macxokaypdefault~€interrupt-controller+}}spi@1132c000(mediatek,mt8188-normediatek,mt8186-nor¡2À3%X55 :spisfaxi%X[9+ xdisabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3âÂ+”;xokaypcie-phy@0¡3%Ä:ref ˆ}hdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phy¡Õð3&:pll_ref hdmi_txpll  ˆ “  ¢ xdisabled}¯dsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx¡È3: mipi_tx0_pll  ˆxokay}£dsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx¡É3: mipi_tx0_pll  ˆ xdisabled}¦i2c@11e00000mediatek,mt8188-i2c ¡à"€[˜ )3�&7 :maindma+xokaypdefault~‚³€i2c@11e01000mediatek,mt8188-i2c ¡à"€€[” )3�&7 :maindma+xokaypdefault~ƒ³€clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w¡à  }�t-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+âãxokayusb-phy@0¡3%Ê$ :refda_ref ˆxokay}vt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+âäxokayusb-phy@0¡3%Æ$ :refda_ref ˆxokay}Iusb-phy@700¡ 3$: :refda_ref ˆxokay}Jt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+âèxokayusb-phy@0¡3%Ì$ :refda_ref ˆxokay}ti2c@11ec0000mediatek,mt8188-i2c ¡ì"€€[• )3„&7 :maindma+ xdisabledi2c@11ec1000mediatek,mt8188-i2c ¡ì"€[– )3„&7 :maindma+ xdisabledclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en¡ì  }„efuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse¡ò+dp-calib@1a0¡  }°lvts1-calib@1ac¡¬@}Fgpu-speedbin@581¡� ´}†socinfo-data1@7a0¡ socinfo-data2@7e0¡àgpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm¡@3…0[~} ijobmmugpuí† ùspeed-bin ¹‡”;;; Ícore0core1core2cxokay à#} clock-controller@13fbf000mediatek,mt8188-mfgcfg¡ûð }…syscon@14000000mediatek,mt8188-vppsys0syscon¡ }(dma-controller@14001000mediatek,mt8188-mdp3-rdma¡ ì3(<Lj ˆˆˆˆ ÷‰€”; þŠ   *‹display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg¡ 3( þŠ display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr¡@3(" þŠ@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal¡P[F3( ”; þŠPdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz¡`3(  þŠ` %display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp¡p3(# þŠpdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color¡€[I3($”; þŠ€display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl¡�[J3(%”; þŠ� ÷‰‚display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding¡ 3(”; þŠ display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc¡°3( þаdisplay@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot¡À ì3( ÷‰ƒ”; þŠÀ  +mutex@1400f000mediatek,mt8188-vpp-mutex¡ð[P3(”; þŠðsmi@14012000mediatek,mt8188-smi-common-vpp¡ 3((:apbsmi”;}Œsmi@14013000mediatek,mt8188-smi-larb¡03((:apbsmi”; 7 HŒ}�iommu@14018000mediatek,mt8188-iommu-vpp¡€P3(:bclk[R”;m U�Ž��‘’}‰dma-controller@14f09000mediatek,mt8188-mdp3-rdma¡ð� ì3*  ÷“¤”; þŠ � …©dma-controller@14f0a000mediatek,mt8188-mdp3-rdma¡ð  ì3*  ÷‰À”; þŠ   †ªdisplay@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg¡ðÀ3*  þŠ Àdisplay@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg¡ðÐ3*  þŠ Ðdisplay@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr¡ðð3*" þŠ ðdisplay@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr¡ñ3*$ þŠ display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal¡ñ [j3*#”; þŠ display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal¡ñ0[k3*%”; þŠ 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz¡ñP3* þŠ P ‘°display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz¡ñ`3* þŠ ` ’±display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp¡ñ€3* þŠ €display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp¡ñ�3* þŠ �display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge¡ñ 3*”; þŠ  display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge¡ñ°3*”; þŠ °display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color¡ñÐ[u3*”; þŠ Ðdisplay@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color¡ñà[v3*”; þŠ àdisplay@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding¡ò3*”; þŠ display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding¡ò 3*”; þŠ display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot¡ò@ ì3* ÷“¦”; þŠ @  ¬display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot¡òP ì3* ÷‰Â”; þŠ P ¡­clock-controller@14e00000mediatek,mt8188-wpesys¡à }4clock-controller@14e02000mediatek,mt8188-wpesys-vpp0¡à  smi@14e04000mediatek,mt8188-smi-larb¡à@344:apbsmi”; 7 HŒ}‘syscon@14f00000mediatek,mt8188-vppsys1syscon¡ð }*mutex@14f01000mediatek,mt8188-vpp-mutex¡ð[{3*&”; þŠ smi@14f02000mediatek,mt8188-smi-larb¡ð 3**:apbsmi”; 7 H”}¬smi@14f03000mediatek,mt8188-smi-larb¡ð03**:apbsmi”; 7 HŒ}�clock-controller@15000000mediatek,mt8188-imgsys¡ clock-controller@15110000 mediatek,mt8188-imgsys1-dip-top¡ Iclock-controller@15130000mediatek,mt8188-imgsys1-dip-nr¡ Iclock-controller@15220000mediatek,mt8188-imgsys-wpe1¡" Iclock-controller@15330000mediatek,mt8188-ipesys¡3 Iclock-controller@15520000mediatek,mt8188-imgsys-wpe2¡R Iclock-controller@15620000mediatek,mt8188-imgsys-wpe3¡b Iclock-controller@16000000mediatek,mt8188-camsys¡ }-clock-controller@1604f000mediatek,mt8188-camsys-rawa¡ð I}0clock-controller@1606f000mediatek,mt8188-camsys-yuva¡ð I}1clock-controller@1608f000mediatek,mt8188-camsys-rawb¡ð I}.clock-controller@160af000mediatek,mt8188-camsys-yuvb¡ ð I}/clock-controller@17200000mediatek,mt8188-ccusys¡  video-decoder@18000000mediatek,mt8188-vcodec-dec ¡@â` ÷‰æ+ *‹video-codec@10000mediatek,mtk-vcodec-lat¡%4"%x 3%4++%x:selvdeclattop[ÄH ÷‰à‰á‰â‰ã‰ä‰å‰æ‰ç‰è”;video-codec@25000mediatek,mtk-vcodec-core¡P%4"%x 3%4,,%x:selvdeclattop[ÃX ÷“À“Á““ÓēœƓǓȓɓʔ;smi@1800d000mediatek,mt8188-smi-larb¡Ð3++:apbsmi”; 7 HŒ}’clock-controller@1800f000mediatek,mt8188-vdecsys-soc¡ð }+smi@1802e000mediatek,mt8188-smi-larb¡à3,,:apbsmi”; 7 H”}®clock-controller@1802f000mediatek,mt8188-vdecsys¡ð },clock-controller@1a000000mediatek,mt8188-vencsys¡ }3smi@1a010000mediatek,mt8188-smi-larb¡333:apbsmi”; 7 H”}­video-encoder@1a020000mediatek,mt8188-vcodec-enc¡+%3"%p33 :venc_sel[aX ÷“ “¡“¢“£“¤“¶“·“¸“¹“ª“º”; *‹jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc¡33:jpgenc[b ÷“§“¨“©“¬”;jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec¡333:jpgdec-smijpgdec[c0 ÷“­“®“²“³“´“µ”;ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl¡3)[| ÷“”; þˆports+port@0¡endpoint ?•}©port@1¡endpoint ?–}—rdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma¡ 3)[~ ÷‰ ”; þˆ ports+port@0¡endpoint ?—}–port@1¡endpoint ?˜}™color@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color¡03)[”; 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compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0ethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0mmc1mmc2rtc0rtc1serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-downinput-enabledrive-strengthbias-pull-upoutput-highinput-disablebias-disabledrive-strength-microampoutput-low#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrstpinctrl-namespinctrl-0#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-boot-onregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parentsregulator-on-in-suspendregulator-suspend-microvolt#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesmediatek,pad-selectnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphysmediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymax-frequencymmc-hs200-1_8vmmc-hs400-1_8vnon-removableno-sdno-sdiosupports-cqevmmc-supplyvqmmc-supplycap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50cd-gpioscap-sdio-irqkeep-power-in-suspendno-mmcpinctrl-2mmc-pwrseqclock-divreset-gpiosremote-endpointAVDD-supplyCPVDD-supplyDBVDD-supplyDCVDD-supplyMICVDD-supplyPLLVDD-supplySPKVDD1-supplySPKVDD2-supplygpio-cfgenable-gpiosdata-lanesirq-gpiosmaximum-speedmicrochip,led-modesusb-role-switchlabeldata-rolebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzbrightness-levelsdefault-brightness-levelnum-interpolated-stepspwmsstdout-pathbacklightpower-supplyno-mapvout-supplyenable-active-highpost-power-on-delay-ms