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  ¢Æ]@soc+ simple-busöúperformance-controller@11bc10mediatek,cpufreq-hw �¼ ½0 ainterrupt-controller@c000000 arm,gic-v3, C �   ? appi-partitionsinterrupt-partition-0X ainterrupt-partition-1Xasyscon@10000000 mediatek,mt8188-topckgensyscon�îa%syscon@10001000#mediatek,mt8188-infracfg-aosyscon�îaa&syscon@10003000mediatek,mt8188-pericfgsyscon�0îaHpinctrl@10005000mediatek,mt8188-pinctrl`�PÀáâê°0niocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteintxˆ”"°C?ë” RPI_GPIO0RPI_GPIO1RPI_GPIO4RPI_GPIO6RPI_GPIO9RPI_GPIO10RPI_GPIO11RPI_GPIO21RPI_GPIO23RPI_GPIO30RPI_GPIO35RPI_GPIO36RPI_GPIO55RPI_GPIO56RPI_GPIO59RPI_GPIO60RPI_GPIO69RPI_GPIO72RPI_GPIO73RPI_GPIO74RPI_GPIO79RPI_GPIO80RPI_GPIO81RPI_GPIO82RPI_GPIO121RPI_GPIO122RPI_GPIO123RPI_GPIO124a"i2c1-pinsacpins°:9·ËÄèmmc0-default-pinsaSpins-clk°�Üëfpins-cmd-dat$°¡ Ÿžš™˜—œúÜ·epins-rst°›Ü·emmc0-uhs-pinsaTpins-clk°�Üëfpins-cmd-dat$°¡ Ÿžš™˜—œúÜ·epins-ds°¢Üëfpins-rst°›Ü·ei2c0-pinsaXpins°87·ËÄèi2c2-pinsaYpins°<;·ËÄèi2c3-pinsaZpins°>=·ËÄèi2c5-pinsaepins°BA·ËÄèi2c6-pinsafpins°DC·ËÄèuart0-pinsaApins° ·uart1-pinsaBpins°VW·uart2-pinsaCpins°#$·pcie-defaultaamux °/01·eth-default-pinsaQpins-cc°‹Œ�ŽÜpins-mdio°��Üúpins-power°‘’pins-rxd°‡ˆ‰ŠÜpins-txd°ƒ„…†Üeth-sleep-pinsaRpins-cc°‹Œ�Žpins-mdio°��!pins-rxd°‡ˆ‰Špins-txd°ƒ„…†spi2-pinsaEpins-spi°OPQR!audio-default-pinsapins-cmd-dat°yz{|usb-default-pinsa]pins-valid°Uúsyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfd�`power-controller!mediatek,mt8188-power-controller+.a:power-domain@0�+.B#power-domain@1�P$%Wmfgaltc&+.B'power-domain@2�.power-domain@3�.power-domain@4�.power-domain@15�àP%%%% %3%4%=%¹%¾( ( ((((((((((((((((( ûWtopcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1c&+.power-domain@16�HP%»%À)))))))AWcfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-busc&+.power-domain@20�0P%º%¿****8Wcfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6c&.power-domain@22�P+Wss-vdec1-soc-l1c&+.power-domain@23�P, Wss-vdec2-l1c&.power-domain@29� P%%% %½Wcamccubuscfgckc&+.power-domain@30�(P-----6Wss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsysc&+.power-domain@32� P-./$Wss-camb-subss-camb-rawss-camb-yuv.power-domain@31�P-01$Wss-cama-subss-cama-rawss-cama-yuv.power-domain@17�(P%¼%Á222&Wcfgckcfgxoss-larb2ss-larb3ss-galsc&+.power-domain@9� P%@%? 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P X ^H mU yV †mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc �$랇P%&&$Wsourcehclksource_cgÝ%í%� \disabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc �%枈P%&&AWsourcehclksource_cgÝ%í%� \disabledthermal-sensor@11278000mediatek,mt8188-lvts-mcu�'€?ÊP&9&pD|lvts-calib-data-1�ai2c@11280000mediatek,mt8188-i2c �("€€?— ”PW&7 Wmaindma+\okaycdefaultqX¢€i2c@11281000mediatek,mt8188-i2c �("€€?’ ”PW&7 Wmaindma+\okaycdefaultqY¢€i2c@11282000mediatek,mt8188-i2c �( "€€?“ ”PW&7 Wmaindma+\okaycdefaultqZ¢€clock-controller@11283000mediatek,mt8188-imp-iic-wrap-c�(0îaWusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 �*-ÿ*> nmacippcú*?+?Ý%-í%vP5%Ë5Wsys_ckref_ckmcu_ckÂ[Ï ÇHp\okayÞhost æhigh-speedôIusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci�nmac?Ý%.í%vP5Wsys_ck\okay+ôIhub@1microchip,usb2513bi�Kusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 �+-ÿ+> nmacippcú+?+?Ý%,í%vP5%É5Wsys_ckref_ckmcu_ckÂ\Ï ÇH`\okay Þperipheralcdefaultq]ôIusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci�nmac?Ý%+í%vP5Wsys_ck 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ýa\t-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+úä\okayusb-phy@0�P%Æ$ Wrefda_ref ýaFusb-phy@700� P$9 Wrefda_ref ýaGt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+úè\okayusb-phy@0�P%Ì$ Wrefda_ref ýa[i2c@11ec0000mediatek,mt8188-i2c �ì"€€?• ”Pd&7 Wmaindma+\okaycdefaultqe¢€i2c@11ec1000mediatek,mt8188-i2c �ì"€?– ”Pd&7 Wmaindma+\okaycdefaultqf¢€clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en�ì îadefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse�ò+dp-calib@1a0�  a‰lvts1-calib@1ac�¬@aDgpu-speedbin@581�� )ahsocinfo-data1@7a0� socinfo-data2@7e0�àgpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm�@Pg0?~} "jobmmugpuph |speed-bin .i+::: Bcore0core1core2R\okay U#a clock-controller@13fbf000mediatek,mt8188-mfgcfg�ûðîagsyscon@14000000mediatek,mt8188-vppsys0syscon�îa(dma-controller@14001000mediatek,mt8188-mdp3-rdma� aP(<^j jjjj lk€+: sl ‹  Ÿmdisplay@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg� P( sl 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 display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge�ñ°P*+: sl °display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color�ñÐ?uP*+: sl Ðdisplay@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color�ñà?vP*+: sl àdisplay@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding�òP*+: sl display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding�ò P*+: sl display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot�ò@ aP* lu¦+: sl @ ‹ ¬display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot�òP aP* lkÂ+: sl P ‹¡­clock-controller@14e00000mediatek,mt8188-wpesys�àîa4clock-controller@14e02000mediatek,mt8188-wpesys-vpp0�à îsmi@14e04000mediatek,mt8188-smi-larb�à@P44Wapbsmi+: ¬ ½nassyscon@14f00000mediatek,mt8188-vppsys1syscon�ðîa*mutex@14f01000mediatek,mt8188-vpp-mutex�ð?{P*&+: sl smi@14f02000mediatek,mt8188-smi-larb�ð P**Wapbsmi+: ¬ ½va…smi@14f03000mediatek,mt8188-smi-larb�ð0P**Wapbsmi+: ¬ ½narclock-controller@15000000mediatek,mt8188-imgsys�îclock-controller@15110000 mediatek,mt8188-imgsys1-dip-top�îaclock-controller@15130000mediatek,mt8188-imgsys1-dip-nr�îaclock-controller@15220000mediatek,mt8188-imgsys-wpe1�"îaclock-controller@15330000mediatek,mt8188-ipesys�3îaclock-controller@15520000mediatek,mt8188-imgsys-wpe2�Rîaclock-controller@15620000mediatek,mt8188-imgsys-wpe3�bîaclock-controller@16000000mediatek,mt8188-camsys�îa-clock-controller@1604f000mediatek,mt8188-camsys-rawa�ðîaa0clock-controller@1606f000mediatek,mt8188-camsys-yuva�ðîaa1clock-controller@1608f000mediatek,mt8188-camsys-rawb�ðîaa.clock-controller@160af000mediatek,mt8188-camsys-yuvb� ðîaa/clock-controller@17200000mediatek,mt8188-ccusys� îvideo-decoder@18000000mediatek,mt8188-vcodec-dec �@ú` lkæ+ Ÿmvideo-codec@10000mediatek,mtk-vcodec-lat�Ý%4í%x P%4++%xWselvdeclattop?ÄH lkàkákâkãkäkåkækçkè+:video-codec@25000mediatek,mtk-vcodec-core�PÝ%4í%x P%4,,%xWselvdeclattop?ÃX luÀuÁuÂuÃuÄuÅuÆuÇuÈuÉuÊ+:smi@1800d000mediatek,mt8188-smi-larb�ÐP++Wapbsmi+: ¬ ½natclock-controller@1800f000mediatek,mt8188-vdecsys-soc�ðîa+smi@1802e000mediatek,mt8188-smi-larb�àP,,Wapbsmi+: ¬ ½va‡clock-controller@1802f000mediatek,mt8188-vdecsys�ðîa,clock-controller@1a000000mediatek,mt8188-vencsys�îa3smi@1a010000mediatek,mt8188-smi-larb�P33Wapbsmi+: ¬ ½va†video-encoder@1a020000mediatek,mt8188-vcodec-enc�+Ý%3í%pP3 Wvenc_sel?aX lu u¡u¢u£u¤u¶u·u¸u¹uªuº+: Ÿmjpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc�P3Wjpgenc?b lu§u¨u©u¬+:jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec�P33Wjpgdec-smijpgdec?c0 lu­u®u²u³u´uµ+:ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl�P)?| lu+: sjports+port@0�endpointport@1�endpoint Ùwaxrdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma� P)?~ lk +: sj ports+port@0�endpoint Ùxawport@1�endpoint Ùyazcolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color�0P)?+: sj0ports+port@0�endpoint Ùzayport@1�endpoint Ù{a|ccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr�@P)?€+: sj@ports+port@0�endpoint Ù|a{port@1�endpoint Ù}a~aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aal�PP) ?�+: sjPports+port@0�endpoint Ù~a}port@1�endpoint Ùa€gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma�`P)?‚+: sj`ports+port@0�endpoint Ù€aport@1�endpointdither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-dither�pP)?ƒ+: sjpports+port@0�endpointport@1�endpointdsi@1c008000mediatek,mt8188-dsi�€P))�Wenginedigitalhs?„Â� ódphy+:9) \disableddsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc��P) ?…+: sj�dsi@1c012000mediatek,mt8188-dsi� P) )‚Wenginedigitalhs?Ž‚ ódphy+:9)  \disabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�@P) 2Wmergemerge_async?�+: sj@dp-intf@1c015000mediatek,mt8188-dp-intf�PP) ) $Wpixelenginepll?‘+: \disabledmutex@1c016000mediatek,mt8188-disp-mutex�`P)?’+: sj` ‹>postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask� P)?•+: sj ports+port@0�endpointport@1�endpointsyscon@1c01d000mediatek,mt8188-vdosys0syscon�Ðîa ^j sjÐa)smi@1c022000mediatek,mt8188-smi-larb� P))Wapbsmi+: ¬ ½vaƒsmi@1c023000mediatek,mt8188-smi-larb�0P))Wapbsmi+: ¬ ½naosmi@1c024000mediatek,mt8188-smi-common-vdo�@P))Wapbsmi+:aviommu@1c028000mediatek,mt8188-iommu-vdo�€PP)Wbclk?¡+: ʃ„…†‡ausyscon@1c100000mediatek,mt8188-vdosys1syscon�îa ^j sja2mutex@1c101000mediatek,mt8188-disp-mutex�P2?î+: sj ‹Åsmi@1c102000mediatek,mt8188-smi-larb� P22Wapbsmi+: ¬ ½va„smi@1c103000mediatek,mt8188-smi-larb�0P22Wapbsmi+: ¬ ½naprdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�@P2?ï lu@+: a sj@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�PP2?ð lk`+: a sjPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�`P2?ñ luA+: a sj`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�pP2?ò lka+: a sjprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�€P2?ó luB+: a sj€rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma��P2?ô lkb+: a sj�rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma� P2?õ luC+: a sj rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�°P2?ö lkc+: a sj°merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�ÀP2 2Wmergemerge_async?÷+:92 sjÀ émerge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�ÐP2 2Wmergemerge_async?ø+:92 sjÐ émerge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�àP2 2Wmergemerge_async?ù+:92 sjà émerge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�ðP2 2Wmergemerge_async?ú+:92 sjð émerge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�P2 2Wmergemerge_async?û+:92 sj ýdpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi� P2822=Wpixelenginepll? +:92 \disabledports+port@0�endpointport@1�endpointdp-intf@1c113000mediatek,mt8188-dp-intf�0P2:2$Wpixelenginepll?+: \disabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp�@Pp� °À4nmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dshP202+2.2,2/2-2<2122232425%ƒWmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top?6 lkdke+:(92122232425p sj@jPjpj�j j°jÀpadding@1c11d000mediatek,mt8188-disp-padding�ÐP2+: sjÐpadding@1c11e000mediatek,mt8188-disp-padding�àP2 +: sjàpadding@1c11f000mediatek,mt8188-disp-padding�ðP2!+: sjðpadding@1c120000mediatek,mt8188-disp-padding�P2"+: sjpadding@1c121000mediatek,mt8188-disp-padding�P2#+: sjpadding@1c122000mediatek,mt8188-disp-padding� P2$+: sj padding@1c123000mediatek,mt8188-disp-padding�0P2%+: sj0padding@1c124000mediatek,mt8188-disp-padding�@P2&+: sj@hdmi@1c300000mediatek,mt8188-hdmi-tx��0 P%@%>%?*.Wbushdcphdcp24mhdmi-splitÝ%>í%s?®+: ˆ óhdmi \disabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddcP9ports+port@0�endpointport@1�endpointedp-tx@1c500000mediatek,mt8188-edp-tx�P€?¤p‰|dp_calibration_data+: ¤ \disableddp-tx@1c600000mediatek,mt8188-dp-tx�`€?Êp‰|dp_calibration_data+:  \disabledchosen %serial0:921600n8firmwareopteelinaro,optee-tz›smcreserved-memory+úoptee@43200000 1�C Àmemory@50000000shared-dma-pool�P� 1a8memory@54600000 1�T` memory@55000000shared-dma-pool�U@memory@57000000shared-dma-pool�W@memory@60000000shared-dma-pool�`ð 1a@memory@60f00000shared-dma-pool�`ð 1a<memory@61000000shared-dma-pool�a 1a?regulator-vsysregulator-fixedÄvsys 8aŠregulator-0regulator-fixed Äfixed-5v0ÓLK@ëLK@ J ]Šregulator-1regulator-fixed Äfixed-4v2Ó@@ë@@ J ]Šregulator-2regulator-fixed Äfixed-3v3Ó2Z ë2Z  J ]ŠaKmemory@40000000„memory�@ compatibleinterrupt-parent#address-cells#size-cellschassis-typemodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c1mmc0ethernet0i2c0i2c2i2c3i2c5i2c6serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0audio-routingmediatek,adsppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-updrive-strength-microampdrive-strengthbias-pull-downinput-enableoutput-highinput-disablebias-disable#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectphysmediatek,syscon-wakeupdr_modemaximum-speedvusb33-supplypeer-hubreset-gpiosvdd-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolmediatek,tx-delay-pssnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpioeee-broken-1000tsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removableclock-divbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzstdout-pathno-mapregulator-boot-onenable-active-highvin-supply