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P X ^H mS yT †mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc �$랇P#$$$Wsourcehclksource_cgÝ#í#� \disabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc �%枈P#$$AWsourcehclksource_cgÝ#í#� \disabledthermal-sensor@11278000mediatek,mt8188-lvts-mcu�'€?ÊP$9$pB|lvts-calib-data-1�ai2c@11280000mediatek,mt8188-i2c �("€€?— ”PU$7 Wmaindma+\okaycdefaultqV¢€i2c@11281000mediatek,mt8188-i2c �("€€?’ ”PU$7 Wmaindma+\okaycdefaultqW¢€i2c@11282000mediatek,mt8188-i2c �( "€€?“ ”PU$7 Wmaindma+\okaycdefaultqX¢€clock-controller@11283000mediatek,mt8188-imp-iic-wrap-c�(0îaUusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 �*-ÿ*> nmacippcú*?+?Ý#-í#vP3#Ë3Wsys_ckref_ckmcu_ckÂYÏ ÇFp\okayÞhost æhigh-speedôGusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci�nmac?Ý#.í#vP3Wsys_ck\okay+ôGhub@1microchip,usb2513bi�Iusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 �+-ÿ+> nmacippcú+?+?Ý#,í#vP3#É3Wsys_ckref_ckmcu_ckÂZÏ ÇF`\okay Þperipheralcdefaultq[ôGusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci�nmac?Ý#+í#vP3Wsys_ck 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ýaZt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+úä\okayusb-phy@0�P#Æ" Wrefda_ref ýaDusb-phy@700� P"7 Wrefda_ref ýaEt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+úè\okayusb-phy@0�P#Ì" Wrefda_ref ýaYi2c@11ec0000mediatek,mt8188-i2c �ì"€€?• ”Pb$7 Wmaindma+\okaycdefaultqc¢€i2c@11ec1000mediatek,mt8188-i2c �ì"€?– ”Pb$7 Wmaindma+\okaycdefaultqd¢€clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en�ì îabefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse�ò+dp-calib@1a0�  a‡lvts1-calib@1ac�¬@aBgpu-speedbin@581�� )afsocinfo-data1@7a0� socinfo-data2@7e0�àgpu@13000000)mediatek,mt8370-maliarm,mali-valhall-jm�@Pe0?~} "jobmmugpupf |speed-bin .g+88 Bcore0core1R\okay U!aclock-controller@13fbf000mediatek,mt8188-mfgcfg�ûðîaesyscon@14000000mediatek,mt8188-vppsys0syscon�îa&dma-controller@14001000mediatek,mt8188-mdp3-rdma� aP&<^h hhhh li€+8 sj ‹  Ÿkdisplay@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg� P& sj display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr�@P&" sj@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal�P?FP& +8 sjPdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz�`P&  sj` ‹%display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp�pP&# sjpdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color�€?IP&$+8 sj€display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl��?JP&%+8 sj� li‚display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding� P&+8 sj display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc�°P& sj°display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot�À aP& liƒ+8 sjÀ ‹ +mutex@1400f000mediatek,mt8188-vpp-mutex�ð?PP&+8 sjðsmi@14012000mediatek,mt8188-smi-common-vpp� P&&Wapbsmi+8alsmi@14013000mediatek,mt8188-smi-larb�0P&&Wapbsmi+8 ¬ ½laoiommu@14018000mediatek,mt8188-iommu-vpp�€PP&Wbclk?R+8 Êmnopqraidma-controller@14f09000mediatek,mt8188-mdp3-rdma�ð� aP(  ls¤+8 sj � ‹…©dma-controller@14f0a000mediatek,mt8188-mdp3-rdma�ð  aP(  liÀ+8 sj   ‹†ªdisplay@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg�ðÀP(  sj Àdisplay@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg�ðÐP(  sj Ðdisplay@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr�ððP(" sj ðdisplay@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr�ñP($ sj display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal�ñ ?jP(#+8 sj display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal�ñ0?kP(%+8 sj 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz�ñPP( sj P ‹‘°display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz�ñ`P( sj ` ‹’±display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp�ñ€P( sj €display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp�ñ�P( sj �display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge�ñ P(+8 sj  display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge�ñ°P(+8 sj °display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color�ñÐ?uP(+8 sj Ðdisplay@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color�ñà?vP(+8 sj àdisplay@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding�òP(+8 sj display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding�ò P(+8 sj display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot�ò@ aP( ls¦+8 sj @ ‹ ¬display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot�òP aP( liÂ+8 sj P ‹¡­clock-controller@14e00000mediatek,mt8188-wpesys�àîa2clock-controller@14e02000mediatek,mt8188-wpesys-vpp0�à îsmi@14e04000mediatek,mt8188-smi-larb�à@P22Wapbsmi+8 ¬ ½laqsyscon@14f00000mediatek,mt8188-vppsys1syscon�ðîa(mutex@14f01000mediatek,mt8188-vpp-mutex�ð?{P(&+8 sj smi@14f02000mediatek,mt8188-smi-larb�ð P((Wapbsmi+8 ¬ ½taƒsmi@14f03000mediatek,mt8188-smi-larb�ð0P((Wapbsmi+8 ¬ ½lapclock-controller@15000000mediatek,mt8188-imgsys�îclock-controller@15110000 mediatek,mt8188-imgsys1-dip-top�îaclock-controller@15130000mediatek,mt8188-imgsys1-dip-nr�îaclock-controller@15220000mediatek,mt8188-imgsys-wpe1�"îaclock-controller@15330000mediatek,mt8188-ipesys�3îaclock-controller@15520000mediatek,mt8188-imgsys-wpe2�Rîaclock-controller@15620000mediatek,mt8188-imgsys-wpe3�bîaclock-controller@16000000mediatek,mt8188-camsys�îa+clock-controller@1604f000mediatek,mt8188-camsys-rawa�ðîaa.clock-controller@1606f000mediatek,mt8188-camsys-yuva�ðîaa/clock-controller@1608f000mediatek,mt8188-camsys-rawb�ðîaa,clock-controller@160af000mediatek,mt8188-camsys-yuvb� ðîaa-clock-controller@17200000mediatek,mt8188-ccusys� îvideo-decoder@18000000mediatek,mt8188-vcodec-dec �@ú` liæ+ Ÿkvideo-codec@10000mediatek,mtk-vcodec-lat�Ý#4í#x P#4))#xWselvdeclattop?ÄH liàiáiâiãiäiåiæiçiè+8video-codec@25000mediatek,mtk-vcodec-core�PÝ#4í#x P#4**#xWselvdeclattop?ÃX lsÀsÁsÂsÃsÄsÅsÆsÇsÈsÉsÊ+8smi@1800d000mediatek,mt8188-smi-larb�ÐP))Wapbsmi+8 ¬ ½larclock-controller@1800f000mediatek,mt8188-vdecsys-soc�ðîa)smi@1802e000mediatek,mt8188-smi-larb�àP**Wapbsmi+8 ¬ ½ta…clock-controller@1802f000mediatek,mt8188-vdecsys�ðîa*clock-controller@1a000000mediatek,mt8188-vencsys�îa1smi@1a010000mediatek,mt8188-smi-larb�P11Wapbsmi+8 ¬ ½ta„video-encoder@1a020000mediatek,mt8188-vcodec-enc�+Ý#3í#pP1 Wvenc_sel?aX ls s¡s¢s£s¤s¶s·s¸s¹sªsº+8 Ÿkjpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc�P1Wjpgenc?b ls§s¨s©s¬+8jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec�P11Wjpgdec-smijpgdec?c0 ls­s®s²s³s´sµ+8ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl�P'?| ls+8 shports+port@0�endpointport@1�endpoint Ùuavrdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma� P'?~ li +8 sh ports+port@0�endpoint Ùvauport@1�endpoint Ùwaxcolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color�0P'?+8 sh0ports+port@0�endpoint Ùxawport@1�endpoint Ùyazccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr�@P'?€+8 sh@ports+port@0�endpoint Ùzayport@1�endpoint Ù{a|aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aal�PP' ?�+8 shPports+port@0�endpoint Ù|a{port@1�endpoint Ù}a~gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma�`P'?‚+8 sh`ports+port@0�endpoint Ù~a}port@1�endpointdither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-dither�pP'?ƒ+8 shpports+port@0�endpointport@1�endpointdsi@1c008000mediatek,mt8188-dsi�€P''Wenginedigitalhs?„ ódphy+89' \disableddsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc��P' ?…+8 sh�dsi@1c012000mediatek,mt8188-dsi� P' '€Wenginedigitalhs?Ž€ ódphy+89'  \disabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�@P' 0Wmergemerge_async?�+8 sh@dp-intf@1c015000mediatek,mt8188-dp-intf�PP' ' "Wpixelenginepll?‘+8 \disabledmutex@1c016000mediatek,mt8188-disp-mutex�`P'?’+8 sh` ‹>postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask� P'?•+8 sh ports+port@0�endpointport@1�endpointsyscon@1c01d000mediatek,mt8188-vdosys0syscon�Ðîa ^h shÐa'smi@1c022000mediatek,mt8188-smi-larb� P''Wapbsmi+8 ¬ ½ta�smi@1c023000mediatek,mt8188-smi-larb�0P''Wapbsmi+8 ¬ ½lamsmi@1c024000mediatek,mt8188-smi-common-vdo�@P''Wapbsmi+8atiommu@1c028000mediatek,mt8188-iommu-vdo�€PP'Wbclk?¡+8 Ê�‚ƒ„…assyscon@1c100000mediatek,mt8188-vdosys1syscon�îa ^h sha0mutex@1c101000mediatek,mt8188-disp-mutex�P0?î+8 sh ‹Åsmi@1c102000mediatek,mt8188-smi-larb� P00Wapbsmi+8 ¬ ½ta‚smi@1c103000mediatek,mt8188-smi-larb�0P00Wapbsmi+8 ¬ ½lanrdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�@P0?ï ls@+8 a sh@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�PP0?ð li`+8 a shPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�`P0?ñ lsA+8 a sh`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�pP0?ò lia+8 a shprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�€P0?ó lsB+8 a sh€rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma��P0?ô lib+8 a sh�rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma� P0?õ lsC+8 a sh rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma�°P0?ö lic+8 a sh°merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�ÀP0 0Wmergemerge_async?÷+890 shÀ émerge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�ÐP0 0Wmergemerge_async?ø+890 shÐ émerge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�àP0 0Wmergemerge_async?ù+890 shà émerge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�ðP0 0Wmergemerge_async?ú+890 shð émerge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge�P0 0Wmergemerge_async?û+890 sh ýdpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi� P0800=Wpixelenginepll? +890 \disabledports+port@0�endpointport@1�endpointdp-intf@1c113000mediatek,mt8188-dp-intf�0P0:0"Wpixelenginepll?+8 \disabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp�@Pp� °À4nmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dshP000+0.0,0/0-0<0102030405#ƒWmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top?6 lidie+8(90102030405p sh@hPhph�h h°hÀpadding@1c11d000mediatek,mt8188-disp-padding�ÐP0+8 shÐpadding@1c11e000mediatek,mt8188-disp-padding�àP0 +8 shàpadding@1c11f000mediatek,mt8188-disp-padding�ðP0!+8 shðpadding@1c120000mediatek,mt8188-disp-padding�P0"+8 shpadding@1c121000mediatek,mt8188-disp-padding�P0#+8 shpadding@1c122000mediatek,mt8188-disp-padding� P0$+8 sh padding@1c123000mediatek,mt8188-disp-padding�0P0%+8 sh0padding@1c124000mediatek,mt8188-disp-padding�@P0&+8 sh@hdmi@1c300000mediatek,mt8188-hdmi-tx��0 P#@#>#?(.Wbushdcphdcp24mhdmi-splitÝ#>í#s?®+8 † óhdmi \disabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddcP7ports+port@0�endpointport@1�endpointedp-tx@1c500000mediatek,mt8188-edp-tx�P€?¤p‡|dp_calibration_data+8 ¤ \disableddp-tx@1c600000mediatek,mt8188-dp-tx�`€?Êp‡|dp_calibration_data+8  \disabledchosen %serial0:921600n8firmwareopteelinaro,optee-tz›smcreserved-memory+úoptee@43200000 1�C Àmemory@50000000shared-dma-pool�P� 1a6memory@54600000 1�T` memory@55000000shared-dma-pool�U@memory@57000000shared-dma-pool�W@memory@60000000shared-dma-pool�`ð 1a>memory@60f00000shared-dma-pool�`ð 1a:memory@61000000shared-dma-pool�a 1a=regulator-vsysregulator-fixedÄvsys 8aˆregulator-0regulator-fixed Äfixed-5v0ÓLK@ëLK@ J ]ˆregulator-1regulator-fixed Äfixed-4v2Ó@@ë@@ J ]ˆregulator-2regulator-fixed Äfixed-3v3Ó2Z ë2Z  J ]ˆaImemory@40000000„memory�@ compatibleinterrupt-parent#address-cells#size-cellschassis-typemodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c1mmc0ethernet0i2c0i2c2i2c3i2c5i2c6serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0audio-routingmediatek,adsppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-updrive-strength-microampdrive-strengthbias-pull-downinput-enableoutput-highinput-disablebias-disable#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectphysmediatek,syscon-wakeupdr_modemaximum-speedvusb33-supplypeer-hubreset-gpiosvdd-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolmediatek,tx-delay-pssnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpioeee-broken-1000tsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removableclock-divbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzstdout-pathno-mapregulator-boot-onenable-active-highvin-supply