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„pcie-mac‚  Jÿ†pci T+0a'L'#'&'+'C6 /hpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem1A` ennnn s †oÿÿ �çp Ÿpcie-phyP;^<emac^okayedefaultsqinterrupt-controller1Ycnspi@1132c000(mediatek,mt8188-normediatek,mt8186-nor’2Àa&X66 hspisfaxi&XA9+ ^disabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3Â+P;^okaypcie-phy@0’a&Ähref ©cphdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phy’Õða'hpll_ref ýhdmi_txpllð © ´  Ã^okayedefaultsrc¶dsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx’Èa: ýmipi_tx0_pllð ©^okaycždsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx’Éa: ýmipi_tx0_pllð © ^disabledc¦i2c@11e00000mediatek,mt8188-i2c ’à"€A˜ ßas'7 hmaindma+^okayedefaultst¤€typec-mux@48 ite,it5205’H Õ á ôuportendpointIvc|i2c@11e01000mediatek,mt8188-i2c ’à"€€A” ßas'7 hmaindma+^okayedefaultsw¤B@rt1715@4erichtek,rt1715’N å# edefaultsx 5yconnectorusb-c-connector ÿUSB-C dual ˜–€ !dual ,sink ; G"�È Q"�Èaltmodesdisplayport ]ÿ bGports+port@0’endpointIzcQport@1’endpointI{cPport@2’endpointI|cvclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w’à ðcst-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ã^okayusb-phy@0’a&Ê% hrefda_ref ©ckt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ä^okayusb-phy@0’a&Æ% hrefda_ref ©cHusb-phy@700’ a%: hrefda_ref ©cIt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+è^okayusb-phy@0’a&Ì% hrefda_ref ©cgi2c@11ec0000mediatek,mt8188-i2c ’ì"€€A• ßa}'7 hmaindma+^okayedefaults~¤€i2c@11ec1000mediatek,mt8188-i2c ’ì"€A– ßa}'7 hmaindma+^okayedefaults¤€clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en’ì ðc}efuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse’ò+dp-calib@1a0’  cºlvts1-calib@1ac’¬@cEgpu-speedbin@581’� fc�socinfo-data1@7a0’ socinfo-data2@7e0’àgpu@13000000)mediatek,mt8370-maliarm,mali-valhall-jm’@a€0A~} Yjobmmugpu•� ¡speed-bin k‚P;; core0core1T^okay ’$c!clock-controller@13fbf000mediatek,mt8188-mfgcfg’ûððc€syscon@14000000mediatek,mt8188-vppsys0syscon’ðc)dma-controller@14001000mediatek,mt8188-mdp3-rdma’ ža)<ƒƒ ƒƒƒƒ ©„€P; °… È  ܆display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg’ a) °… display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr’@a)" °…@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal’PAFa) P; °…Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz’`a)  °…` È%display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp’pa)# °…pdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color’€AIa)$P; °…€display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl’�AJa)%P; °…� ©„‚display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding’ a)P; °… display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc’°a) °…°display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot’À ža) ©„ƒP; °…À È +mutex@1400f000mediatek,mt8188-vpp-mutex’ðAPa)P; °…ðsmi@14012000mediatek,mt8188-smi-common-vpp’ a))hapbsmiP;c‡smi@14013000mediatek,mt8188-smi-larb’0a))hapbsmiP; é ú‡cŠiommu@14018000mediatek,mt8188-iommu-vpp’€Pa)hbclkARP;) ˆ‰Š‹Œ�c„dma-controller@14f09000mediatek,mt8188-mdp3-rdma’ð� ža+  ©Ž¤P; °… � È…©dma-controller@14f0a000mediatek,mt8188-mdp3-rdma’ð  ža+  ©„ÀP; °…   Ȇªdisplay@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg’ðÀa+  °… Àdisplay@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg’ðÐa+  °… Ðdisplay@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr’ðða+" °… ðdisplay@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr’ña+$ °… display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal’ñ Aja+#P; °… display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal’ñ0Aka+%P; °… 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz’ñPa+ °… P È‘°display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz’ñ`a+ °… ` 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ú‡cŒsyscon@14f00000mediatek,mt8188-vppsys1syscon’ððc+mutex@14f01000mediatek,mt8188-vpp-mutex’ðA{a+&P; °… smi@14f02000mediatek,mt8188-smi-larb’ð a++hapbsmiP; é ú�c¬smi@14f03000mediatek,mt8188-smi-larb’ð0a++hapbsmiP; é ú‡c‹clock-controller@15000000mediatek,mt8188-imgsys’ðclock-controller@15110000 mediatek,mt8188-imgsys1-dip-top’ðwclock-controller@15130000mediatek,mt8188-imgsys1-dip-nr’ðwclock-controller@15220000mediatek,mt8188-imgsys-wpe1’"ðwclock-controller@15330000mediatek,mt8188-ipesys’3ðwclock-controller@15520000mediatek,mt8188-imgsys-wpe2’Rðwclock-controller@15620000mediatek,mt8188-imgsys-wpe3’bðwclock-controller@16000000mediatek,mt8188-camsys’ðc.clock-controller@1604f000mediatek,mt8188-camsys-rawa’ððwc1clock-controller@1606f000mediatek,mt8188-camsys-yuva’ððwc2clock-controller@1608f000mediatek,mt8188-camsys-rawb’ððwc/clock-controller@160af000mediatek,mt8188-camsys-yuvb’ ððwc0clock-controller@17200000mediatek,mt8188-ccusys’ ðvideo-decoder@18000000mediatek,mt8188-vcodec-dec ’@` ©„æ+ ܆video-codec@10000mediatek,mtk-vcodec-lat’&4&x a&4,,&xhselvdeclattopAÄH ©„à„á„â„ã„ä„儿„ç„èP;video-codec@25000mediatek,mtk-vcodec-core’P&4&x a&4--&xhselvdeclattopAÃX ©ŽÀŽÁŽÂŽÃŽÄŽÅŽÆŽÇŽÈŽÉŽÊP;smi@1800d000mediatek,mt8188-smi-larb’Ða,,hapbsmiP; é ú‡c�clock-controller@1800f000mediatek,mt8188-vdecsys-soc’ððc,smi@1802e000mediatek,mt8188-smi-larb’àa--hapbsmiP; é ú�c®clock-controller@1802f000mediatek,mt8188-vdecsys’ððc-clock-controller@1a000000mediatek,mt8188-vencsys’ðc4smi@1a010000mediatek,mt8188-smi-larb’a44hapbsmiP; é ú�c­video-encoder@1a020000mediatek,mt8188-vcodec-enc’+&3&pa4 hvenc_selAaX ©Ž Ž¡Ž¢Ž£Ž¤Ž¶Ž·Ž¸Ž¹ŽªŽºP; ܆jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc’a4hjpgencAb ©Ž§Ž¨Ž©Ž¬P;jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec’a44hjpgdec-smijpgdecAc0 ©Ž­Ž®Ž²Ž³Ž´ŽµP;ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl’a*A| ©ŽP; °ƒports+port@0’endpointI�c©port@1’endpointI‘c’rdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma’ a*A~ ©„ P; °ƒ ports+port@0’endpointI’c‘port@1’endpointI“c”color@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color’0a*AP; °ƒ0ports+port@0’endpointI”c“port@1’endpointI•c–ccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr’@a*A€P; °ƒ@ports+port@0’endpointI–c•port@1’endpointI—c˜aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aal’Pa* A�P; °ƒPports+port@0’endpointI˜c—port@1’endpointI™cšgamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma’`a*A‚P; °ƒ`ports+port@0’endpointIšc™port@1’endpointI›c§dither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-dither’pa*AƒP; °ƒpports+port@0’endpointIœc¨port@1’endpointI�c¤dsi@1c008000mediatek,mt8188-dsi’€a**žhenginedigitalhsA„çž ŸdphyP;^*^okay+panel@0#startek,kd070fhfid078himax,hx8279’ Ÿ #- 2# - >¡edefaults¢portendpointI£c¥ports+port@0’endpointI¤c�port@1’endpointI¥c£dsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc’�a* A…P; °ƒ�dsi@1c012000mediatek,mt8188-dsi’ a* *¦henginedigitalhsAŽç¦ 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ú‡c‰rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’@a3Aï ©Ž@P; ž °ƒ@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’Pa3Að ©„`P; ž °ƒPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’`a3Añ ©ŽAP; ž °ƒ`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’pa3Aò ©„aP; ž °ƒprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’€a3Aó ©ŽBP; ž °ƒ€rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’�a3Aô ©„bP; ž °ƒ�rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’ a3Aõ ©ŽCP; ž °ƒ rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma’°a3Aö ©„cP; ž °ƒ°merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge’Àa3 3hmergemerge_asyncA÷P;^3 °ƒÀ :merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge’Ða3 3hmergemerge_asyncAøP;^3 °ƒÐ :merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge’àa3 3hmergemerge_asyncAùP;^3 °ƒà :merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge’ða3 3hmergemerge_asyncAúP;^3 °ƒð :merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge’a3 3hmergemerge_asyncAûP;^3 °ƒ Nports+port@0+’endpoint@1’I°cµport@1+’endpoint@1’I±c²dpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi’ a3833=hpixelenginepllA P;^3^okayports+port@0’endpointI²c±port@1’endpointI³c¸dp-intf@1c113000mediatek,mt8188-dp-intf’0a3:3%hpixelenginepllAP; ^disabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp’@Pp� °À4„mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsha303+3.3,3/3-3<3132333435&ƒhmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_topA6 ©„d„eP;(^3132333435p °ƒ@ƒPƒpƒ�ƒ ƒ°ƒÀports+port@0+’endpoint@1’I´c¯port@1+’endpoint@1’Iµc°padding@1c11d000mediatek,mt8188-disp-padding’Ða3P; °ƒÐpadding@1c11e000mediatek,mt8188-disp-padding’àa3 P; °ƒàpadding@1c11f000mediatek,mt8188-disp-padding’ða3!P; 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