Ð þí.t8%¨(Ì%p$mediatek,mt8195-evbmediatek,mt8195 +!7MediaTek MT8195 evaluation boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000€/soc/vpp-merge@1c10d000‡/soc/vpp-merge@1c10e000Ž/soc/vpp-merge@1c10f000•/soc/vpp-merge@1c110000œ/soc/dma-controller@1c104000§/soc/dma-controller@1c105000²/soc/dma-controller@1c106000½/soc/dma-controller@1c107000È/soc/dma-controller@1c108000Ó/soc/dma-controller@1c109000Þ/soc/dma-controller@1c10a000é/soc/dma-controller@1c10b000ô/soc/serial@11001100cpus+cpu@0ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@100ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@200ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@300ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@400ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙ cpu@500ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙcpu@600ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙcpu@700ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙcpu-mapcluster0core0á core1á core2á core3á core4á core5ácore6ácore7áidle-statesåpscicpu-retention-larm,idle-stateò 2+_;DÙcpu-retention-barm,idle-stateò -+Œ;äÙcpu-off-larm,idle-stateò 7+›;HÙcpu-off-barm,idle-stateò 2+È;èÙl2-cache0cacheLcp@‚¹XÙl2-cache1cacheLcp@‚¹XÙl3-cachecacheLc p@‚XÙdsu-pmu arm,dsu-pmuf q vfaildmic-codec dmic-codec}Š2mt8195-soundš vdisabledfixed-factor-clock-13mfixed-factor-clock¬¹ÀÊÕclk13mÙ(oscillator-26m fixed-clock¬.Œº€Õclk26mÙoscillator-32k fixed-clock¬.€Õclk32kperformance-controller@11bc10mediatek,cpufreq-hw ¼ ½0 èÙopp-table-gpuoperating-points-v2ÙVopp-390000000 >í€ ‰hopp-410000000 p€ ¡Òopp-431000000 °‰À ¡Òopp-473000000 1h@ º<opp-515000000 ²FÀ º<opp-556000000 !#ã Ò¦opp-598000000 #¤Á€ ëopp-640000000 &%  ëopp-670000000 'ïc€ äopp-700000000 )¹' L¸opp-730000000 +‚ê€ }Œopp-760000000 -L® ®`opp-790000000 /q€ ß4opp-820000000 0à5 opp-850000000 2©ø€ @Üopp-880000000 4s¼ q°pmu-a55arm,cortex-a55-pmu fpmu-a78arm,cortex-a78-pmu fpsci arm,psci-1.0smctimerarm,armv8-timer @f   soc+ simple-bus")interrupt-controller@c000000 arm,gic-v34E \    f Ùppi-partitionsinterrupt-partition-0q Ùinterrupt-partition-1q Ùsyscon@10000000 mediatek,mt8195-topckgensyscon¬Ùsyscon@10001000#mediatek,mt8195-infracfg_aosyscon¬zÙsyscon@10003000mediatek,mt8195-pericfgsyscon0¬Ù7pinctrl@10005000mediatek,mt8195-pinctrl€PÑÓÔâëô°B‡iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint‘¡­�\fë4Ùi2c0-pinsÙEpins¹ ÀeÍi2c1-pinsÙFpins¹  ÀeÍi2c4-pinsÙGpins¹ÀeÜèi2c6-pinsÙCpins¹Àei2c7-pinspins¹Àenor-pinsÙApins0 ¹Ž��ôpins1 ¹Œ‚ƒÀuart0-pinsÙ.pins¹bcsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+Ù*power-domain@8+power-domain@9 ¹mfgalt#+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15ع @AKà   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18#+power-domain@168¹â$%&'()Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5#+power-domain@17¹ávppsys1vppsys1-0vppsys1-1#power-domain@22 ¹$wepsys-0wepsys-1wepsys-2wepsys-3#power-domain@23¹vdec0-0#+power-domain@24¹vdec1-0#power-domain@25¹ vdec2-0#power-domain@26¹! venc0-larb#+power-domain@27¹" venc1-larb#power-domain@18 ¹ã###&vdosys1vdosys1-0vdosys1-1vdosys1-2#+power-domain@19#power-domain@20#power-domain@21¹Qhdmi_txpower-domain@28¹$$  img-0img-1#+power-domain@29power-domain@30¹$%ipeipe-0ipe-1#power-domain@31(¹&&&&&cam-0cam-1cam-2cam-3cam-4#+power-domain@32 power-domain@33!power-domain@34"power-domain@0#power-domain@1#power-domain@2power-domain@3power-domain@4¹57csi_rx_topcsi_rx_top1power-domain@5¹' etherpower-domain@6¹Xn adspadsp1+#power-domain@7 ¹g"n2audioaudio1audio2audio3#watchdog@10007000mediatek,mt8195-wdt5pzÙ-syscon@1000c000"mediatek,mt8195-apmixedsyssysconÀ¬Ùtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpf ¹(pwrap@10024000mediatek,mt8195-pwrapsyscon@‡pwrapfó¹ spiwrapM$]Ëspmi@10027000mediatek,mt8195-spmi p� ‡pmifspmimst¹E(pmif_sys_ckpmif_tmr_ckspmimst_clk_muxM$]Ëinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPPftÙ=mailbox@10320000mediatek,mt8195-gce2@fâ�¹Ùymailbox@10330000mediatek,mt8195-gce3@fä�¹ÙWscp@10500000mediatek,mt8195-scp0Prp€‡sramcfgl1tcmfÎ vdisabledÙXclock-controller@10720000mediatek,mt8195-scp_adspr¬Ù)dsp@10803000mediatek,mt8195-dsp €0„ ‡cfgsram,¹XnŠ)#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h�*›rxtx¦+, vdisabledmailbox@10816000mediatek,mt8195-adsp-mbox��`f¾Ù+mailbox@10817000mediatek,mt8195-adsp-mbox��pf¿Ù,mt8195-afe-pcm@10890000mediatek,mt8195-audio‰­�*f6¿- Æaudiosys”¹ÚÛÜÝßg"#neabcd2)óclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp vdisabledÙserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartf� ¹ baudbusvokayÒdefaultà.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartfŽ ¹ baudbus vdisabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartf� ¹ baudbus vdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartfÓ ¹ baudbus vdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartfÔ ¹ baudbus vdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartfÕ ¹ baudbus vdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc ¹mainêvokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon0¬Ù'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ f¿¹™parent-clksel-clkspi-clk vdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap° f©¹¿ü/0$lvts-calib-data-1lvts-calib-data-2Ù¡svs@1100bc00mediatek,mt8195-svs¼fǹmainü1/(svs-calibration-datat-calibration-data¿Æsvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmàfË�*/¹*0mainmm vdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmðf/¹+Nmainmm vdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+fÀ¹™3parent-clksel-clkspi-clk vdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ fÁ¹™4parent-clksel-clkspi-clk vdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0f¹™5parent-clksel-clkspi-clk vdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+€fù™<parent-clksel-clkspi-clk vdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+�fĹ™=parent-clksel-clkspi-clk vdisabledspi@1101d000mediatek,mt8195-spi-slaveÐfŹRspiM]˜ vdisabledspi@1101e000mediatek,mt8195-spi-slaveàfƹSspiM]˜ vdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@fÌ:macirq.axiapbmac_mainptp_refrmii_internalmac_cg0¹''RST' MRST]ÂÃÄ�*J[2k3~4‘œ§ vdisabledmdiosnps,dwmac-mdio+stmmac-axi-config´ÄÔÙ2rx-queues-configÞôÙ3queue0queue1queue2queue3tx-queues-config0FÙ4queue0Xdqueue1Xdqueue2Xdqueue3Xdusb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  -ÿ > ‡macippc" ?+f€¹/íBsys_ckref_ckmcu_ckr56w …7gvokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci‡macf�M,-]––$¹/íB$sys_ckref_ckmcu_ckdma_ckxhci_ckvokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #õfƒ¹sourcehclksource_cg vdisabledmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $Çf‡¹$sourcehclksource_cgM]¿ vdisabledmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %æfˆ¹ Isourcehclksource_cgM ]¿ vdisabledufshci@11270000mediatek,mt8195-ufshci'#f‰r8@¹?@A678Z]Xufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@œª vdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'€fª¹¿ü/0$lvts-calib-data-1lvts-calib-data-2Ù˜usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> ‡macippcfr9:M./]––$¹'ï'$sys_ckref_ckmcu_ckdma_ckxhci_ck …7hwvokayusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-ÿ*> ‡macippc"*?+fM0]–¹'ñ'sys_ckref_ckmcu_ckr;w …7ivokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci‡macfM1]–¹'sys_ckvokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-ÿ+> ‡macippc"+?+fM2]–¹'ó' sys_ckref_ckmcu_ckr<w …7jvokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci‡macfM3]–¹' sys_ckvokayÃpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcieüpci+/@ ‡pcie-macfÔÿ8"� ‚ àÞ=è0¹V#&+K'/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memMG]r> ÷pcie-phy�*4`???? vdisabledinterrupt-controller\4Ù?pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcieüpci+/€@ ‡pcie-macfÔÿ8"�$$ ‚$ $ àÞ=è(¹WXQ'/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memMH]r: ÷pcie-phy�*4`@@@@ vdisabledinterrupt-controller\4Ù@spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2Àf9¹o'' spisfaxi+vokayÒdefaultàAflash@0jedec,spi-nor"úð€efuse@11c10000%mediatek,mt8195-efusemediatek,efuseÁ+usb3-tx-imp@184,1„4ÙMusb3-rx-imp@184,2„4ÙLusb3-intr@185…4ÙKusb3-tx-imp@186,1†4ÙJusb3-rx-imp@186,2†4ÙIusb3-intr@187‡4ÙHusb2-intr-p0@188,1ˆ4usb2-intr-p1@188,2ˆ4usb2-intr-p2@189,1‰4usb2-intr-p3@189,2‰4pciephy-rx-ln1@190,1�4ÙTpciephy-tx-ln1-nmos@190,2�4ÙSpciephy-tx-ln1-pmos@191,1‘4ÙRpciephy-rx-ln0@191,2‘4ÙQpciephy-tx-ln0-nmos@192,1’4ÙPpciephy-tx-ln0-pmos@192,2’4ÙOpciephy-glb-intr@193“4ÙNdp-data@1ac¬Ù—lvts1-calib@1bc¼Ù/lvts2-calib@1d0Ð8Ù0svs-calib@580€dÙ1socinfo-data1@7a0 t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"Ävokayusb-phy@0¹òref9Ù;t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"Åvokayusb-phy@0¹ôref9Ù<dsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txȹ Õmipi_tx0_pll¬9 vdisabledÙ†dsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txɹ Õmipi_tx1_pll¬9 vdisabledÙ‡i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€€fšÀ¹B; maindma+ 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üHIJintrrx_imptx_imp9Ù:t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"ävokayusb-phy@0 ¹î refda_ref9Ù5usb-phy@700¹î refda_ref üKLMintrrx_imptx_imp9Ù6phy@11e80000mediatek,mt8195-pcie-phyè‡sifüNOPQRSTGglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1�*9 vdisabledÙ>ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphyúÀ¹ unipromp9 vdisabledÙ8gpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@¹U0f�Œ‹ :jobmmugpueV(�* * * * *ycore0core1core2core3core4 vdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgûð¬ÙUsyscon@14000000mediatek,mt8195-vppsys0syscon¬ŒWÙdma-controller@14001000mediatek,mt8195-mdp3-rdmaŒW¤ ¸X�*ÅY€¹<¦W W WWWÌdisplay@14002000mediatek,mt8195-mdp3-fg ŒW ¹display@14003000mediatek,mt8195-mdp3-stitch0ŒW0¹display@14004000mediatek,mt8195-mdp3-hdr@ŒW@¹"display@14005000mediatek,mt8195-mdp3-aalPfFŒWP¹ �*display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz`ŒW`¤%¹ display@14007000mediatek,mt8195-mdp3-tdshppŒWp¹#display@14008000mediatek,mt8195-mdp3-color€fIŒW€¹$�*display@14009000mediatek,mt8195-mdp3-ovl�fJŒW�¹%�*ÅY‚display@1400a000mediatek,mt8195-mdp3-padding ŒW ¹�*display@1400b000mediatek,mt8195-mdp3-tcc°ŒW°¹dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotÀŒWÀ¤ +¹ÅYƒ�*Ìmutex@1400f000mediatek,mt8195-vpp-mutexðfPŒWð¹�*smi@14010000mediatek,mt8195-smi-sub-common¹apbsmigals0×Z�*Ù[smi@14011000mediatek,mt8195-smi-sub-common¹apbsmigals0×Z�*Ùxsmi@14012000mediatek,mt8195-smi-common-vpp  ¹apbsmigals0gals1�*ÙZlarb@14013000mediatek,mt8195-smi-larb0ä×[¹apbsmi�*Ù^iommu@14018000mediatek,mt8195-iommu-vpp€8õ\]^_`abcdefghifR¹bclkt�*ÙYclock-controller@14e00000mediatek,mt8195-wpesysà¬Ùclock-controller@14e02000mediatek,mt8195-wpesys_vpp0à ¬clock-controller@14e03000mediatek,mt8195-wpesys_vpp1à0¬larb@14e04000mediatek,mt8195-smi-larbà@ä×j¹apbsmi�*Ù‹larb@14e05000mediatek,mt8195-smi-larbàPä×Z¹ apbsmigals�*Ù`syscon@14f00000mediatek,mt8195-vppsys1sysconð¬ŒW Ùmutex@14f01000mediatek,mt8195-vpp-mutexðf{ŒW ¹'�*larb@14f02000mediatek,mt8195-smi-larbð ä×j¹ apbsmigals�*ÙŠlarb@14f03000mediatek,mt8195-smi-larbð0ä×[¹ apbsmigals�*Ù_display@14f06000mediatek,mt8195-mdp3-splitð`ŒW `¹+,�*display@14f07000mediatek,mt8195-mdp3-tccðpŒW p¹dma-controller@14f08000mediatek,mt8195-mdp3-rdmað€ŒW €¤„¨¹Åk �*Ìdma-controller@14f09000mediatek,mt8195-mdp3-rdmað�ŒW �¤…©¹ Åk¤�*Ìdma-controller@14f0a000mediatek,mt8195-mdp3-rdmað ŒW  ¤†ª¹ ÅYÀ�*Ìdisplay@14f0b000mediatek,mt8195-mdp3-fgð°ŒW °¹ display@14f0c000mediatek,mt8195-mdp3-fgðÀŒW À¹ display@14f0d000mediatek,mt8195-mdp3-fgðÐŒW й display@14f0e000mediatek,mt8195-mdp3-hdrðàŒW à¹display@14f0f000mediatek,mt8195-mdp3-hdrððŒW ð¹display@14f10000mediatek,mt8195-mdp3-hdrñŒW ¹ display@14f11000mediatek,mt8195-mdp3-aalñfiŒW ¹�*display@14f12000mediatek,mt8195-mdp3-aalñ fjŒW ¹�*display@14f13000mediatek,mt8195-mdp3-aalñ0fkŒW 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compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-updrive-strengthdrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupfreq-table-hzmediatek,ufs-disable-mcqusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-max-frequencybits#phy-cellsmediatek,ibiasmediatek,ibias_upoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-en#sound-dai-cellsmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-path