Ð þíQÀ8F¸( F€%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000€/soc/vpp-merge@1c10d000‡/soc/vpp-merge@1c10e000Ž/soc/vpp-merge@1c10f000•/soc/vpp-merge@1c110000œ/soc/dma-controller@1c104000§/soc/dma-controller@1c105000²/soc/dma-controller@1c106000½/soc/dma-controller@1c107000È/soc/dma-controller@1c108000Ó/soc/dma-controller@1c109000Þ/soc/dma-controller@1c10a000é/soc/dma-controller@1c10b000ô/soc/serial@11001100cpus+cpu@0ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@100ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@200ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@300ücpuarm,cortex-a55 psci.ec3@>4Qa€n@€€�€š@¬€¹ÊÙ cpu@400ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙ cpu@500ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙcpu@600ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙcpu@700ücpuarm,cortex-a78 psci.�fÔÀ>Qan@€�š@¬¹ÊÙcpu-mapcluster0core0á core1á core2á core3á core4á core5ácore6ácore7áidle-statesåpscicpu-retention-larm,idle-stateò 2+_;DÙcpu-retention-barm,idle-stateò -+Œ;äÙcpu-off-larm,idle-stateò 7+›;HÙcpu-off-barm,idle-stateò 2+È;èÙl2-cache0cacheLcp@‚¹XÙl2-cache1cacheLcp@‚¹XÙl3-cachecacheLc p@‚XÙdsu-pmu arm,dsu-pmuf q vfaildmic-codec dmic-codec}Š2mt8195-soundš vdisabledfixed-factor-clock-13mfixed-factor-clock¬¹ÀÊÕclk13mÙ(oscillator-26m fixed-clock¬.Œº€Õclk26mÙoscillator-32k fixed-clock¬.€Õclk32kperformance-controller@11bc10mediatek,cpufreq-hw ¼ ½0 èÙopp-table-gpuoperating-points-v2Ùaopp-390000000 >í€ ‰hopp-410000000 p€ ¡Òopp-431000000 °‰À ¡Òopp-473000000 1h@ º<opp-515000000 ²FÀ º<opp-556000000 !#ã Ò¦opp-598000000 #¤Á€ ëopp-640000000 &%  ëopp-670000000 'ïc€ äopp-700000000 )¹' L¸opp-730000000 +‚ê€ }Œopp-760000000 -L® ®`opp-790000000 /q€ ß4opp-820000000 0à5 opp-850000000 2©ø€ @Üopp-880000000 4s¼ q°pmu-a55arm,cortex-a55-pmu fpmu-a78arm,cortex-a78-pmu fpsci arm,psci-1.0smctimerarm,armv8-timer @f   soc+ simple-bus")interrupt-controller@c000000 arm,gic-v34E \    f Ùppi-partitionsinterrupt-partition-0q Ùinterrupt-partition-1q Ùsyscon@10000000 mediatek,mt8195-topckgensyscon¬Ùsyscon@10001000#mediatek,mt8195-infracfg_aosyscon¬zÙsyscon@10003000mediatek,mt8195-pericfgsyscon0¬Ù;pinctrl@10005000mediatek,mt8195-pinctrl€PÑÓÔâëô°B‡iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint‘¡­�\fë4Ùeth-default-pinsÙ7pins-txd¹MNOPÀpins-cc¹UXWVÀpins-rxd¹QRSTpins-mdio¹YZÏpins-power¹[\Üeth-sleep-pinsÙ8pins-txd¹MNOPpins-cc¹UXWVpins-rxd¹QRSTpins-mdio¹YZèögpio-keys-pinsÙ­pins¹jÏi2c6-pinsÙPpins¹mmc0-default-pinsÙ>pins-clk¹zÀfpins-cmd-dat$¹~}|{wvutyÏÀepins-rst¹xÀemmc0-uhs-pinsÙ?pins-clk¹zÀfpins-cmd-dat$¹~}|{wvutyÏÀepins-ds¹Àfpins-rst¹xÀemmc1-default-pinsÙBpins-clk¹oÀfpins-cmd-dat¹npqrsÏÀepins-insert¹�mmc1-uhs-pinsÙCpins-clk¹oÀfpins-cmd-dat¹npqrsÏÀeuart0-pinsÙ.pins¹bcuart1-pinsÙ/pins¹fgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+Ù*power-domain@8+power-domain@9 ¹3mfgalt?+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15ع @AKà   3vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18?+power-domain@168¹â$%&'()D3vdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5?+power-domain@17¹á3vppsys1vppsys1-0vppsys1-1?power-domain@22 ¹$3wepsys-0wepsys-1wepsys-2wepsys-3?power-domain@23¹3vdec0-0?+power-domain@24¹3vdec1-0?power-domain@25¹ 3vdec2-0?power-domain@26¹! 3venc0-larb?+power-domain@27¹" 3venc1-larb?power-domain@18 ¹ã###&3vdosys1vdosys1-0vdosys1-1vdosys1-2?+power-domain@19?power-domain@20?power-domain@21¹Q3hdmi_txpower-domain@28¹$$  3img-0img-1?+power-domain@29power-domain@30¹$%3ipeipe-0ipe-1?power-domain@31(¹&&&&&3cam-0cam-1cam-2cam-3cam-4?+power-domain@32 power-domain@33!power-domain@34"power-domain@0?power-domain@1?power-domain@2power-domain@3power-domain@4¹573csi_rx_topcsi_rx_top1power-domain@5¹' 3etherpower-domain@6¹Xn 3adspadsp1+?power-domain@7 ¹g"n23audioaudio1audio2audio3?watchdog@10007000mediatek,mt8195-wdtQpzÙ-syscon@1000c000"mediatek,mt8195-apmixedsyssysconÀ¬Ùtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpf ¹(pwrap@10024000mediatek,mt8195-pwrapsyscon@‡pwrapfó¹ 3spiwrapi$yËpmicmediatek,mt6359\4� ¡Þadcmediatek,mt6359-auxadcµaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1Çvs1Ö 5î!‘À"buck_vgpu11Çvgpu11Ö€î76ˆÈ K"buck_vmodemÇvmodemÖ€îÈà6*Èbuck_vpuÇvpuÖ€î76ˆÈ K"buck_vcoreÇvcoreÖ€îÖ 6ˆÈ K"buck_vs2Çvs2Ö 5îj"buck_vpaÇvpaÖ¡ î7±Ð,buck_vproc2Çvproc2Ö€î76LÈ K"buck_vproc1Çvproc1Ö€î76LÈ K"buck_vcore_sshub Çvcore_sshubÖ€î7buck_vgpu11_sshub Çvgpu11_sshubÖ€î7ldo_vaud18Çvaud18Öw@îw@ðldo_vsim1Çvsim1Öð î/M`ldo_vibrÇvibrÖO€î2Z ldo_vrf12Çvrf12ÖÈàîÖ "ldo_vusbÇvusbÖ-ÆÀî-ÆÀÀ"Ù<ldo_vsram_proc2 Çvsram_proc2Ö¡ î½¶6Lð"ldo_vio18Çvio18Öð îýàÀ"ldo_vcamioÇvcamioÖð îýàldo_vcn18Çvcn18Öw@îw@ðldo_vfe28Çvfe28Ö*¹€î*¹€xldo_vcn13Çvcn13Ö » îÖ ldo_vcn33_1_bt Çvcn33_1_btÖ*¹€î5gàldo_vcn33_1_wifi Çvcn33_1_wifiÖ*¹€î5gàldo_vaux18Çvaux18Öw@îw@ð"ldo_vsram_others Çvsram_othersÖ¡ î½¶6ˆð"ldo_vefuseÇvefuseÖð î„€ldo_vxo22Çvxo22Öw@î!‘À"ldo_vrfckÇvrfckÖã`îð ldo_vrfck_1ÇvrfckÖëÀîjldo_vbif28Çvbif28Ö*¹€î*¹€ðldo_vio28Çvio28Ö*¹€î2Z "ldo_vemcÇvemcÖ,@ î2Z ldo_vemc_1ÇvemcÖ&% î2Z Ù@ldo_vcn33_2_bt Çvcn33_2_btÖ*¹€î5gàldo_vcn33_2_wifi Çvcn33_2_wifiÖ*¹€î5gàldo_va12Çva12ÖO€îÖ "ldo_va09Çva09Ö 5îO€ldo_vrf18Çvrf18Öð îžPldo_vsram_md Çvsram_mdÖ¡ î½¶6*ð"ldo_vufsÇvufsÖð îýàÙAldo_vm18Çvm18Öð îýà"ldo_vbbckÇvbbckÖÈàîO€"ldo_vsram_proc1 Çvsram_proc1Ö¡ î½¶6Lð"ldo_vsim2Çvsim2Öð î/M`ldo_vsram_others_sshubÇvsram_others_sshubÖ¡ î½¶rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi p� ‡pmifspmimst¹E(3pmif_sys_ckpmif_tmr_ckspmimst_clk_muxi$yËinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPPfcÙKmailbox@10320000mediatek,mt8195-gce2@fâp¹Ù„mailbox@10330000mediatek,mt8195-gce3@fäp¹Ùbscp@10500000mediatek,mt8195-scp0Prp€‡sramcfgl1tcmfÎ vdisabledÙcclock-controller@10720000mediatek,mt8195-scp_adspr¬Ù)dsp@10803000mediatek,mt8195-dsp €0„ ‡cfgsram,¹XnŠ)#K3adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h|*Šrxtx•+, vdisabledmailbox@10816000mediatek,mt8195-adsp-mboxp�`f¾Ù+mailbox@10817000mediatek,mt8195-adsp-mboxp�pf¿Ù,mt8195-afe-pcm@10890000mediatek,mt8195-audio‰œ|*f6®- µaudiosys”¹ÚÛÜÝßg"#neabcd2)ó3clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp vdisabledÙserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartf� ¹ 3baudbusvokayÁdefaultÏ.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartfŽ ¹ 3baudbusvokayÁdefaultÏ/serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartf� ¹ 3baudbus vdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartfÓ ¹ 3baudbus vdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartfÔ ¹ 3baudbus vdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartfÕ ¹ 3baudbus vdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc ¹3mainµ vdisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0¬Ù'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ f¿¹™3parent-clksel-clkspi-clk vdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap° f©¹®Ù01$ålvts-calib-data-1lvts-calib-data-2öÙ¬svs@1100bc00mediatek,mt8195-svs¼fǹ3mainÙ20(åsvs-calibration-datat-calibration-data®µsvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmàfË|* ¹*03mainmm vdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmðf ¹+N3mainmm vdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+fÀ¹™33parent-clksel-clkspi-clk vdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ fÁ¹™43parent-clksel-clkspi-clk vdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0f¹™53parent-clksel-clkspi-clk vdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+€fù™<3parent-clksel-clkspi-clk vdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+�fĹ™=3parent-clksel-clkspi-clk vdisabledspi@1101d000mediatek,mt8195-spi-slaveÐfŹR3spiiy˜ vdisabledspi@1101e000mediatek,mt8195-spi-slaveàfƹS3spiiy˜ vdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@fÌmacirq.3axiapbmac_mainptp_refrmii_internalmac_cg0¹''RST' iRSTyÂÃÄ|*'83H4[5ny„vokay ‘rgmii-idš6 ¥] µ'8€ÁdefaultsleepÏ7Ê8Ômdiosnps,dwmac-mdio+ethernet-phy@1Ù6stmmac-axi-configåõÙ3rx-queues-config%Ù4queue06Iqueue16Iqueue26Iqueue36Itx-queues-configawÙ5queue0‰6•queue1‰6•queue2‰6•queue3‰6•usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  -ÿ > ‡macippc" ?+f€¹/íB3sys_ckref_ckmcu_ck£9:¨ ¶;gvokayÍ<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhci‡macf�i,-y––$¹/íB$3sys_ckref_ckmcu_ckdma_ckxhci_ckvokayÛ=mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #õfƒ¹3sourcehclksource_cgvokayÁdefaultstate_uhsÏ>Ê?çñ ëÂÿ /@HNL]@iAvmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $Çf‡¹$3sourcehclksource_cgiy¿vokayÁdefaultstate_uhsÏBÊC „�çñ ëÂ�ž«]DiEmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %æfˆ¹ I3sourcehclksource_cgi y¿ vdisabledufshci@11270000mediatek,mt8195-ufshci'#f‰£F@¹?@A678Z]X3ufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@¹Ç vdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'€fª¹®Ù01$ålvts-calib-data-1lvts-calib-data-2öÙ£usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> ‡macippcf£GHi./y––$¹'ï'$3sys_ckref_ckmcu_ckdma_ckxhci_ck ¶;h¨vokayÍ<usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-ÿ*> ‡macippc"*?+fi0y–¹'ñ'3sys_ckref_ckmcu_ck£I¨ ¶;ivokayÍ<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhci‡macfi1y–¹'3sys_ckvokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-ÿ+> ‡macippc"+?+fi2y–¹'ó' 3sys_ckref_ckmcu_ck£J¨ ¶;jvokayÍ<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhci‡macfi3y–¹' 3sys_ckvokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcieüpci+/@ ‡pcie-macfàÿ8"� ‚ àêKô0¹V#&+K'/3pl_250mtl_26mtl_96mtl_32kperi_26mperi_memiGy£L pcie-phy|*4 ` MMMM vdisabledinterrupt-controller\4ÙMpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcieüpci+/€@ ‡pcie-macfàÿ8"�$$ ‚$ $ àêKô(¹WXQ'/3pl_250mtl_26mtl_96mtl_32kperi_26mperi_memiHy£H pcie-phy|*4 ` NNNN vdisabledinterrupt-controller\4ÙNspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2Àf9¹o'' 3spisfaxi+ vdisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuseÁ+usb3-tx-imp@184,1„ .ÙXusb3-rx-imp@184,2„ .ÙWusb3-intr@185… .ÙVusb3-tx-imp@186,1† .ÙUusb3-rx-imp@186,2† .ÙTusb3-intr@187‡ .ÙSusb2-intr-p0@188,1ˆ .usb2-intr-p1@188,2ˆ .usb2-intr-p2@189,1‰ .usb2-intr-p3@189,2‰ .pciephy-rx-ln1@190,1� .Ù_pciephy-tx-ln1-nmos@190,2� .Ù^pciephy-tx-ln1-pmos@191,1‘ .Ù]pciephy-rx-ln0@191,2‘ .Ù\pciephy-tx-ln0-nmos@192,1’ .Ù[pciephy-tx-ln0-pmos@192,2’ .ÙZpciephy-glb-intr@193“ .ÙYdp-data@1ac¬Ù¢lvts1-calib@1bc¼Ù0lvts2-calib@1d0Ð8Ù1svs-calib@580€dÙ2socinfo-data1@7a0 t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"Ävokayusb-phy@0¹ò3ref 3ÙIt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"Åvokayusb-phy@0¹ô3ref 3ÙJdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txȹ Õmipi_tx0_pll¬ 3 vdisabledÙ‘dsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txɹ Õmipi_tx1_pll¬ 3 vdisabledÙ’i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€€fšÀ¹O; 3maindma+ vdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€f›À¹O; 3maindma+vokay.€ÏPÁdefaultpmic@34mediatek,mt63604\4 ¡eIRQBchargermediatek,mt6360-chg >Ý@ usb-otg-vbus-regulator Çusb-otg-vbusÖC…(îXáèÙ=regulatormediatek,mt6360-regulator WQbuck1 Çmt6360,buck1Ö“àîÖ  K"buck2 Çmt6360,buck2Ö“àîÖ  K"ÙQldo1 Çmt6360,ldo1ÖO€î6î€Kldo2 Çmt6360,ldo2ÖO€î6î€Kldo3 Çmt6360,ldo3ÖO€î6î€KÙEldo5 Çmt6360,ldo5Ö)2àî6î€KÙDldo6 Çmt6360,ldo6Ö¡ î Kldo7 Çmt6360,ldo7Ö¡ î K"i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð "€€fœÀ¹O; 3maindma+ vdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_sÐ0¬ÙOhdmi-phy@11d5f000mediatek,mt8195-hdmi-phyÕð ¹P  3pll_ref26mpll1pll2 Õhdmi_txpll¬ 3 g  v vdisabledÙ¡i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c à"€€f�À¹R; 3maindma+ vdisabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c à"€f“À¹R; 3maindma+ vdisabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c à "€€f–À¹R; 3maindma+ vdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c à0"€€f˜À¹R; 3maindma+ vdisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c à@"€f™À¹R; 3maindma+ vdisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wàP¬ÙRt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"ã|*vokayusb-phy@0 ¹ð 3refda_ref 3ÙGusb-phy@700¹ð 3refda_ref ÙSTUåintrrx_imptx_imp 3ÙHt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"ävokayusb-phy@0 ¹î 3refda_ref 3Ù9usb-phy@700¹î 3refda_ref ÙVWXåintrrx_imptx_imp 3Ù:phy@11e80000mediatek,mt8195-pcie-phyè‡sifÙYZ[\]^_Gåglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1|* 3 vdisabledÙLufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphyúÀ¹ 3unipromp 3 vdisabledÙFgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@¹`0f�Œ‹ jobmmugpu ˆa(|* * * * * œcore0core1core2core3core4 vdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgûð¬Ù`syscon@14000000mediatek,mt8195-vppsys0syscon¬ ¯bÙdma-controller@14001000mediatek,mt8195-mdp3-rdma ¯b Ç  Ûc|* èd€¹<•b b bbb ïdisplay@14002000mediatek,mt8195-mdp3-fg  ¯b ¹display@14003000mediatek,mt8195-mdp3-stitch0 ¯b0¹display@14004000mediatek,mt8195-mdp3-hdr@ ¯b@¹"display@14005000mediatek,mt8195-mdp3-aalPfF ¯bP¹ |*display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` ¯b` Ç%¹ display@14007000mediatek,mt8195-mdp3-tdshpp ¯bp¹#display@14008000mediatek,mt8195-mdp3-color€fI ¯b€¹$|*display@14009000mediatek,mt8195-mdp3-ovl�fJ ¯b�¹%|* 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