Ð þíRh8D (HCè-google,ciri-sku0google,cirimediatek,mt8188 +7Google Ciri sku0 boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/dsc@1c009000Y/soc/ethdr@1c114000`/soc/mailbox@10320000e/soc/mailbox@10330000j/soc/merge0@1c014000q/soc/merge@1c10c000x/soc/merge@1c10d000/soc/merge@1c10e000†/soc/merge@1c10f000�/soc/merge@1c110000”/soc/mutex@1c016000›/soc/mutex@1c101000¢/soc/padding@1c11d000«/soc/padding@1c11e000´/soc/padding@1c11f000½/soc/padding@1c120000Æ/soc/padding@1c121000Ï/soc/padding@1c122000Ø/soc/padding@1c123000á/soc/padding@1c124000ê/soc/rdma@1c104000õ/soc/rdma@1c105000/soc/rdma@1c106000 /soc/rdma@1c107000/soc/rdma@1c108000!/soc/rdma@1c109000,/soc/rdma@1c10a0007/soc/rdma@1c10b000B/soc/dsi@1c008000G/soc/i2c@11280000L/soc/i2c@11e00000Q/soc/i2c@11281000V/soc/i2c@11282000[/soc/i2c@11e01000`/soc/i2c@11ec0000e/soc/i2c@11ec1000j/soc/mmc@11230000o/soc/serial@11001100cpus+cpu@0wcpuarm,cortex-a55ƒ‡psci•w5”¥¸È€Õ@ç€ô€@€ 1ET cpu@100wcpuarm,cortex-a55ƒ‡psci•w5”¥¸È€Õ@ç€ô€@€ 1ET cpu@200wcpuarm,cortex-a55ƒ‡psci•w5”¥¸È€Õ@ç€ô€@€ 1ET cpu@300wcpuarm,cortex-a55ƒ‡psci•w5”¥¸È€Õ@ç€ô€@€ 1ET cpu@400wcpuarm,cortex-a55ƒ‡psci•w5”¥¸È€Õ@ç€ô€@€ 1ET cpu@500wcpuarm,cortex-a55ƒ‡psci•w5”¥¸È€Õ@ç€ô€@€ 1ETcpu@600wcpuarm,cortex-a78ƒ‡psci•šøÚ¥¸ÈÕ@çô@ 1ETcpu@700wcpuarm,cortex-a78ƒ‡psci•šøÚ¥¸ÈÕ@çô@ 1ETcpu-mapcluster0core0\ core1\ core2\ core3\ core4\ core5\core6\core7\idle-states`pscicpu-off-larm,idle-statem„•2¦_¶DTcpu-off-barm,idle-statem„•-¦Œ¶äTcluster-off-larm,idle-statem„•7¦›¶HTcluster-off-barm,idle-statem„•2¦È¶èTl2-cache0cacheÇÊ×@é ÓTl2-cache1cacheÇÊ×@é ÓTl3-cachecacheÇÊ ×@éÓToscillator-13m fixed-clocká•Æ]@îclk13mTAoscillator-26m fixed-clockᕌº€îclk26mTDoscillator-32k fixed-clocká•€îclk32kopp-table-gpuoperating-points-v2Tzopp-390000000 >í€Æ!ÿopp-431000000 °‰Àöì!ÿopp-473000000 1h@ 'À!ÿopp-515000000 ²FÀ X”!ÿopp-556000000 !#ã ‰h!ÿopp-598000000 #¤Á€ º<!ÿopp-640000000 &%  ë!ÿopp-670000000 'ïc€ ä!ÿopp-700000000 )¹' L¸!ÿopp-730000000 +‚ê€ }Œ!ÿopp-760000000 -L® ®`!ÿopp-790000000 /q€ ß4!ÿopp-835000000 1ÅÀ (r!ÿopp-880000000 4s¼ q°!ÿopp-915000000 6‰ÊÀ ÓX!�opp-915000000-5 6‰ÊÀ ¢„!0opp-915000000-6 6‰ÊÀ q°!popp-950000000 8ŸÙ€ 5!�opp-950000000-5 8ŸÙ€ ÓX!0opp-950000000-6 8ŸÙ€ q°!ppmu-a55arm,cortex-a55-pmu 2pmu-a78arm,cortex-a78-pmu 2psci arm,psci-1.0Žsmcsound=Ookay]Vaud_etdm_hp_onaud_etdm_hp_offaud_etdm_spk_onaud_etdm_spk_offaud_mtkaif_onaud_mtkaif_offdnx‚Œ– mediatek,mt8188-rt5682s7mt8188_m98390_5682á®ETDM1_OUTETDM_SPK_PINETDM2_OUTETDM_HP_PINETDM1_INETDM_SPK_PINETDM2_INETDM_HP_PINADDA CaptureMTKAIF_PINHeadphone JackHPOLHeadphone JackHPORIN1PHeadset MicLeft SpkFront Left BE_OUTRight SpkFront Right BE_OUTdai-link-0 ¼ETDM1_IN_BEÆi2sÑcpudai-link-1 ¼ETDM1_OUT_BEÆi2sÑcpucodecçdai-link-2 ¼ETDM2_IN_BEÑcpucodecçdai-link-3 ¼ETDM2_OUT_BEÑcpucodecçdai-link-4¼DPTX_BEcodecçthermal-zonescpu-little0-thermalñèÿ– tripstrip-alert0%_�1Ð~passiveT!trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<!HA ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little1-thermalñèÿ– tripstrip-alert0%_�1Ð~passiveT"trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<"HA ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little2-thermalñèÿ– tripstrip-alert0%_�1Ð~passiveT#trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<#HA ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little3-thermalñèÿ– tripstrip-alert0%_�1Ð~passiveT$trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<$HA ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big0-thermalñèÿd tripstrip-alert0%_�1Ð~passiveT%trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<%Aÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big1-thermalñèÿd tripstrip-alert0%_�1Ð~passiveT&trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<&Aÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿapu-thermalñèÿú'tripstrip-alert0%L1Ð~passivetrip-alert1%s1Ð~hottrip-crit%† 1 ~criticalgpu-thermalñèÿú'tripstrip-alert0%L1Ð~passiveT(trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<( A)ÿÿÿÿÿÿÿÿgpu1-thermalñèÿú'tripstrip-alert0%L1Ð~passiveT*trip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcooling-mapsmap0<* A)ÿÿÿÿÿÿÿÿadsp-thermalñèÿú'tripstrip-alert0%L1Ð~passivetrip-alert1%s1Ð~hottrip-crit%† 1 ~criticalvdo-thermalñèÿú'tripstrip-alert0%L1Ð~passivetrip-alert1%s1Ð~hottrip-crit%† 1 ~criticalinfra-thermalñèÿú'tripstrip-alert0%L1Ð~passivetrip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcam1-thermalñèÿú'tripstrip-alert0%L1Ð~passivetrip-alert1%s1Ð~hottrip-crit%† 1 ~criticalcam2-thermalñèÿú'tripstrip-alert0%L1Ð~passivetrip-alert1%s1Ð~hottrip-crit%† 1 ~criticaltimerarm,armv8-timer @2   •Æ]@soc+ simple-busPTperformance-controller@11bc10mediatek,cpufreq-hw ƒ¼ ½0 [Tinterrupt-controller@c000000 arm,gic-v3u† � ƒ   2 Tppi-partitionsinterrupt-partition-0² Tinterrupt-partition-1²Tsyscon@10000000 mediatek,mt8188-topckgensysconƒáT.syscon@10001000#mediatek,mt8188-infracfg-aosysconƒá»T/syscon@10003000mediatek,mt8188-pericfgsysconƒ0áTXpinctrl@10005000mediatek,mt8188-pinctrl`ƒPÀáâê°0Èiocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteintÒâî+°�2ëuBúGSC_AP_INT_ODLAP_DISP_BKLTENEN_PPVAR_MIPI_DISPEN_PPVAR_MIPI_DISP_150MATCHSCR_RST_1V8_LI2S_SPKR_DATAOUTEN_PP3300_WLAN_XWIFI_KILL_1V8_LBT_KILL_1V8_LAP_FLASH_WP_LWCAM_PWDN_LWCAM_RST_LUCAM_PWDM_LUCAM_RST_LWCAM_24M_CLKUCAM_24M_CLKMT6319_INTDISP_RST_1V8_LDSIO_DSI_TETPMIPI_BL_PWM_1V8UART_AP_TX_GSC_RXUART_GSC_TX_AP_RXUART_SSPM_TX_DBGCON_RXUART_DBGCON_TX_SSPM_RXUART_ADSP_TX_DBGCON_RXUART_DBGCON_TX_ADSP_RXJTAG_AP_TMSJTAG_AP_TCKJTAG_AP_TDIJTAG_AP_TDOJTAG_AP_TRSTAP_KPCOL0TPTPEC_AP_HPD_ODPCIE_WAKE_1V8_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLAP_I2C_AUD_SCL_1V8AP_I2C_AUD_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TPM_SDA_1V8AP_I2C_TCHSCR_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_PMIC_SAR_SCL_1V8AP_I2C_PMIC_SAR_SDA_1V8AP_I2C_EC_HID_KB_SCL_1V8AP_I2C_EC_HID_KB_SDA_1V8AP_I2C_UCAM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_WCAM_SCL_1V8AP_I2C_WCAM_SDA_1V8SPI_AP_CS_EC_LSPI_AP_CLK_ECSPI_AP_DO_EC_DISPI_AP_DI_EC_DOTPTPSPI_AP_CS_TCHSCR_LSPI_AP_CLK_TCHSCRSPI_AP_DO_TCHSCR_DISPI_AP_DI_TCHSCR_DOTPTPTPTPTPPWRAP_SPI_CS_LPWRAP_SPI_CKPWRAP_SPI_MOSIPWRAP_SPI_MISOSRCLKENA0SRCLKENA1SCP_VREQ_VAOAP_RTC_CLK32KAP_PMIC_WDTRST_LAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1HP_INT_ODLSPKR_INT_ODLI2S_HP_DATAINEN_SPKRI2S_SPKR_MCLKI2S_SPKR_BCLKI2S_HP_MCLKI2S_HP_BCLKI2S_HP_LRCKI2S_HP_DATAOUTRST_SPKR_LI2S_SPKR_LRCKI2S_SPKR_DATAINSPI_AP_CLK_ROMSPI_AP_CS_ROM_LSPI_AP_DO_ROM_DISPI_AP_DI_ROM_DOTPTPEN_PP2800A_UCAM_XEN_PP1200_UCAM_XEN_PP2800A_WCAM_XEN_PP1100_WCAM_XTCHSCR_INT_1V8_LMT7921_PMU_EN_1V8AP_EC_WARM_RST_REQEC_AP_HID_INT_ODLEC_AP_INT_ODLAP_XHCI_INIT_DONEEMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RST_LEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLUSB3_HUB_RST_LEC_AP_RSVD0_ODLSPMI_SCLSPMI_SDAT+adsp-uart-pinsTLpins-bus #$aud-etdm-hp-on-pinsTpins-bus nstupins-mclk raud-etdm-hp-off-pinsTpins-bus nstu pins-mclk r aud-etdm-spk-on-pinsTpins-bus qwx-aud-etdm-spk-off-pinsTpins-bus qwx aud-mtkaif-on-pinsTpins-bus efghijaud-mtkaif-off-pinsTpins-bus efghij cros-ec-int-pinsTOpins-ec-ap-int-odl • disp-pwm0-pinsTQpins-disp-pwm0 <disp-pwm1-pinsTRpins-disp-pwm1 <dp-tx-hpd-pinsT±pins-dp-tx-hpd .gsc-int-pinsTspins-gsc-ap-int-odl  i2c0-pinsTcpins-bus 87i2c1-pinsTrpins-bus :9i2c2-pinsTgpins-bus <;H- i2c3-pinsThpins-bus >=i2c4-pinsTtpins-bus @?i2c5-pinsTvpins-bus BAi2c6-pinsTwpins-bus DCmipi-disp-avdd-en-pinsT·pins-en-ppvar-mipi-disp Umipi-disp-avee-en-pinsT¸pins-en-ppvar-mipi-disp-150ma Umipi-dsi-pinsT—pins-bus Ummc0-default-pinsT^pins-bus$ ¡ Ÿžš™˜—œ -`epins-clk �-fpins-rst ›-`emmc0-uhs-pinsT_pins-bus$ ¡ Ÿžš™˜—œ -`epins-clk �-fpins-ds ¢-fpins-rst ›-`enor-default-pinsTppins-clk  }€pins-cs ~`pcie-default-pinsTopins-bus  /01scp-pinsTBpins-scp-vreq bHspi0-pinsTNpins-bus EFGHHspi1-default-pinsTSpins-bus KLMNHspi1-sleep-pinsTTpins-bus KLMN spi2-pinsTUpins-bus OPQRHuart0-pinsTMpins-bus  `wlan-en-pinsTµpins-en-pp3300-wlan Uaudio-codec-pinsTdpins-hp-int-odl l speaker-en-pinsTfpins-en-spkr osyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfdƒ`power-controller!mediatek,mt8188-power-controller+mTEpower-domain@0ƒ+m�,power-domain@1ƒ�-.–mfgalt¢/+m�0power-domain@2ƒmpower-domain@3ƒmpower-domain@4ƒmpower-domain@15ƒà�.... .3.4.=.¹.¾1 1 11111111111111111 û–topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1¢/+mpower-domain@16ƒH�.».À2222222A–cfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-bus¢/+mpower-domain@20ƒ0�.º.¿33338–cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6¢/mpower-domain@22ƒ�4–ss-vdec1-soc-l1¢/+mpower-domain@23ƒ�5 –ss-vdec2-l1¢/mpower-domain@29ƒ �... .½–camccubuscfgck¢/+m�6power-domain@30ƒ(�777776–ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsys¢/+mpower-domain@32ƒ �789$–ss-camb-subss-camb-rawss-camb-yuvmpower-domain@31ƒ�7:;$–ss-cama-subss-cama-rawss-cama-yuvmpower-domain@17ƒ(�.¼.Á<<<&–cfgckcfgxoss-larb2ss-larb3ss-gals¢/+mpower-domain@9ƒ �.@.? –bushdcp¢/mpower-domain@18ƒ¢/mpower-domain@19ƒ¢/mpower-domain@24ƒ �====0–ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sram¢/mpower-domain@21ƒ�>>–ss-wpe-l7ss-wpe-l7pce¢/mpower-domain@5ƒ¢/�? –ss-pextp-fmemmpower-domain@7ƒ�.0.1–seninf0seninf1mpower-domain@6ƒmpower-domain@10ƒ �.E.D –busmain¢/+mpower-domain@11ƒ ¢/+mpower-domain@14ƒ�.F–asm¢/mpower-domain@13ƒ �.S.@–a1sysintbusadspck¢/mpower-domain@12ƒ ¢/mpower-domain@8ƒ�?  –ethermac¢/mwatchdog@10007000mediatek,mt8188-wdtƒp´»TFsyscon@1000c000"mediatek,mt8188-apmixedsyssysconƒÀáT-timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerƒp2 �Apwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsysconƒ@Èpwrap2ó�// –spiwrappmicmediatek,mt6359�uÌ Ý+Þadcmediatek,mt6359-auxadcñaudio-codecmediatek,mt6359-codec*regulatorsmediatek,mt6359-regulatorbuck_vs1>vs1M 5e!‘À}™buck_vgpu11>vgpu11M€e7­ˆ}È Â™buck_vmodem>vmodemM ÓXe ÓX­*}Èbuck_vpu>vpuM€e7­ˆ}È Â™buck_vcore>vcoreM€eÖ ­ˆ}È Â™buck_vs2>vs2M 5ej}™buck_vpa>vpaM¡ e/M`},buck_vproc2>ppvar_dvdd_vgpuMdpe 5­L}È ÂÚ0ñjT,buck_vproc1>vproc1M€e7­L}È ÂT6buck_vcore_sshub >vcore_sshubM€e7buck_vgpu11_sshub >vgpu11_sshubMdpedp™ldo_vaud18>vaud18Mw@ew@}ðldo_vsim1>vsim1Mð e/M`ldo_vibr>vibrMO€e2Z ldo_vrf12>vrf12MÈàeÖ ™ldo_vusb>vusbM-ÆÀe-ÆÀ}À™ldo_vsram_proc2 >vsram_proc2M¡ e½¶­L}ð™ldo_vio18>vio18Mð eýà}À™Teldo_vcamio>vcamioMð eýàldo_vcn18>vcn18Mw@ew@}ðldo_vfe28>vfe28M*¹€e*¹€}xldo_vcn13>vcn13M » eÖ ldo_vcn33_1_bt >vcn33_1_btM*¹€e5gàldo_vcn33_1_wifi >vcn33_1_wifiM*¹€e5gàldo_vaux18>vaux18Mw@ew@}ð™ldo_vsram_others>pp0850_dvdd_sram_gpuM q°e 5­ˆ}ðÚ,ñjT0ldo_vefuse>vefuseMð e„€ldo_vxo22>vxo22Mw@e!‘À™ldo_vrfck>vrfckMã`eð ldo_vrfck_1>vrfckMëÀejldo_vbif28>vbif28M*¹€e*¹€}ðldo_vio28>vio28M*¹€e2Z ldo_vemc>vemcM,@ e2Z ldo_vemc_1>vemcM&% e2Z T`ldo_vcn33_2_bt >vcn33_2_btM*¹€e5gàldo_vcn33_2_wifi >vcn33_2_wifiM*¹€e5gàldo_va12>va12MO€eÖ ™ldo_va09>va09M 5eO€ldo_vrf18>vrf18Mð ežPldo_vsram_md >vsram_mdM 5e 5­*}ðldo_vufs>vufsMð eýà™Taldo_vm18>vm18Mw@eýà† T›ldo_vbbck>vbbckMÈàeO€ldo_vsram_proc1 >vsram_proc1M¡ e½¶­L}ð™ldo_vsim2>vsim2Mð e/M`ldo_vsram_others_sshub>vsram_others_sshubM¡ e½¶rtcmediatek,mt6358-rtcspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi ƒp� Èpmifspmimst).89.¬�//.8(–pmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infraƒ1P2PTmmailbox@10320000mediatek,mt8188-gceƒ2@2â]�/T{mailbox@10330000mediatek,mt8188-gceƒ3@2ä]�/T}scp@10720000mediatek,mt8188-scp-dualƒrÈcfg+TPOokayscp@0mediatek,scp-coreƒ Èsram2ÎOokayVdefaultdBiCT~scp@d0000mediatek,scp-coreƒ ðÈsram2Ï Odisabledaudio-controller@10b10000mediatek,mt8188-afeƒ±).S9.„´�D- - .³.´.µ.¶.¸.S.. .E.Q.M.N.O.P@.„.†.·.T.Rÿ–clk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec26wE …F Œaudiosys¢/˜.OokayiGªËTadsp@10b80000mediatek,mt8188-dsp@ƒ¸ и°¸ðÈcfgsramsecbus).D�.D.E–audiodspadsp_busëHIòrxtxwE OokayiJKVdefaultdLTmailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxƒ¸a2Þ]THmailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxƒ¸q2ß]TIclock-controller@10b91100mediatek,mt8188-adsp-audio26mƒ¹áT@serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uartƒ2� �D/ –baudbusOokayVdefaultdMserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uartƒ2Ž �D/ –baudbus Odisabledserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uartƒ2� �D/ –baudbus Odisabledserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uartƒ2Ó �D/ –baudbus Odisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadcƒ �/–mainñOokaysyscon@11003000"mediatek,mt8188-pericfg-aosysconƒ0áT?spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ƒ 2¿�.y./–parent-clksel-clkspi-clkOokayVdefaultdNec@0google,cros-ec-spiƒ Ý+•VdefaultdOý-ÆÀi2c-tunnelgoogle,cros-ec-i2c-tunnel+sbs-battery@fsbs,sbs-batteryƒ!5cbasgoogle,cros-cbaskeyboard-controllergoogle,cros-ec-keybJZ mD‡ž­txàáø q rs}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i(”  thermal-sensor@1100b000mediatek,mt8188-lvts-apƒ° 2È�/…/©Pµlvts-calib-data-1ÆT'pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwmƒà�.'//–mainmm2ËÜOokayVdefaultdQT´pwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwmƒð�.(/F–mainmm2Ü OdisabledVdefaultdRspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ƒ2À�.y./2–parent-clksel-clkspi-clkOokayVdefaultsleepdSnTspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ƒ 2Á�.y./3–parent-clksel-clkspi-clkOokayVdefaultdUspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ƒ02Â�.y./4–parent-clksel-clkspi-clk Odisabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ƒ€2Ã�.y./8–parent-clksel-clkspi-clk Odisabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ƒ�2Ä�.y./9–parent-clksel-clkspi-clk Odisabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3 ƒ -ÿ > ÈmacippcT ?+2€).)9.v�? .Å? –sys_ckref_ckmcu_ckçVWì úXhOokay host Yusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciƒÈmac2�).*9.v�? –sys_ckOokay Y 'Zethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10aƒ@2Ì 3macirq0�??.A.B.C? .–axiapbmac_mainptp_refrmii_internalmac_cg).A.B.C9. .¢.£wE C/ T[ d\ w] Š •   Odisabledmdiosnps,dwmac-mdio+stmmac-axi-config ­ · ÇT[rx-queues-config × íT\queue0 þ queue1 þ queue2 þ queue3 þ tx-queues-config ) ?T]queue0 þ Q _queue1 þ Q _queue2 þ Q _queue3 þ Q _mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc ƒ#õ݃ �.///M!–sourcehclksource_cgcrypto_clkOokay k u ‡ ˜H ë § ¶ Å ß å íVdefaultstate_uhsd^n_ û ` ammc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc ƒ$ë݇�.//$–sourcehclksource_cg).9.� Odisabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc ƒ%æÝˆ�.//A–sourcehclksource_cg).9.� Odisabledthermal-sensor@11278000mediatek,mt8188-lvts-mcuƒ'€2Ê�/…/©Pµlvts-calib-data-1ÆT i2c@11280000mediatek,mt8188-i2c ƒ("€€2— !�b/7 –maindma+OokayVdefaultdc•€audio-codec@1arealtek,rt5682sƒ Ý+lVdefaultddÌ +e 7e De SY aTamplifier@38maxim,max98390ƒ8 pFront Right ‚+vVdefaultdfÌTamplifier@39maxim,max98390ƒ9 pFront LeftÌTi2c@11281000mediatek,mt8188-i2c ƒ("€€2’ !�b/7 –maindma+OokayVdefaultdg•€i2c@11282000mediatek,mt8188-i2c ƒ( "€€2“ !�b/7 –maindma+OokayVdefaultdh•€clock-controller@11283000mediatek,mt8188-imp-iic-wrap-cƒ(0áTbusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 ƒ*-ÿ*> ÈmacippcT*?+2).-9.v�?.Ë?–sys_ckref_ckmcu_ckçiì úXpOokay host Yusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciƒÈmac2)..9.v�?–sys_ckOokay Žusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 ƒ+-ÿ+> ÈmacippcT+?+2).,9.v�?.É?–sys_ckref_ckmcu_ckçjì úX`Ookay host Yusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciƒÈmac2).+9.v�?–sys_ckOokay 'kpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcieƒ/  Èpcie-macT‚  Ÿÿwpci ©+0�/L/#/&/+/C? /–pl_250mtl_26mtl_96mtl_32kperi_26mperi_memu2` ºllll È Ûmÿÿ åçn ôpcie-phywE…FŒmacOokayVdefaultdointerrupt-controlleru�Tlspi@1132c000(mediatek,mt8188-normediatek,mt8186-norƒ2À�.X?? –spisfaxi).X29+OokayVdefaultdpflash@0jedec,spi-norƒýut-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3TÂ+wEOokaypcie-phy@0ƒ�.Ä–ref þTnhdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phyƒÕð�/–pll_ref îhdmi_txpllá þ   OdisabledT¯dsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txƒÈ�D îmipi_tx0_pllá þOokay *PT–dsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txƒÉ�D îmipi_tx0_pllá þ OdisabledTŸi2c@11e00000mediatek,mt8188-i2c ƒà"€2˜ !�q/7 –maindma+OokayVdefaultdr•€tpm@50 google,cr50ƒP Ý+Vdefaultdsi2c@11e01000mediatek,mt8188-i2c ƒà"€€2” !�q/7 –maindma+OokayVdefaultdt•€clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-wƒà áTqt-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+TãOokayusb-phy@0ƒ�.Ê- –refda_ref þTjt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+TäOokayusb-phy@0ƒ�.Æ- –refda_ref þTVusb-phy@700ƒ �-D –refda_ref þTWt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+TèOokayusb-phy@0ƒ�.Ì- –refda_ref þTii2c@11ec0000mediatek,mt8188-i2c ƒì"€€2• !�u/7 –maindma+OokayVdefaultdv•€i2c@11ec1000mediatek,mt8188-i2c ƒì"€2– !�u/7 –maindma+OokayVdefaultdw•€clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-enƒì áTuefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuseƒò+dp-calib@1a0ƒ  T°lvts1-calib@1acƒ¬@TPgpu-speedbin@581ƒ� BTysocinfo-data1@7a0ƒ socinfo-data2@7e0ƒàgpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jmƒ@�x02~} 3jobmmugpu©y µspeed-bin GzwEEE [core0core1core2EOokay n,T)clock-controller@13fbf000mediatek,mt8188-mfgcfgƒûðáTxsyscon@14000000mediatek,mt8188-vppsys0sysconƒáT1dma-controller@14001000mediatek,mt8188-mdp3-rdmaƒ z�1<ë{ {{{{ …|€wE Œ} ¤  ¸~display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fgƒ �1 Œ} display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdrƒ@�1" Œ}@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalƒP2F�1 wE Œ}Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszƒ`�1  Œ}` ¤%display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpƒp�1# Œ}pdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-colorƒ€2I�1$wE Œ}€display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovlƒ�2J�1%wE Œ}� …|‚display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddingƒ �1wE Œ} display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tccƒ°�1 Œ}°display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotƒÀ z�1 …|ƒwE Œ}À ¤ +mutex@1400f000mediatek,mt8188-vpp-mutexƒð2P�1wE Œ}ðsmi@14012000mediatek,mt8188-smi-common-vppƒ �11–apbsmiwETsmi@14013000mediatek,mt8188-smi-larbƒ0�11–apbsmiwE Å ÖT‚iommu@14018000mediatek,mt8188-iommu-vppƒ€P�1–bclk2RwEP ã€�‚ƒ„…T|dma-controller@14f09000mediatek,mt8188-mdp3-rdmaƒð� z�3  …†¤wE Œ} � ¤…©dma-controller@14f0a000mediatek,mt8188-mdp3-rdmaƒð  z�3  …|ÀwE Œ}   ¤†ªdisplay@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fgƒðÀ�3  Œ} Àdisplay@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fgƒðÐ�3  Œ} Ðdisplay@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdrƒðð�3" Œ} ðdisplay@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdrƒñ�3$ Œ} display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalƒñ 2j�3#wE Œ} display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalƒñ02k�3%wE Œ} 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszƒñP�3 Œ} P ¤‘°display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszƒñ`�3 Œ} ` ¤’±display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpƒñ€�3 Œ} €display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpƒñ��3 Œ} �display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-mergeƒñ �3wE Œ}  display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-mergeƒñ°�3wE Œ} °display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-colorƒñÐ2u�3wE Œ} Ðdisplay@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-colorƒñà2v�3wE Œ} àdisplay@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddingƒò�3wE Œ} display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddingƒò �3wE Œ} display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotƒò@ z�3 …†¦wE Œ} @ ¤ ¬display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotƒòP z�3 …|ÂwE Œ} P ¤¡­clock-controller@14e00000mediatek,mt8188-wpesysƒàáT>clock-controller@14e02000mediatek,mt8188-wpesys-vpp0ƒà ásmi@14e04000mediatek,mt8188-smi-larbƒà@�>>–apbsmiwE Å ÖT„syscon@14f00000mediatek,mt8188-vppsys1sysconƒðáT3mutex@14f01000mediatek,mt8188-vpp-mutexƒð2{�3&wE Œ} smi@14f02000mediatek,mt8188-smi-larbƒð �33–apbsmiwE Å Ö‡T¥smi@14f03000mediatek,mt8188-smi-larbƒð0�33–apbsmiwE Å ÖTƒclock-controller@15000000mediatek,mt8188-imgsysƒáclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topƒá»clock-controller@15130000mediatek,mt8188-imgsys1-dip-nrƒá»clock-controller@15220000mediatek,mt8188-imgsys-wpe1ƒ"á»clock-controller@15330000mediatek,mt8188-ipesysƒ3á»clock-controller@15520000mediatek,mt8188-imgsys-wpe2ƒRá»clock-controller@15620000mediatek,mt8188-imgsys-wpe3ƒbá»clock-controller@16000000mediatek,mt8188-camsysƒáT7clock-controller@1604f000mediatek,mt8188-camsys-rawaƒðá»T:clock-controller@1606f000mediatek,mt8188-camsys-yuvaƒðá»T;clock-controller@1608f000mediatek,mt8188-camsys-rawbƒðá»T8clock-controller@160af000mediatek,mt8188-camsys-yuvbƒ ðá»T9clock-controller@17200000mediatek,mt8188-ccusysƒ ávideo-decoder@18000000mediatek,mt8188-vcodec-dec ƒ@T` …|æ+ ¸~video-codec@10000mediatek,mtk-vcodec-latƒ).49.x �.444.x–selvdeclattop2ÄH …|à|á|â|ã|ä|å|æ|ç|èwEvideo-codec@25000mediatek,mtk-vcodec-coreƒP).49.x �.455.x–selvdeclattop2ÃX …†À†Á††ÆĆņƆdžȆɆÊwEsmi@1800d000mediatek,mt8188-smi-larbƒÐ�44–apbsmiwE Å ÖT…clock-controller@1800f000mediatek,mt8188-vdecsys-socƒðáT4smi@1802e000mediatek,mt8188-smi-larbƒà�55–apbsmiwE Å Ö‡T§clock-controller@1802f000mediatek,mt8188-vdecsysƒðáT5clock-controller@1a000000mediatek,mt8188-vencsysƒáT=smi@1a010000mediatek,mt8188-smi-larbƒ�==–apbsmiwE Å Ö‡T¦video-encoder@1a020000mediatek,mt8188-vcodec-encƒ+).39.p�= –venc_sel2aX …† †¡†¢†£†¤†¶†·†¸†¹†ª†ºwE ¸~jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgencƒ�=–jpgenc2b …†§†¨†©†¬wEjpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdecƒ�==–jpgdec-smijpgdec2c0 …†­†®†²†³†´†µwEovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovlƒ�22| …†wE Œ{ports+port@0ƒendpoint òˆT¢port@1ƒendpoint ò‰TŠrdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdmaƒ �22~ …| wE Œ{ ports+port@0ƒendpoint òŠT‰port@1ƒendpoint ò‹TŒcolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-colorƒ0�22wE Œ{0ports+port@0ƒendpoint òŒT‹port@1ƒendpoint ò�TŽccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorrƒ@�22€wE Œ{@ports+port@0ƒendpoint òŽT�port@1ƒendpoint ò�T�aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalƒP�2 2�wE Œ{Pports+port@0ƒendpoint ò�T�port@1ƒendpoint ò‘T’gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gammaƒ`�22‚wE Œ{`ports+port@0ƒendpoint ò’T‘port@1ƒendpoint ò“T dither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherƒp�22ƒwE Œ{pports+port@0ƒendpoint ò”T¡port@1ƒendpoint ò•T�dsi@1c008000mediatek,mt8188-dsiƒ€�22––enginedigitalhs2„ç– ôdphywE…2Ookay+panel@0ƒ +Vdefaultd— ˜ ™ %š 1› ?Ookayboe,nv110wum-l60himax,hx83102portendpoint òœTžports+port@0ƒendpoint ò�T•port@1ƒendpoint òžTœdsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dscƒ��2 2…wE Œ{�dsi@1c012000mediatek,mt8188-dsiƒ �2 2Ÿ–enginedigitalhs2ŽçŸ ôdphywE…2  Odisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeƒ@�2 <–mergemerge_async2�wE Œ{@dp-intf@1c015000mediatek,mt8188-dp-intfƒP�2 2 -–pixelenginepll2‘wE Odisabledmutex@1c016000mediatek,mt8188-disp-mutexƒ`�22’wE Œ{` ¤>postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmaskƒ �22•wE Œ{ ports+port@0ƒendpoint ò T“port@1ƒendpoint ò¡T”syscon@1c01d000mediatek,mt8188-vdosys0sysconƒÐá» ë{ Œ{ÐT2port+endpoint@0ƒ ò¢Tˆsmi@1c022000mediatek,mt8188-smi-larbƒ �22–apbsmiwE Å Ö‡T£smi@1c023000mediatek,mt8188-smi-larbƒ0�22–apbsmiwE Å ÖT€smi@1c024000mediatek,mt8188-smi-common-vdoƒ@�22–apbsmiwET‡iommu@1c028000mediatek,mt8188-iommu-vdoƒ€P�2–bclk2¡wEP 㣤¥¦§T†syscon@1c100000mediatek,mt8188-vdosys1sysconƒá» ë{ Œ{T<port+endpoint@1ƒ ò¨T­mutex@1c101000mediatek,mt8188-disp-mutexƒ�<2îwE Œ{ ¤Åsmi@1c102000mediatek,mt8188-smi-larbƒ �<<–apbsmiwE Å Ö‡T¤smi@1c103000mediatek,mt8188-smi-larbƒ0�<<–apbsmiwE Å ÖT�rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒ@�<2ï …†@wE z Œ{@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒP�<2ð …|`wE z Œ{Prdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒ`�<2ñ …†AwE z Œ{`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒp�<2ò …|awE z Œ{prdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒ€�<2ó …†BwE z Œ{€rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒ��<2ô …|bwE z Œ{�rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒ �<2õ …†CwE z Œ{ rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaƒ°�<2ö …|cwE z Œ{°merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeƒÀ�< <–mergemerge_async2÷wE…< Œ{À Hmerge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeƒÐ�< <–mergemerge_async2øwE…< Œ{Ð Hmerge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeƒà�< <–mergemerge_async2ùwE…< Œ{à Hmerge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeƒð�< <–mergemerge_async2úwE…< Œ{ð Hmerge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeƒ�< <–mergemerge_async2ûwE…< Œ{ \ports+port@0+ƒendpoint@1ƒ ò©T®port@1+ƒendpoint@1ƒ òªT«dpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpiƒ �<8<<=–pixelenginepll2 wE…< Odisabledports+port@0ƒendpointport@1ƒendpointdp-intf@1c113000mediatek,mt8188-dp-intfƒ0�<:<-–pixelenginepll2wEOokayports+port@0+ƒendpoint@1ƒ ò«Tªport@1+ƒendpoint@1ƒ ò¬T²ethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrpƒ@Pp� °À4Èmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh�<0<+<.<,</<-<<<1<2<3<4<5.ƒ–mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top26 …|d|ewE(…<1<2<3<4<5p Œ{@{P{p{�{ {°{Àports+port@0+ƒendpoint@1ƒ ò­T¨port@1+ƒendpoint@1ƒ ò®T©padding@1c11d000mediatek,mt8188-disp-paddingƒÐ�<wE Œ{Ðpadding@1c11e000mediatek,mt8188-disp-paddingƒà�< wE Œ{àpadding@1c11f000mediatek,mt8188-disp-paddingƒð�<!wE Œ{ðpadding@1c120000mediatek,mt8188-disp-paddingƒ�<"wE Œ{padding@1c121000mediatek,mt8188-disp-paddingƒ�<#wE Œ{padding@1c122000mediatek,mt8188-disp-paddingƒ �<$wE Œ{ padding@1c123000mediatek,mt8188-disp-paddingƒ0�<%wE Œ{0padding@1c124000mediatek,mt8188-disp-paddingƒ@�<&wE Œ{@hdmi@1c300000mediatek,mt8188-hdmi-tx̃0 �.@.>.?3.–bushdcphdcp24mhdmi-split).>9.s2®wE ç¯ ôhdmi Odisabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddc�Dports+port@0ƒendpointport@1ƒendpointedp-tx@1c500000mediatek,mt8188-edp-txƒP€2¤©°µdp_calibration_datawE s¤ Odisableddp-tx@1c600000mediatek,mt8188-dp-txƒ`€2Ê©°µdp_calibration_datawE sOokayVdefaultd±ÌTports+port@0ƒendpoint ò²T¬port@1ƒendpoint „backlight-lcd0pwm-backlight �ÿ ¡@ + ºÿ ѳ Þ´¡ T˜chosen ãserial0:115200n8dmic-codec dmic-codec ï üdmemory@40000000wmemoryƒ@regulator-pp1800-ldo-z1regulator-fixed>pp1800_ldo_z1™ Mw@ew@kregulator-pp3300-s3regulator-fixed >pp3300_s3™ M2Z e2Z kTYregulator-pp3300-z1regulator-fixed >pp3300_z1™ M2Z e2Z ³Tkregulator-pp3300-wlanregulator-fixed >pp3300_wlan™M2Z e2Z ) <+ dµVdefaultkregulator-pp4200-s5regulator-fixed >pp4200_s5™ M@@e@@³regulator-pp5000-z1regulator-fixed >pp5000_z1™ MLK@eLK@³T¶regulator-pp5000-usb-vbusregulator-fixed>pp5000_usb_vbusMLK@eLK@) <+–¶TZregulator-ppvar-sysregulator-fixed >ppvar_sys™ T³regulator-ppvar-mipi-disp-avddregulator-fixed>ppvar_mipi_disp_avdd) <+Vdefaultd·¶T™regulator-ppvar-mipi-disp-aveeregulator-fixed>ppvar_mipi_disp_avee}') <+Vdefaultd¸¶Tšreserved-memory+Tmemory@50000000shared-dma-poolƒP€ATCmemory@55000000shared-dma-poolƒU@memory@60000000shared-dma-poolƒ`ðATKmemory@60f00000shared-dma-poolƒ`ðATGmemory@61000000shared-dma-poolƒaATJ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0pinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5mediatek,adspaudio-routinglink-namedai-formatmediatek,clk-providersound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-downinput-enabledrive-strengthoutput-highbias-disableoutput-lowbias-pull-up#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadregulator-microvolt-offsetassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmediatek,etdm-out1-cowork-sourcemediatek,etdm-in2-cowork-sourcemboxesmbox-namesspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdno-sdionon-removablesupports-cqevmmc-supplyvqmmc-supplyclock-divAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-srcsound-name-prefixreset-gpiosusb2-lpm-disablebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_updrive-strength-microampbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointenable-gpiosbacklightavdd-supplyavee-supplypp1800-supplyrotationmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanesbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msregulator-boot-onvin-supplyenable-active-highgpiono-map