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Jdisabledports+port@0~endpointport@1~endpointdp-intf@1c113000mediatek,mt8188-dp-intf~0º.:.!Ápixelenginepll-6 Jdisabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp~@Pp� °À4(mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dshº.0.+...,./.-.<.1.2.3.4.5"ƒÁmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top-6 §]d]e6(&.1.2.3.4.5p ®\@\P\p\�\ \°\Àpadding@1c11d000mediatek,mt8188-disp-padding~к.6 ®\Ðpadding@1c11e000mediatek,mt8188-disp-padding~àº. 6 ®\àpadding@1c11f000mediatek,mt8188-disp-padding~ðº.!6 ®\ðpadding@1c120000mediatek,mt8188-disp-padding~º."6 ®\padding@1c121000mediatek,mt8188-disp-padding~º.#6 ®\padding@1c122000mediatek,mt8188-disp-padding~ º.$6 ®\ padding@1c123000mediatek,mt8188-disp-padding~0º.%6 ®\0padding@1c124000mediatek,mt8188-disp-padding~@º.&6 ®\@hdmi@1c300000mediatek,mt8188-hdmi-tx÷~0 º"@">"?&.Ábushdcphdcp24mhdmi-splitÊ">Ú"s-®6 ³z (hdmi Jdisabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddcº5ports+port@0~endpointport@1~endpointedp-tx@1c500000mediatek,mt8188-edp-tx~P€-¤u{�dp_calibration_data6 O¤ Jdisableddp-tx@1c600000mediatek,mt8188-dp-tx~`€-Êu{�dp_calibration_data6 O Jdisabledchosen `serial0:115200n8memory@40000000rmemory~@€reserved-memory+´memory@50000000shared-dma-pool~P� lO4 compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upinput-enabledrive-strengthbias-pull-downbias-disable#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namespinctrl-namespinctrl-0nvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthhs400-ds-delaymax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplypinctrl-1clock-divbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-namesspi-max-frequency#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-names#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzstdout-pathno-map