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Ä“/,/6---F- - --e--h-?-@-A-B-C-ƒ-„-…-†-‡-,)}¥aud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s4_m_seltop_tdm_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div4top_apll12_div_tdmtop_mux_audio_htop_clk26m_clk¾© Ë#/ ß-†h ÀaudiosysžokayÖiѶusb@11201000#mediatek,mt8186-mtu3mediatek,mtu3 š -ÿ > Gmacippc(“-/=/3//>$¥sys_ckref_ckmcu_ckdma_ckxhci_ck¾/ ñj B+ÍÖ ök žokayusb@11200000'mediatek,mt8186-xhcimediatek,mtk-xhciš Gmac(“-/=/3//>$¥sys_ckref_ckmcu_ckdma_ckxhci_ck¾&žokay Rmmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc š#Í “- //U/¥sourcehclksource_cgcrypto¾d}- �žokay°defaultstate_uhs¾l m # ë - ; M \ k x ~ † — ¦ ½n É]mmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc š$É“-//V¥sourcehclksource_cg}-�-ožokay°defaultstate_uhsstate_eint¾o p Öq àmsdcsdio_wakeup fe,W+ # ëÂ ð   Ö 2 ? x ½R É] Frbluetooth@2mediatek,mt7921s-bluetoothš°default¾s L,›usb@11281000#mediatek,mt8186-mtu3mediatek,mtu3 š(-ÿ(> Gmacippc$“/B/?/7)/@$¥sys_ckref_ckmcu_ckdma_ckxhci_ck¾K ñtu B+ÍÖ ök$žokayusb@11280000'mediatek,mt8186-xhcimediatek,mtk-xhciš(Gmac$“/B/?/7)/@$¥sys_ckref_ckmcu_ckdma_ckxhci_ck¾Džokay vt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+ÍÈžokayusb-phy@0š“)¥ref QÑtusb-phy@700š “)¥ref QÑut-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+ÍÊžokayusb-phy@0š“)¥ref Q \Ñjefuse@11cb0000%mediatek,mt8186-efusemediatek,efusešË+lvts1-calib@1ccšÌÑ`lvts2-calib@2f8šøÑacalib@550šPPÑbgpu-speedbin@59cšœ lÑxsocinfo-data1@7a0š dsi-phy@11cc0000mediatek,mt8183-mipi-txšÌ“)x Q šmipi_tx0_pllžokayÑ€clock-controller@13000000mediatek,mt8186-mfgsysšxÑwgpu@13040000&mediatek,mt8186-maliarm,mali-bifrostš@“w0¾ àjobmmugpu BB qcore0core1Û�x ™speed-bin±y5Ožokay „0Ñšsyscon@14000000mediatek,mt8186-mmsyssysconšx:zz �zÑ1mutex@14001000mediatek,mt8186-disp-mutexš“1¾' �z ¨²³ Bsmi@14002000mediatek,mt8186-smi-commonš  “1111¥apbsmigals0gals1 BÑ{smi@14003000mediatek,mt8186-smi-larbš0“11¥apbsmi ¼ Í{ BÑ‚smi@14004000mediatek,mt8186-smi-larbš@“11¥apbsmi ¼ Í{ Bуovl@140050002mediatek,mt8186-disp-ovlmediatek,mt8192-disp-ovlšP“1¾) Ú| �zP Bovl@140060008mediatek,mt8186-disp-ovl-2lmediatek,mt8192-disp-ovl-2lš`“1¾* Ú|! �z` Brdma@140070004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmašp“1¾+ Ú|" �zp Bcolor@140090006mediatek,mt8186-disp-colormediatek,mt8173-disp-colorš�“1 ¾- �z€ Bdpi@1400a000mediatek,mt8186-dpiš “-;1 ¥pixelenginepll}-;�-j¾5 B ždisabled°defaultsleep¾} ~portendpointrÑZccorr@1400b0006mediatek,mt8186-disp-ccorrmediatek,mt8192-disp-ccorrš°“1¾. �z° Baal@1400c0002mediatek,mt8186-disp-aalmediatek,mt8183-disp-aalšÀ“1¾0 �zÀ Bgamma@1400d0006mediatek,mt8186-disp-gammamediatek,mt8183-disp-gammašÐ“1 ¾1 �zÐ Bpostmask@1400e000<mediatek,mt8186-disp-postmaskmediatek,mt8192-disp-postmaskšà“1 ¾2 �zà Bdither@1400f0008mediatek,mt8186-disp-dithermediatek,mt8183-disp-ditheršð“1¾3 �zð Bdsi@14013000mediatek,mt8186-dsiš0“11€¥enginedigitalhs¾7 B†1 ñ€ ádphyžokayportendpointr�ÑKiommu@14016000mediatek,mt8186-iommu-mmš`“1¥bclk¾98 낃„…†‡ˆ‰Š‹Œ�Ž� B úÑ|rdma@1401f0004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmašð“1¾4 Ú|  �zð Bclock-controller@14020000mediatek,mt8186-wpesysšxÑ7smi@14023000mediatek,mt8186-smi-larbš0“77¥apbsmi ¼ Í{ Bчclock-controller@15020000mediatek,mt8186-imgsys1šxÑ4smi@1502e000mediatek,mt8186-smi-larbšà“44¥apbsmi ¼  Í{ Bшclock-controller@15820000mediatek,mt8186-imgsys2š‚xÑ�smi@1582e000mediatek,mt8186-smi-larbš‚à“4�¥apbsmi ¼  Í{ Bщvideo-decoder@16000000mediatek,mt8186-vcodec-decšÍ+É@ÿð Ú|€ ‘video-codec@16025000mediatek,mtk-vcodec-corešP¾W` Ú|€|�|‚|ƒ|„|…|†|‡|ˆ|‰|Š|‹ “-)22-U%¥vdec-selvdec-soc-vdecvdecvdec-top}-)�-U Bsmi@1602e000mediatek,mt8186-smi-larbšà“22¥apbsmi ¼ Í{ BÑ…clock-controller@1602f000mediatek,mt8186-vdecsysšðxÑ2clock-controller@17000000mediatek,mt8186-vencsysšxÑ6smi@17010000mediatek,mt8186-smi-larbš“66¥apbsmi ¼ Í{ B цvideo-encoder@170200006mediatek,mt8186-vcodec-encmediatek,mt8183-vcodec-encš ¾óH Ú|à|á|â|ã|ä|å|æ|ç|è“6 ¥venc_sel}-$�-U B  ‘jpeg-encoder@17030000+mediatek,mt8186-jpgencmediatek,mtk-jpgencš¾õ“6¥jpgenc Ú|é|ê|ë|ì B clock-controller@1a000000mediatek,mt8186-camsysšxÑ3smi@1a001000mediatek,mt8186-smi-larbš“33¥apbsmi ¼  Í{ B ÑŠsmi@1a002000mediatek,mt8186-smi-larbš “33¥apbsmi ¼ Í{ B Ñ‹smi@1a00f000mediatek,mt8186-smi-larbšð“3’¥apbsmi ¼ Í{ B ÑŒsmi@1a010000mediatek,mt8186-smi-larbš“3“¥apbsmi ¼ Í{ B Ñ�clock-controller@1a04f000mediatek,mt8186-camsys_rawašðxÑ’clock-controller@1a06f000mediatek,mt8186-camsys_rawbšðxÑ“clock-controller@1b000000mediatek,mt8186-mdpsysšxÑ”smi@1b002000mediatek,mt8186-smi-larbš “””¥apbsmi ¼ Í{ BÑ„clock-controller@1c000000mediatek,mt8186-ipesysšxÑ5smi@1c00f000mediatek,mt8186-smi-larbšð“55¥apbsmi ¼ Í{ B Ñ�smi@1c10f000mediatek,mt8186-smi-larbšð“55¥apbsmi ¼ Í{ B ÑŽthermal-zonescpu-little0-thermal è "– 8•tripstrip-alert0 HL TÐEpassiveÑ–trip-alert1 Hs TÐEhottrip-crit H†  T Ecriticalcooling-mapsmap0 _–H dÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little1-thermal è "– 8•tripstrip-alert0 HL TÐEpassiveÑ—trip-alert1 Hs TÐEhottrip-crit H†  T Ecriticalcooling-mapsmap0 _—H dÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little2-thermal è "– 8•tripstrip-alert0 HL TÐEpassiveјtrip-alert1 Hs TÐEhottrip-crit H†  T Ecriticalcooling-mapsmap0 _˜H dÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcam-thermal è "ú 8•tripstrip-alert0 HL TÐEpassivetrip-alert1 Hs TÐEhottrip-crit H†  T Ecriticalnna-thermal è "ú 8•tripstrip-alert0 HL TÐEpassivetrip-alert1 Hs TÐEhottrip-crit H†  T Ecriticaladsp-thermal è "ú 8•tripstrip-alert0 HL TÐEpassivetrip-alert1 Hs TÐEhottrip-crit H†  T Ecriticalgpu-thermal è "ú 8•tripstrip-alert0 HL TÐEpassiveÑ™trip-alert1 Hs TÐEhottrip-crit H†  T Ecriticalcooling-mapsmap0 _™ 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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0rdma0rdma1i2c0i2c1i2c2i2c3i2c5mmc0mmc1serial0i2c4clocksregstatusclock-namesoperating-points-v2proc-supplyphandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxinput-enablebias-pull-downinput-schmitt-enablebias-disableoutput-lowdrive-strengthoutput-highbias-pull-up#power-domain-cellsdomain-supplymediatek,infracfgmediatek,disable-extrstmediatek,reset-by-toprguinterrupts-extendedAvdd-supplymediatek,dmic-modevsys-ldo1-supplyvsys-ldo2-supplyvsys-ldo3-supplyvsys-vcore-supplyvsys-vdram1-supplyvsys-vgpu-supplyvsys-vmodem-supplyvsys-vpa-supplyvsys-vproc11-supplyvsys-vproc12-supplyvsys-vs1-supplyvsys-vs2-supplyvs1-ldo1-supplyvs2-ldo1-supplyvs2-ldo2-supplyvs2-ldo3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-coupled-withregulator-coupled-max-spreadassigned-clocksassigned-clock-parents#mbox-cellspinctrl-namespinctrl-0firmware-namememory-regionmediatek,rpmsg-namembox-namesmboxespower-domainsspi-max-frequency#io-channel-cellspowerdown-gpiosreset-gpiosvdd12-supplyvdd33-supplyremote-endpointpower-supplybacklighti2c-scl-internal-delay-nsvcc33-supplyno-reset-on-power-offwakeup-sourcehid-descr-addr#sound-dai-cellsovdd-supplypwr18-supplyextconlink-frequenciessvdd-supplyAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-srcresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellsmediatek,pad-selectgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolegoogle,usb-port-idkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosmediatek,apmixedsysmediatek,topckgenphysmediatek,syscon-wakeupvbus-supplypinctrl-1bus-widthnon-removablecap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqeno-sdno-sdiocap-mmc-hw-reseths400-ds-delaymediatek,hs400-ds-dly3vmmc-supplyvqmmc-supplypinctrl-2interrupt-namescap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50keep-power-in-suspendcap-sdio-irqno-mmcmmc-pwrseq#phy-cellsmediatek,discthbitspower-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathpwmsenable-gpiosbrightness-levelsnum-interpolated-stepsdefault-brightness-levelnum-channelswakeup-delay-mswakeup-event-actionlinux,codelinux,input-typeenable-active-highvin-supplyregulator-boot-onalignmentno-mappinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12pinctrl-13pinctrl-14pinctrl-15pinctrl-16pinctrl-17pinctrl-18mediatek,adspmediatek,platformaudio-routinglink-namedai-formatmediatek,clk-providersound-daisdb-gpiosgpiopost-power-on-delay-ms