Ð þ퟿8—h(W—0(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf}¼Žúžè¯ cluster-sleeparm,idle-stateUf}莼ž Œ·Ü¯cpu@0arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@1arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@2arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@3arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@100arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯cpu@101arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯cpu@102arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯cpu@103arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯ l2-cache0cacheLX¯ l2-cache1cacheLX¯opp-table-0operating-points-v2f¯ opp00q eÔxÞ€†¡ opp01q¿ÌxÞ€†¡ opp02q+s¨@x¡Ð†¡ opp03q98px`†¡ opp04qG†ŒxKP†¡ interrupt-controller@f6801000 arm,gic-400@Õö€ö€ ö€@ ö€` —¨ ½ ÿ¯timerarm,armv8-timer 0½ ÿÿ ÿ ÿsoc simple-bus+Èsram@fff80000!hisilicon,hi6220-sramctrlsysconÕÿø ¯ao_ctrl@f7800000hisilicon,hi6220-aoctrlsysconÕ÷€ Ïܯsys_ctrl@f7030000 hisilicon,hi6220-sysctrlsysconÕ÷ Ïܯmedia_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconÕôAÏܯTpm_ctrl@f7032000hisilicon,hi6220-pmctrlsysconÕ÷ Ïacpu_sctrl@f6504000#hisilicon,hi6220-acpu-sctrlsysconÕöP@ϯXmedianoc_ade@f4520000sysconÕôR@¯Sstub_clockhisilicon,hi6220-stub-clkéÏmbox-tx ¯ serial@f8015000arm,pl011arm,primecellÕøP ½$ø$$uartclkapb_pclkserial@f7111000arm,pl011arm,primecellÕ÷ ½%øuartclkapb_pclk!default /9 >rxtxHokayO)_ðÑ€bluetooth ti,wl1835-st tø ext_clockserial@f7112000arm,pl011arm,primecellÕ÷  ½&øuartclkapb_pclk!default/Hokay �LS-UART0serial@f7113000arm,pl011arm,primecellÕ÷0 ½'øuartclkapb_pclk!default/Hokay �LS-UART1serial@f7114000arm,pl011arm,primecellÕ÷@ ½(øuartclkapb_pclk!default/ Hdisableddma@f7370000hisilicon,k3-dma-1.0Õ÷7‡’Ÿ  ½Tø ¬ ·hi6220_dmaHokay¯timer@f8008000arm,sp804arm,primecellÕø€½øtimer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecellÕø0 ½ ø% apb_pclkrtc@f8004000arm,pl031arm,primecellÕø@ ½ø& apb_pclkpinmux@f7010000pinctrl-singleÕ÷|+ÀÏá ÿp P X ` h p x       ! + 0 8 J z ~  ‡ � —!default/!"#$%¯,gpio-range6¯ boot-sel-pinsW¯!emmc-pinsPW  $¯;sd-pins0W  ¯@sd-idle-pins0W  ¯Csdio-pins0W(,048<¯Hsdio-idle-pins0W(,048<¯Kisp-pins€W$(,048<@DHLPTX\`hkadc-ssi-pinsWh¯"codec-clk-pinsWl¯#codec-pins Wptx|fm-pins W€„ˆŒbt-pins W�”˜œpwm-in-pinsW¸¯$bl-pwm-pinsW¼¯%uart0-pinsWÀÄuart1-pins WÈÌÐÔ¯uart2-pins WØÜàä¯uart3-pins W€„ˆŒ¯uart4-pins WÐÔØÜ¯uart5-pinsWÈÌi2c0-pinsWèì¯0i2c1-pinsWðô¯2i2c2-pinsWøü¯4spi0-pins W ¤¨¬¯-pinmux@f7010800pinconf-singleÕ÷Œ+Àá !default/&'()*boot-sel-cfg-pinsWkˆ£p¯&hkadc-ssi-cfg-pinsWlkˆ£p¯'emmc-clk-cfg-pinsWkˆ£ p¯<emmc-cfg-pinsHW  $(kˆ£p¯=emmc-rst-cfg-pinsW,kˆ£p¯>sd-clk-cfg-pinsW kˆ£0p¯Asd-clk-cfg-idle-pinsW kˆ£p¯Dsd-cfg-pins(W kˆ£ p¯Bsd-cfg-idle-pins(W kˆ£p¯Esdio-clk-cfg-pinsW4kˆ£ p¯Isdio-clk-cfg-idle-pinsW4kˆ£p¯Lsdio-cfg-pins(W8<@DHkˆ£p¯Jsdio-cfg-idle-pins(W8<@DHkˆ£p¯Misp-cfg-func1-pinsxW(,048<@DHLPX\`dkˆ£pisp-cfg-idle1-pinsW48kˆ£pisp-cfg-func2-pinsWTkˆ£pcodec-clk-cfg-pinsWpkˆ£p¯(codec-clk-cfg-idle-pinsWpkˆ£pcodec-cfg-func1-pinsWtkˆ£pcodec-cfg-func2-pinsWx|€kˆ£pcodec-cfg-idle2-pinsWx|€kˆ£pfm-cfg-pins W„ˆŒ�kˆ£pbt-cfg-pins W”˜œ kˆ£pbt-cfg-idle-pins W”˜œ kˆ£ppwm-in-cfg-pinsW¼kˆ£p¯)bl-pwm-cfg-pinsWÀkˆ£p¯*uart0-cfg-func1-pinsWÄkˆ£puart0-cfg-func2-pinsWÈkˆ£puart1-cfg-func1-pinsWÌÔkˆ£p¯uart1-cfg-func2-pinsWÐØkˆ£p¯uart2-cfg-pins WÜàäèkˆ£p¯uart3-cfg-pins W�”˜œkˆ£p¯uart4-cfg-pins Wàäèìkˆ£p¯uart5-cfg-pinsWØÜkˆ£pi2c0-cfg-pinsWìðkˆ£p¯1i2c1-cfg-pinsWôøkˆ£p¯3i2c2-cfg-pinsWükˆ£p¯5spi0-cfg-pins W°´¸¼kˆ£p¯.pinmux@f8001800pinconf-singleÕøx+Àá !default/+rstout-n-cfg-pinsWkˆ£p¯+pmu-peri-en-cfg-pinsWkˆ£psysclk0-en-cfg-pinsWkˆ£pjtag-tdo-cfg-pinsW kˆ£ prf-reset-cfg-pinsWptkˆ£pgpio@f8011000arm,pl061arm,primecellÕø ½4ÁѨ—ø apb_pclkOÝPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN¯6gpio@f8012000arm,pl061arm,primecellÕø  ½5ÁѨ—ø apb_pclk:ÝSD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ON¯gpio@f8013000arm,pl061arm,primecellÕø0 ½6ÁѨ—ø apb_pclkBÝGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecellÕø@ ½7ÁÑí,P¨—ø apb_pclk%ÝGPIO3_0NCNCNCWLAN_ACTIVENCNC¯}gpio@f7020000arm,pl061arm,primecellÕ÷ ½8ÁÑí,X¨—ø apb_pclk?ÝUSER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVE¯|gpio@f7021000arm,pl061arm,primecellÕ÷ ½9ÁÑí,`¨—ø apb_pclk?ÝNCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecellÕ÷  ½:ÁÑí,h¨—ø apb_pclk=Ý[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G¯/gpio@f7023000arm,pl061arm,primecellÕ÷0 ½;ÁÑí,p¨—ø apb_pclk$ÝNCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecellÕ÷@ ½<ÁÑ í,x,¨—ø apb_pclkÝNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellÕ÷P ½=ÁÑí,¨—ø apb_pclk'ÝGPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecellÕ÷` ½>ÁÑ í,,¨—ø apb_pclk?ÝBOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellÕ÷p ½?ÁÑ í,,¨—ø apb_pclk"Ý[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecellÕ÷€ ½@ÁÑ í,!,+¨—ø apb_pclk8Ý[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecellÕ÷� ½AÁÑí,0¨—ø apb_pclkhÝ[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecellÕ÷  ½BÁÑí,8¨—ø apb_pclkZÝ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecellÕ÷° ½CÁÑ0í,J,z,~¨—ø apb_pclk ÝNCgpio@f702c000arm,pl061arm,primecellÕ÷À ½DÁÑí,¨—ø apb_pclkgpio@f702d000arm,pl061arm,primecellÕ÷Ð ½EÁÑí,‡¨—ø apb_pclkgpio@f702e000arm,pl061arm,primecellÕ÷à ½FÁÑí,�¨—ø apb_pclkgpio@f702f000arm,pl061arm,primecellÕ÷ð ½GÁÑí,—¨—ø apb_pclkspi@f7106000arm,pl022arm,primecellÕ÷` ½2øsspclkapb_pclk!default/-.ù /Hokayi2c@f7100000snps,designware-i2cÕ÷ ½,ø  ,!default/01Hokayi2c@f7101000snps,designware-i2cÕ÷ø ½- ,!default/23Hokayi2c@f7102000snps,designware-i2cÕ÷ ø ½. ,!default/45Hokay+adv7533@39 adi,adv7533Õ9 ½ 6'5ports+port@0ÕendpointF7¯Wport@2ÕendpointF8¯Pusbphyhisilicon,hi6220-usb-phyVa9l¯:usb@f72c0000hisilicon,hi6220-usbÕ÷,ˆ: �usb2-phyøotg—otgŸ®€<À€€€€€€€€ ½Mmailbox@f7510000hisilicon,hi6220-mbox Õ÷Qßø ½^ϯdwmmc0@f723d000hisilicon,hi6220-dw-mshcÕ÷#Ð ½HøciubiuÛâreset!default/;<=>î?dwmmc1@f723e000hisilicon,hi6220-dw-mshclÕ÷#à ½I+øciubiuÛâreset !defaultidle /@AB $CDE.È@Q^kxFG… �dwmmc2@f723f000hisilicon,hi6220-dw-mshcÕ÷#ð ½JøciubiuÛâreset !defaultidle /HIJ $KLM™N¬O+wlcore@2 ti,wl1835Õ ½watchdog@f8005000arm,sp805arm,primecellÕøP ½ øwdog_clkapb_pclktsensor@f7030700hisilicon,tsensorÕ÷ ½ø thermal_clk·¯Qi2s@f7118000hisilicon,hi6210-i2sÕ÷€€ ½{ø 8dacodeci2s-base9>rxtxÍ5portsport@0¯~endpointFPæi2s¯8thermal-zonescls0-thermalñèÿd þ'Qtripstrip-point07ýèCÐpassivetrip-point17$øCÐpassive¯Rcooling-mapsmap0NR`Sÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿade@f4100000hisilicon,hi6220-adeÕôx bade_baselSÛT ½søTTT(clk_ade_coreclk_codec_jpegclk_ade_pixOTT_u**ˆ�HokayportendpointFU¯Vdsi@f4107800hisilicon,hi6220-dsiÕôxøTpclkHokayports+port@0ÕendpointFV¯Uport@1Õendpoint@0FW¯7debug@f6590000&arm,coresight-cpu-debugarm,primecellÕöYø; apb_pclkDdebug@f6592000&arm,coresight-cpu-debugarm,primecellÕöY ø; apb_pclkDdebug@f6594000&arm,coresight-cpu-debugarm,primecellÕöY@ø; apb_pclkDdebug@f6596000&arm,coresight-cpu-debugarm,primecellÕöY`ø; apb_pclkDdebug@f65d0000&arm,coresight-cpu-debugarm,primecellÕö]ø; apb_pclkDdebug@f65d2000&arm,coresight-cpu-debugarm,primecellÕö] ø; apb_pclkDdebug@f65d4000&arm,coresight-cpu-debugarm,primecellÕö]@ø; apb_pclkDdebug@f65d6000&arm,coresight-cpu-debugarm,primecellÕö]`ø; apb_pclkD gpu@f4080000#hisilicon,hi6220-maliarm,mali-450Õô „½~~~~~~~~~~~8Žgpgpmmupppp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3øTT buscoreOTT_Íe•Dâao_g3dmedia_g3dÛTfunnel@f6401000+arm,coresight-dynamic-funnelarm,primecellÕö@øX apb_pclkout-portsportendpointFY¯[in-portsportendpointFZ¯betf@f6402000 arm,coresight-tmcarm,primecellÕö@ øX apb_pclkin-portsportendpointF[¯Yout-portsportendpointF\¯]replicator arm,coresight-static-replicatorøX apb_pclkin-portsportendpointF]¯\out-ports+port@0ÕendpointF^¯`port@1ÕendpointF_¯aetr@f6404000 arm,coresight-tmcarm,primecellÕö@@øX apb_pclkin-portsportendpointF`¯^tpiu@f6405000!arm,coresight-tpiuarm,primecellÕö@PøX apb_pclkin-portsportendpointFa¯_funnel@f6501000+arm,coresight-dynamic-funnelarm,primecellÕöPøX apb_pclkout-portsportendpointFb¯Zin-ports+port@0ÕendpointFc¯kport@1ÕendpointFd¯lport@2ÕendpointFe¯mport@3ÕendpointFf¯nport@4ÕendpointFg¯oport@5ÕendpointFh¯pport@6ÕendpointFi¯qport@7ÕendpointFj¯retm@f659c000"arm,coresight-etm4xarm,primecellÕöYÀøX apb_pclkD¯sout-portsportendpointFk¯cetm@f659d000"arm,coresight-etm4xarm,primecellÕöYÐøX apb_pclkD¯tout-portsportendpointFl¯detm@f659e000"arm,coresight-etm4xarm,primecellÕöYàøX apb_pclkD¯uout-portsportendpointFm¯eetm@f659f000"arm,coresight-etm4xarm,primecellÕöYðøX apb_pclkD¯vout-portsportendpointFn¯fetm@f65dc000"arm,coresight-etm4xarm,primecellÕö]ÀøX apb_pclkD¯wout-portsportendpointFo¯getm@f65dd000"arm,coresight-etm4xarm,primecellÕö]ÐøX apb_pclkD¯xout-portsportendpointFp¯hetm@f65de000"arm,coresight-etm4xarm,primecellÕö]àøX apb_pclkD¯yout-portsportendpointFq¯ietm@f65df000"arm,coresight-etm4xarm,primecellÕö]ðøX apb_pclkD ¯zout-portsportendpointFr¯jcti@f6403000 arm,coresight-ctiarm,primecellÕö@0øX apb_pclkcti@f6598000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY€øX apb_pclkDžscti@f6599000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY�øX apb_pclkDžtcti@f659a000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY øX apb_pclkDžucti@f659b000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY°øX apb_pclkDžvcti@f65d8000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö]€øX apb_pclkDžwcti@f65d9000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö]�øX apb_pclkDžxcti@f65da000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö] øX apb_pclkDžycti@f65db000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö]°øX apb_pclkD žzaliases¯/soc/serial@f8015000·/soc/serial@f7111000¿/soc/serial@f7112000Ç/soc/serial@f7113000chosenÏserial3:115200n8memory@0Émemory`Õàðð ïÐà`ðA¯"reserved-memory+Èramoops@21f00000ramoopsÕ!ðÛçôlinux,cmashared-dma-pool© reboot-mode-syscon@5f01000sysconsimple-mfdÕðreboot-modesyscon-reboot-mode"wfU.wfU>wfUregulator-0regulator-fixedLSYS_5V[LK@sLK@‹�¯{regulator-1regulator-fixedLVDD_3V3[2Z s2Z ‹�±{¯Nregulator-2regulator-fixedL5V_HUB[LK@sLK@‹ ¼6�±{¯9wl1835-pwrseqmmc-pwrseq-simple Á6ø ext_clockÍ ä ¯Oleds gpio-ledsled-user-1 �green:user1 {| ÷heartbeatled-user-2 �green:user2 {|÷mmc0led-user-3 �green:user3 {|÷mmc1led-user-4 �green:user4 {| ÷noneled-wlan �yellow:wlan {}÷phy0txoffled-bt�blue:bt {| ÷hci0-poweroffpmic@f8000000hisilicon,hi655x-pmicÕøÏ¨— +¯regulatorsLDO2 LLDO2_2V8[&% s0Ô6xLDO7 LLDO7_SDIO[w@s2Z 6x¯FLDO10 LLDO10_2V85[w@s-ÆÀ6h¯GLDO13 LLDO13_1V8[jsÁ06xLDO14 LLDO14_2V8[&% s0Ô6xLDO15 LLDO15_1V8[jsÁ0‹�6xLDO17 LLDO17_2V5[&% s0Ô6xLDO19 LLDO19_3V0[w@s-ÆÀ6h¯?LDO21 LLDO21_1V8[-Ps„€�6xLDO22 LLDO22_1V2[ » sO€‹�6xfirmwareopteelinaro,optee-tz=smcsound_cardaudio-graph-cardR~ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usphandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cpu-idle-states#cooling-cellsdynamic-power-coefficientcache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0dmasdma-namesstatusassigned-clocksassigned-clock-ratesenable-gpioslabel#dma-cellsdma-channelsdma-requestsdma-no-ccidma-type#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesnum-cscs-gpiosi2c-sda-hold-time-nspd-gpiosadi,dsi-lanes#sound-dai-cellsremote-endpoint#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsresetsreset-namescap-mmc-highspeednon-removablebus-widthvmmc-supplypinctrl-1card-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpioscap-power-off-cardmmc-pwrseq#thermal-sensor-cellshisilicon,sysctrl-syscondai-formatpolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentinterrupt-namesarm,cs-dev-assocserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoveryregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvin-supplygpioreset-gpiospost-power-on-delay-mspower-off-delay-uslinux,default-triggerpanic-indicatordefault-statepmic-gpiosregulator-enable-ramp-delaydais