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ì^UokayJdefaultXípwm@5d0100002fsl,imx27-pwmÂ]-ipgperÆîî hÀxn6n ì_UokayJdefaultXïpwm@5d0200002fsl,imx27-pwmÂ]-ipgperÆðð hÁxn6n ì`UokayJdefaultXñpwm@5d0300002fsl,imx27-pwmÂ]-ipgperÆòò hÂxn6n ìaUokayJdefaultXógpio@5d080000Â] 숕‰×Æ9%Ç2fsl,imx8qm-gpiofsl,imx35-gpio0Tôôô$ô`MXM3_279MXM3_277MXM3_135MXM3_203MXM3_201MXM3_275MXM3_110MXM3_120MXM3_1/GPIO1MXM3_3/GPIO2MXM3_124MXM3_122MXM3_5/GPIO3MXM3_7/GPIO4MXM3_4MXM3_211MXM3_209MXM3_2MXM3_136MXM3_134MXM3_6MXM3_8MXM3_112MXM3_118MXM3_114MXM3_116g¯gpio@5d090000Â]  쉕‰×Æ9%È2fsl,imx8qm-gpiofsl,imx35-gpio@Tô(ô2 ô?ôH}`MXM3_286MXM3_87MXM3_99MXM3_138MXM3_140MXM3_239MXM3_281MXM3_283MXM3_126MXM3_132MXM3_173MXM3_175MXM3_123g°hdmi-ctrl-hogJdefaultXõp¯yCONNECTOR_IS_HDMIƒgpio@5d0a0000Â]  슕‰×Æ9%É2fsl,imx8qm-gpiofsl,imx35-gpio0TôPôUôh ®`MXM3_198MXM3_35MXM3_164MXM3_217MXM3_215MXM3_193MXM3_194MXM3_37MXM3_271MXM3_273MXM3_195MXM3_197MXM3_177MXM3_179MXM3_181MXM3_183MXM3_185MXM3_187gÙgpio@5d0b0000Â]  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ìÀ;9%â2fsl,imx8qm-mufsl,imx6sx-mug&clock-controller@5d4000002fsl,imx8qxp-lpcgÂ]@=4Æ¿¿¿ö¿�hpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk9%¿gìclock-controller@5d4100002fsl,imx8qxp-lpcgÂ]A=4ÆÀÀÀöÀ�hpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk9%Àgîclock-controller@5d4200002fsl,imx8qxp-lpcgÂ]B=4ÆÁÁÁöÁ�hpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk9%Ágðclock-controller@5d4300002fsl,imx8qxp-lpcgÂ]C=4ÆÂÂÂöÂ�hpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk9%Âgòclock-controller@5d4400002fsl,imx8qxp-lpcgÂ]D=4ÆÃÃÃöÃ�hpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk9%Ãclock-controller@5d4500002fsl,imx8qxp-lpcgÂ]E=4ÆÄÄÄöÄ�hpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk9%Äclock-controller@5d4600002fsl,imx8qxp-lpcgÂ]F=4ÆÅÅÅöÅ�hpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk9%Åclock-controller@5d4700002fsl,imx8qxp-lpcgÂ]G=4ÆÆÆÆöÆ�hpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk9%Æclock-hsio-axi 2fixed-clock=ׄ hsio_axi_clkgclock-hsio-per 2fixed-clock=ò�U hsio_per_clkgclock-hsio-refa2gpio-gate-clockÆ÷= �¸JdefaultXøgùclock-hsio-refb2gpio-gate-clockÆù= �Ù JdefaultXúgclock-xtal100m 2fixed-clock=õá xtal_100MHzg÷bus@5f000000 2simple-bus0&__@`€p œ€€€pcie@5f0100002fsl,imx8q-pcieÂ_�ð dbiconfig0&��ø‚€€ðÆìfh msidma Æûûû -dbimstrslv§ÿ¶pci€±ijkl¿ÒÜ9%©éUokayJdefaultXüýþ  pcie-phy üÿpcie-ep@5f0100002fsl,imx8q-pcie-epÂ_€dbiaddr_spaceÒ ìh dmaÆûûû -dbimstrslv9%©é Udisabledclock-controller@5f0600002fsl,imx8qxp-lpcgÂ_ Æ= �Fhsio_pcieb_mstr_axi_clkhsio_pcieb_slv_axi_clkhsio_pcieb_dbi_axi_clk9%©gûclock-controller@5f0b00002fsl,imx8qxp-lpcgÂ_ Æ=�hsio_phyx1_per_clk9%«g clock-controller@5f0d00002fsl,imx8qxp-lpcgÂ_ Æ=�hsio_pcieb_per_clk9%©g clock-controller@5f0f00002fsl,imx8qxp-lpcgÂ_Æ=�hsio_misc_per_clk9%¬gpcie@5f0000002fsl,imx8q-pcieÂ_Oð dbiconfig0&�Oø‚@@ðÆ ìF msi Æ -dbimstrslv§ÿ¶pci€±IJKL¿ÒÜ9%˜éUokayJdefaultXþ  pcie-phy ü¯%pcie-ep@5f0000002fsl,imx8q-pcie-epÂ_@dbiaddr_spaceÒ ìH dmaÆ -dbimstrslv9%˜é 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