Ð þí+À8(D(|( "amd,seattle-overdriveamd,seattle +37AMD Seattle (Rev.B1) Development Board (Overdrive)clock-100000000 fixed-clock=JõáZadl3clk_100mhzmclock-375000000 fixed-clock=JZ ÀZccpclk_375mhzclock-333000000 fixed-clock=JÙ-@Zsataclk_333mhzmclock-500000000 fixed-clock=JÍeZpcieclk_500mhzclock-250000000 fixed-clock=Jæ²€Zmiscclk_250mhzminterrupt-controller@e1101000arm,gic-400arm,cortex-a15-gicuŠ+@›ááð á á  Ÿ ªámv2m@e0080000arm,gic-v2m-frame±›mtimerarm,armv8-timer0Ÿ ÿÿ ÿ ÿbus simple-bus+ªÀsata@e0300000snps,dwc-ahci›à0 ŸcË ÒÙsata@e0d00000æokaysnps,dwc-ahci›àÐ ŸbËÒÙiommu@e0200000 arm,mmu-401›à íŸLLÙmiommu@e0c00000 arm,mmu-401›àÀíŸKKÙmi2c@e1000000æokaysnps,designware-i2c›á ŸeËi2c@e0050000æokaysnps,designware-i2c›à ŸTËserial@e1010000arm,pl011arm,primecell›á ŸHË uartclkapb_pclkspi@e1020000æokayarm,pl022arm,primecell›á ŸJË sspclkapb_pclkspi@e1030000æokayarm,pl022arm,primecell›á ŸIË sspclkapb_pclk+mmc@0 mmc-spi-slot› 1-2 € HAQ`tgpio@e1040000 ædisabledarm,pl061arm,primecellˆ›á” ŸguŠË  apb_pclkgpio@e1050000æokayarm,pl061arm,primecellˆ›á”uŠ ŸfË  apb_pclkgpio@e0020000æokayarm,pl061arm,primecellˆ›à”uŠ ŸnË  apb_pclkgpio@e0030000æokayarm,pl061arm,primecellˆ›à”uŠ ŸmË  apb_pclkgpio@e0080000æokayarm,pl061arm,primecellˆ›à”uŠ ŸiË  apb_pclkccp@e0100000æokayamd,ccp-seattle-v1a›à ŸÙ Ò@Bpcie@f0000000pci-host-ecam-generic+Фpci°º›ðÅÿàØ !"#$%&'()*+ÙÀCTªïÿ@@€ææokayiommu@e0a00000 arm,mmu-401›à íŸMMÙmccn@e8000000 arm,ccn-504›è Ÿ|kcs@e0010000æokay ipmi-kcs¤ipmi›à Ÿ…ðùethernet@e0700000amd,xgbe-seattle-v1aP›àpàxá$á%`á%øHŸEZ[\]C - = Q  d v �ª¡¢£¤¥Ë dma_clkptp_clk¶xgmii Ò Ùethernet@e0900000amd,xgbe-seattle-v1aP›à�à˜á$ á%€`á%üHŸDUVWXB - = Q  d v �ª±²³´µË dma_clkptp_clk¶xgmii Ò Ùiommu@e0600000 arm,mmu-401›à`íŸPPÙm iommu@e0800000 arm,mmu-401›à€íŸOOÙm cpus+cpu-mapcluster0core0¿ core1¿ cluster1core0¿ core1¿cluster2core0¿core1¿cluster3core0¿core1¿cpu@0¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)m cpu@1¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)m cpu@100¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)m cpu@101¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)mcpu@200¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)mcpu@201¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)mcpu@300¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)mcpu@301¤cpuarm,cortex-a57›ÃpsciÑÀÞ@ðý€ @)ml2-cache0Óà@ò2@ml2-cache1Óà@ò2@ml2-cache2Óà@ò2@ml2-cache3Óà@ò2@ml3-cacheQÓ€à@ò 2mpmuarm,cortex-a57-pmu`Ÿ      ] chosenp/bus/serial@e1010000psci arm,psci-0.2Êsmc compatibleinterrupt-parent#address-cells#size-cellsmodel#clock-cellsclock-frequencyclock-output-namesphandleinterrupt-controller#interrupt-cellsreginterruptsrangesmsi-controllerdma-rangesclocksiommusdma-coherentstatus#global-interrupts#iommu-cellsclock-namesnum-csspi-max-frequencyvoltage-rangespl022,interfacepl022,com-modepl022,rx-level-trigpl022,tx-level-trig#gpio-cellsgpio-controllerdevice_typebus-rangemsi-parentinterrupt-map-maskinterrupt-mapiommu-mapreg-sizereg-spacingamd,per-channel-interruptamd,speed-setamd,serdes-blwcamd,serdes-cdr-rateamd,serdes-pq-skewamd,serdes-tx-ampamd,serdes-dfe-tap-configamd,serdes-dfe-tap-enablemac-addressphy-modecpuenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsl2-cachecache-unifiednext-level-cachecache-levelinterrupt-affinitystdout-path