Ð þí=*8:("9Ð)STMicroelectronics STM32F746-DISCO board !st,stm32f746-discost,stm32f746interrupt-controller@e000e100!arm,armv7m-nvic,ARàá Vtimer@e000e010!arm,armv7m-systickRàà^okay esoc !simple-busl}timer@40000000!st,stm32-timerR@„ e€ ^disabledtimers@40000000!st,stm32-timersR@ e€�int ^disabledpwm !st,stm32-pwm› ^disabledtimer@1!st,stm32-timer-triggerR ^disabledtimer@40000400!st,stm32-timerR@„ e� ^disabledtimers@40000400!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm› ^disabledtimer@2!st,stm32-timer-triggerR ^disabledtimer@40000800!st,stm32-timerR@„ e‚ ^disabledtimers@40000800!st,stm32-timersR@ e‚�int ^disabledpwm !st,stm32-pwm› ^disabledtimer@3!st,stm32-timer-triggerR ^disabledtimer@40000c00!st,stm32-timerR@ „2 eƒtimers@40000c00!st,stm32-timersR@  eƒ�int ^disabledpwm !st,stm32-pwm› ^disabledtimer@4!st,stm32-timer-triggerR ^disabledtimer@40001000!st,stm32-timerR@„6 e„ ^disabledtimers@40001000!st,stm32-timersR@ e„�int ^disabledtimer@5!st,stm32-timer-triggerR ^disabledtimer@40001400!st,stm32-timerR@„7 e… ^disabledtimers@40001400!st,stm32-timersR@ e…�int ^disabledtimer@6!st,stm32-timer-triggerR ^disabledtimers@40001800!st,stm32-timersR@ e†�int ^disabledpwm !st,stm32-pwm› ^disabledtimer@11!st,stm32-timer-triggerR  ^disabledtimers@40001c00!st,stm32-timersR@ e‡�int ^disabledpwm !st,stm32-pwm› ^disabledtimers@40002000!st,stm32-timersR@  eˆ�int ^disabledpwm !st,stm32-pwm› ^disabledrtc@40002800 !st,stm32-rtcR@( e ¦ ¶l„ Í ^disabledserial@40004400!st,stm32f7-uartR@D„& e ^disabledserial@40004800!st,stm32f7-uartR@H„' e ^disabledserial@40004c00!st,stm32f7-uartR@L„4 e ^disabledserial@40005000!st,stm32f7-uartR@P„5 e ^disabledi2c@40005400!st,stm32f7-i2cR@T„ × e^okayÞèdefaultö¹ i2c@40005800!st,stm32f7-i2cR@X„!"× e ^disabledi2c@40005c00!st,stm32f7-i2cR@\„HI× e ^disabledi2c@40006000!st,stm32f7-i2cR@`„_`× e ^disabledcec@40006c00 !st,stm32-cecR@l„^e› �cechdmi-cec ^disabledserial@40007800!st,stm32f7-uartR@x„R e ^disabledserial@40007c00!st,stm32f7-uartR@|„S e ^disabledtimers@40010000!st,stm32-timersR@ e �int ^disabledpwm !st,stm32-pwm› ^disabledtimer@0!st,stm32-timer-triggerR ^disabledtimers@40010400!st,stm32-timersR@ e¡�int ^disabledpwm !st,stm32-pwm› ^disabledtimer@7!st,stm32-timer-triggerR ^disabledserial@40011000!st,stm32f7-uartR@„% e^okayÞèdefaultserial@40011400!st,stm32f7-uartR@„G e ^disabledsdio2@40011c00!arm,pl180arm,primecell%ˆ€R@ e§ �apb_pclk„g<Ül ^disabledsdio1@40012c00!arm,pl180arm,primecell%ˆ€R@, e« �apb_pclk„1<Ül^okayJ V èdefaultopendrainÞ _ isyscon@40013800!st,stm32-syscfgsysconR@8Vinterrupt-controller@40013c00!st,stm32-exti,AR@<8„ ()*>LVtimers@40014000!st,stm32-timersR@@ e°�int ^disabledpwm !st,stm32-pwm› ^disabledtimer@8!st,stm32-timer-triggerR ^disabledtimers@40014400!st,stm32-timersR@D e±�int ^disabledpwm !st,stm32-pwm› ^disabledtimers@40014800!st,stm32-timersR@H e²�int ^disabledpwm !st,stm32-pwm› ^disabledpower-config@40007000!st,stm32-power-configsysconR@pVcrc@40023000!st,stm32f7-crcR@0 e  ^disabledrcc@40023800s€!st,stm32f746-rccst,stm32-rccR@8e Í ¦�B@Vdma-controller@40026000 !st,stm32-dmaR@` „ / e¢ ^disableddma-controller@40026400 !st,stm32-dmaR@d „89:;<DEF e¢­ ^disabledusb@40040000!st,stm32f7-hsotgR@„M e�otg¸Ç  Ù€€@@@@ ^okayèhostð  õusb2-phyÞèdefaultusb@50000000!st,stm32f4x9-fsotgRP„C e'�otg^okayèhostÞèdefaultpin-controller }@0lÍÿ!st,stm32f746-pinctrlgpio@40020000!,AR e-GPIOAgpio@40020400!,AR e-GPIOBgpio@40020800!,AR e-GPIOCVgpio@40020c00!,AR  e-GPIODVgpio@40021000!,AR e-GPIOEgpio@40021400!,AR e-GPIOFgpio@40021800!,AR e-GPIOGgpio@40021c00!,AR e-GPIOHgpio@40022000!,AR  e-GPIOIgpio@40022400!,AR$ e -GPIOJgpio@40022800!,AR( e -GPIOKcec-0pins:AK\usart1-0pins1: \iApins2: \usart1-1Vpins1: \iApins2:\i2c1-0Vpins:\KAusbotg-hs-0pins0:t ‹          \iAusbotg-hs-1Vpins0:t "          \iAusbotg-fs-0Vpins : \iAsdio-pins-a-0V pins:( ) * + , 2 iAsdio-pins-od-a-0V pins1:( ) * + , iApins2:2 KAsdio-pins-b-0pins:i j   6 7 iAsdio-pins-od-b-0pins1:i j   6 iApins2:7 KAcan1-0pins1: pins2: ycan1-1pins1: pins2: ycan1-2pins1:1 pins2:0 ycan1-3pins1:} pins2:~ ycan2-0pins1: pins2: ycan2-1pins1: pins2: ycan3-0pins1: pins2: ycan3-1pins1: pins2: yclocksclk-hse€ !fixed-clock†}x@V clk-lse€ !fixed-clock†€clk-lsi€ !fixed-clock†}clk-i2s-ckin€ !fixed-clock†ÜlV chosen–root=/dev/ramŸserial0:115200n8memory@c0000000«memoryRÀ€aliases·/soc/serial@40011000usb-phy¿!usb-nop-xceiv e �main_clkV vcc5v-otg-fs-regulator!regulator-fixed Ê Ïvcc5_host1Þmmc_vcard!regulator-fixed Ïmmc_vcardò2Z  2Z V #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclocksinterrupt-parentrangesinterruptsclock-names#pwm-cellsassigned-clocksassigned-clock-parentsst,syscfgresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-nsarm,primecell-periphidmax-frequencyvmmc-supplycd-gpiospinctrl-1bus-width#reset-cells#clock-cellsassigned-clock-rates#dma-cellsst,mem2memg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modephysphy-namespins-are-numberedgpio-controller#gpio-cellsst,bank-namepinmuxslew-ratedrive-open-drainbias-disabledrive-push-pullbias-pull-upclock-frequencybootargsstdout-pathdevice_typeserial0#phy-cellsgpioregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvolt