Ð þíJ38C¸({C€ elgin,rv1108-r1rockchip,rv1108&7Elgin RV1108 R1 boardaliases=/i2c@20000000B/i2c@10240000G/i2c@10250000L/i2c@10260000Q/serial@10230000Y/serial@10220000a/serial@10210000cpuscpu@f00icpuarm,cortex-a7uyœ@‡Ž�K·ËÖopp_tableoperating-points-v2Öopp-408000000ÞQ–åà˜óœ@opp-600000000Þ#ÃFåà˜óœ@opp-816000000Þ0£,å£èóœ@opp-1008000000Þ<ÜåŒ0óœ@arm-pmuarm,cortex-a7-pmu Ltimerarm,armv7-timer 3n6oscillator fixed-clock3n6Cxin24mVÖbus simple-buscpdma@102a0000arm,pl330arm,primecellu*@ ju�‡À §apb_pclkÖsram@10080000 mmio-sramu  c serial@10210000&rockchip,rv1108-uartsnps,dw-apb-uartu! .³½3n6‡J §baudclkapb_pclkÊÏdefaultÝçokayserial@10220000&rockchip,rv1108-uartsnps,dw-apb-uartu" -³½3n6‡I §baudclkapb_pclkÊÏdefaultÝ çdisabledserial@10230000&rockchip,rv1108-uartsnps,dw-apb-uartu# ,³½3n6‡H §baudclkapb_pclkÊÏdefaultÝçokayi2c@10240000rockchip,rv1108-i2cu$ ‡v §i2cpclkÏdefaultÝ î  çdisabledi2c@10250000rockchip,rv1108-i2cu%  ‡w §i2cpclkÏdefaultÝ î  çdisabledi2c@10260000rockchip,rv1108-i2cu& !‡x §i2cpclkÏdefaultÝ î  çdisabledspi@10270000rockchip,rv1108-spiu' %‡l§spiclkapb_pclkÊ ûtxrxçokayÏdefaultÝ dac@0rohm,dh2228fvun6 pwm@10280000(rockchip,rv1108-pwmrockchip,rk3288-pwmu( &‡y  §pwmpclkÏdefaultÝ) çdisabledpwm@10280010(rockchip,rv1108-pwmrockchip,rk3288-pwmu( &‡y  §pwmpclkÏdefaultÝ) çdisabledpwm@10280020(rockchip,rv1108-pwmrockchip,rk3288-pwmu(  &‡y  §pwmpclkÏdefaultÝ) çdisabledpwm@10280030(rockchip,rv1108-pwmrockchip,rk3288-pwmu(0 &‡y  §pwmpclkÏdefaultÝ) çdisabledsyscon@10300000&rockchip,rv1108-grfsysconsimple-mfdu0Ö usb2-phy@100rockchip,rv1108-usb2phyu ‡{§phyclkVCusbphy4çokayÖ+otg-port 0Dotg-muxTçokayÖ-host-port 3 DlinestateTçokayÖ,timer@10350000,rockchip,rv1108-timerrockchip,rk3288-timeru5  # ‡ §timerpclkwdt@10360000 snps,dw-wdtu6 "‡ §pclk_wdt çdisabledthermal-zonessoc-thermal_uèƒ2•tripstrip-point0¥p±Ðppassivetrip-point1¥L±ÐppassiveÖsoc-crit¥s±Ð pcriticalcooling-mapsmap0¼ ÁÿÿÿÿÿÿÿÿÐtsadc@10370000rockchip,rv1108-tsadcu7 /Ýní q°‡n §tsadcapb_pclkÏinitdefaultsleepÝ H tsadc-apb)ÔÀ@ çdisabledÖadc@1038c000.rockchip,rv1108-saradcrockchip,rk3399-saradcu8À V‡m§saradcapb_pclk çdisabledi2c@20000000rockchip,rv1108-i2cu  ‡[ §i2cpclkÏdefaultÝî çokay3€hpmic@18rockchip,rk805u& —¸ÄÐÜèôregulatorsDCDC_REG1 vdd_core ®`'ã`?SÖregulator-state-meme} » DCDC_REG2 vdd_buck2!‘À'!‘À?SÖregulator-state-mem™DCDC_REG3vcc_ddr?Sregulator-state-memeDCDC_REG4vcc_io2Z '2Z ?Sregulator-state-meme}2Z LDO_REG1vdd_10B@'B@?Sregulator-state-mem™LDO_REG2vcc_18w@'w@?Sregulator-state-mem™LDO_REG3 vdd10_pmuB@'B@?Sregulator-state-meme}B@pwm@20040000(rockchip,rv1108-pwmrockchip,rk3288-pwmu  '‡Z §pwmpclkÏdefaultÝ ) çdisabledpwm@20040010(rockchip,rv1108-pwmrockchip,rk3288-pwmu  '‡Z §pwmpclkÏdefaultÝ!) çdisabledpwm@20040020(rockchip,rv1108-pwmrockchip,rk3288-pwmu   '‡Z §pwmpclkÏdefaultÝ") çdisabledpwm@20040030(rockchip,rv1108-pwmrockchip,rk3288-pwmu 0 '‡Z §pwmpclkÏdefaultÝ#) çdisabledsyscon@20060000rockchip,rv1108-pmugrfsysconu Ö0syscon@202a0000rockchip,rv1108-usbgrfsysconu *Öclock-controller@20200000rockchip,rv1108-cruu î V²Ömmc@301100000rockchip,rv1108-dw-mshcrockchip,rk3288-dw-mshcu0@   ‡FGSV§biuciuciu-driveciu-sample¿ ðÑ€çokayÊÔæìôÏdefault Ý$%&mmc@301200000rockchip,rv1108-dw-mshcrockchip,rk3288-dw-mshcu0@   ‡EERU§biuciuciu-driveciu-sample¿ ðÑ€ çdisabledmmc@301300000rockchip,rv1108-dw-mshcrockchip,rk3288-dw-mshcu0@   ‡DDQT§biuciuciu-driveciu-sample¿ õáÏdefaultÝ'()* çdisabledusb@30140000 generic-ehciu0  ‡S+,#usbçokayusb@30160000 generic-ohciu0  ‡S+,#usbçokayusb@301800002rockchip,rv1108-usbrockchip,rk3066-usbsnps,dwc2u0 ‡T§otg-otg5GV€€@ - #usb2-phyçokayeth@30200000rockchip,rv1108-gmacu0 Dmacirqeth_wake_irq8‡pqqrsÒM§stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macermiiÏdefaultÝ.î çokaynoutput {/‹interrupt-controller@32010000 arm,gic-400¡¶ u22 2@ 2`   Öpinctrlrockchip,rv1108-pinctrlî Ç0cgpio0@20030000rockchip,gpio-banku  (‡Ôä¡¶Ögpio1@10310000rockchip,gpio-banku1 )‡Ôä¡¶Ö/gpio2@10320000rockchip,gpio-banku2 *‡Ôä¡¶gpio3@10330000rockchip,gpio-banku3 +‡Ôä¡¶pcfg-pull-upðÖ6pcfg-pull-downýpcfg-pull-none Ö3pcfg-pull-none-drv-8maÖ2pcfg-pull-none-drv-12ma Ö4pcfg-pull-none-smt (Ö5pcfg-pull-up-drv-8maðÖ1pcfg-pull-none-drv-4maÖ7pcfg-pull-up-drv-4maðÖ8pcfg-output-high=pcfg-output-lowIpcfg-input-highðTemmcemmc-bus8€a11111111Ö&emmc-clka2Ö$emmc-cmda 1Ö%gmacrmii-pins a333 4 4 4 3333Ö.i2c0i2c0-xfer a 5 5Öi2c1i2c1-xfer a66Ö i2c2m1i2c2m1-xfer a33Ö i2c2m1-pins a33i2c2m05vi2c2m05v-xfer a33i2c2m05v-pins a33i2c3i2c3-xfer a33Ö pwm0pwm0-pina3Ö pwm1pwm1-pina3Ö!pwm2pwm2-pina3Ö"pwm3pwm3-pina3Ö#pwm4pwm4-pina3Öpwm5pwm5-pina3Öpwm6pwm6-pina3Öpwm7pwm7-pina 3Ösdmmcsdmmc-clka7Ö'sdmmc-cmda8Ö(sdmmc-cda8Ö)sdmmc-bus1a8sdmmc-bus4@a8888Ö*spim0spim0-clka6spim0-cs0a6spim0-txa6spim0-rxa6spim1spim1-clka6Ö spim1-cs0a6Öspim1-rxa6Öspim1-txa6Ötsadcotp-outa3Öotp-pina3Öuart0uart0-xfer a63Öuart0-ctsa3uart0-rtsa3uart0-rts-pina3uart1uart1-xfer a63Öuart1-ctsa3uart1-rtsa3uart2m0uart2m0-xfer a63Öuart2m1uart2m1-xfer a63uart2_5vuart2_5v-ctsa3uart2_5v-rtsa3memory@60000000imemoryu`chosenoserial2:1500000n8vsys-regulatorregulator-fixedvsysLK@'LK@SÖ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3serial0serial1serial2device_typeregclock-latencyclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-supplyphandleopp-hzopp-microvoltclock-latency-nsinterruptsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesreg-shiftreg-io-widthdmaspinctrl-namespinctrl-0statusrockchip,grfdma-namesspi-max-frequencyspi-cphaspi-cpol#pwm-cellsrockchip,usbgrfinterrupt-names#phy-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-1pinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cells#io-channel-cellsi2c-scl-rising-time-nsi2c-scl-falling-time-nsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspend#reset-cellsfifo-depthbus-widthcap-mmc-highspeedno-sdno-sdionon-removablemmc-ddr-1_8vmmc-hs200-1_8vphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-path