<8( `google,veyron-tiger-rev8google,veyron-tiger-rev7google,veyron-tiger-rev6google,veyron-tiger-rev5google,veyron-tiger-rev4google,veyron-tiger-rev3google,veyron-tiger-rev2google,veyron-tiger-rev1google,veyron-tiger-rev0google,veyron-tigergoogle,veyronrockchip,rk3288& 7Google Tigeraliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbcpu-opp-tableoperating-points-v2jbopp-126000000u| opp-216000000u | opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ|opp-1608000000u_"| opp-1704000000ue|popp-1800000000ukI|\bus simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkbdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkbfreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n65timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystemL mmc@ff0c0000rockchip,rk3288-dw-mshcRр 5Drvbiuciuciu-driveciu-sample`  @kreset disabledmmc@ff0d0000rockchip,rk3288-dw-mshcRр 5Eswbiuciuciu-driveciu-sample` ! @kresetokayw default  'btmrvl@2marvell,sd8897-bt&4 defaultmmc@ff0e0000rockchip,rk3288-dw-mshcRр 5Ftxbiuciuciu-driveciu-sample` "@kreset disabledmmc@ff0f0000rockchip,rk3288-dw-mshcRр 5Guybiuciuciu-driveciu-sample` #@kresetokaywGYwdefault saradc@ff100000rockchip,saradc $5I[saradcapb_pclkW ksaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -default ! disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .default"#$%okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault&okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault'okay2,touchscreen@10elan,ekth3500&(default)* (*+7+Di2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault,okay2,ts3a227e@3b ti,ts3a227e;&-default.Rbi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault/ disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7]g5MUbaudclkapb_pclktxrxdefault 012okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8]g5NVbaudclkapb_pclktxrxdefault3okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9]g5OWbaudclkapb_pclkdefault4okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :]g5PXbaudclkapb_pclktxrxdefault5 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;]g5QYbaudclkapb_pclk  txrxdefault6 disabledthermal-zonesreserve_thermalt7cpu_thermaltd7tripscpu_alert0ppassiveb8cpu_alert1$passiveb9cpu_crit criticalcooling-mapsmap080map190gpu_thermaltd7tripsgpu_alert04passiveb:gpu_crit criticalcooling-mapsmap0: ;tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk ktsadc-apbinitdefaultsleep<=<> Hokay!8b7ethernet@ff290000rockchip,rk3288-gmac)Smacirqeth_wake_irq>85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB kstmmacethokaycs?input@rgmiiAdefaultBCDE0  'u0Dmdio0snps,dwmac-mdioethernet-phy@1b@usb@ff500000 generic-ehciP 5Fusbokayusb@ff520000 generic-ohciR )5Fusb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otg(hostG usb2-phy0okayGusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg(host^p@@ H usb2-phyokayczsHGusb@ff5c0000 generic-ehci\ 5 disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultIokay2dpmic@1brockchip,rk808xin32kwifibt_32kin&-default JKLD+*M M4NbregulatorsDCDC_REG1Avdd_armPdv q qb regulator-state-memDCDC_REG2Avdd_gpuPdv 5qbregulator-state-memDCDC_REG3 Avcc135_ddrPdregulator-state-memDCDC_REG4Avcc_18Pdvw@w@bregulator-state-memw@LDO_REG3Avdd_10PdvB@B@regulator-state-memB@LDO_REG7 Avdd10_lcdPdvB@B@regulator-state-memSWITCH_REG1 Avcc33_lcdPdbdregulator-state-memLDO_REG6 Avcc18_codecPdvw@w@beregulator-state-memLDO_REG2Pdvw@w@ Avdd18_lcdtregulator-state-memLDO_REG8Pdv2Z2Z Avcc33_ccdregulator-state-memSWITCH_REG2 Avcc33_lanbAi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultOokay2 max98090@10maxim,max98090&Pmclk5qdefaultQbpwm@ff680000rockchip,rk3288-pwmhdefaultR5_pwmokaybpwm@ff680010rockchip,rk3288-pwmhdefaultS5_pwmokaybpwm@ff680020rockchip,rk3288-pwmh defaultT5_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultU5_pwm disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerchs bipower-domain@9 5chgfdehilkj$'VWXYZ[\]^power-domain@11 5op'_`power-domain@12 5'apower-domain@13 5'bcreboot-modesyscon-reboot-mode.5RBARBORB _RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv>kHcjk$x#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb>edp-phyrockchip,rk3288-dp-phy5h24mokaybyio-domains"rockchip,rk3288-io-voltage-domainokay+++deusbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclk kphy-resetbHusb-phy@33445^phyclk kphy-resetbFusb-phy@348H5_phyclk kphy-resetbGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif5T mclkhclkftx 6defaultg> disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 55Ri2s_clki2s_hclkfftxrxdefaulth  *okaybcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk kcrypto-rstokayiommu@ff900800rockchip,iommu@ Siep_mmu5 aclkiface D disablediommu@ff914000rockchip,iommu @P Sisp_mmu5 aclkiface D Q disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk li ilm kcoreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop li def kaxiahbdclk zjokayportb endpoint@0 kbendpoint@1 lb{endpoint@2 mbtendpoint@3 nbwiommu@ff930300rockchip,iommu  Svopb_mmu5 aclkiface li  Dokaybjvop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop li  kaxiahbdclk zookayportb endpoint@0 pbendpoint@1 qb|endpoint@2 rbuendpoint@3 sbxiommu@ff940300rockchip,iommu  Svopl_mmu5 aclkiface li  Dokaybomipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk li > disabledportsportendpoint@0 tbmendpoint@1 ubrlvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcv li > disabledportsport@0endpoint@0 wbnendpoint@1 xbsdp@ff970000rockchip,rk3288-dp@ b5icdppclkydp li okdp>okaydefaultzportsport@0endpoint@0 {blendpoint@1 |bqport@1endpoint@0 }bhdmi@ff980000rockchip,rk3288-dw-hdmig> g5hmniahbisfrcec li okaydefaultunwedge~bportsportendpoint@0 bkendpoint@1 bpvideo-codec@ff9a0000rockchip,rk3288-vpu   Svepuvdpu5 aclkhclk z li iommu@ff9a0800rockchip,iommu Svpu_mmu5 aclkiface D li biommu@ff9c0440rockchip,iommu @@@ o Shevc_mmu5 aclkiface D disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Sjobmmugpu5 li okay b;gpu-opp-tableoperating-points-v2bopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000syscon bbqos@ffaa0080syscon bcqos@ffad0000syscon bWqos@ffad0100syscon bXqos@ffad0180syscon bYqos@ffad0400syscon bZqos@ffad0480syscon b[qos@ffad0500syscon bVqos@ffad0800syscon b\qos@ffad0880syscon b]qos@ffad0900syscon b^qos@ffae0000syscon baqos@ffaf0000syscon b_qos@ffaf0080syscon b`efuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   bpinctrlrockchip,rk3288-pinctrl>defaultsleepgpio0@ff750000rockchip,gpio-banku Q5@     PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LHUB_USB1_nFALUTPHY_PMEBPHY_INTRECOVERY_SW_LOTP_OUTUSB_OTG_POWER_ENAP_WARM_RESET_HUSB_OTG_nFALUTI2C0_SDA_PMICI2C0_SCL_PMICDEVMODE_LUSB_INTb-gpio1@ff780000rockchip,gpio-bankx R5A    gpio2@ff790000rockchip,gpio-banky S5B    i CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPb(gpio3@ff7a0000rockchip,gpio-bankz T5C     FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7VCC5V_GOOD_HFLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOPHY_TXD2PHY_TXD3MAC_RXD2MAC_RXD3PHY_TXD0PHY_TXD1MAC_RXD0MAC_RXD1gpio4@ff7b0000rockchip,gpio-bank{ U5D     MAC_MDCMAC_RXDVMAC_RXERMAC_CLKPHY_TXENMAC_MDIOMAC_RXCLKPHY_RSTPHY_TXCLKUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEbgpio5@ff7c0000rockchip,gpio-bank| V5E     USB_OTG_CTL1HUB_USB2_CTL1HUB_USB2_PWR_ENHUB_USB_ILIM_SELUSB_OTG_STATUS_LHUB_USB1_CTL1HUB_USB1_PWR_ENVCC50_HDMI_ENbgpio6@ff7d0000rockchip,gpio-bank} W5F     I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETHUB_USB2_nFALUTUSB_OTG_ILIM_SELbPgpio7@ff7e0000rockchip,gpio-bank~ X5G     LCD_BL_PWMPWM_LOGBL_ENPWR_LED1TPM_INT_HSPK_ONAP_FLASH_WP_LCPU_NMIDVSOKEDP_HPDDVS1LCD_ENDVS2HDMI_CECI2C4_SDAI2C4_SCLI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDbMgpio8@ff7f0000rockchip,gpio-bank Y5H    ^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc b~hdmi-ddc-unwedge bvcc50-hdmi-en bpcfg-output-low bpcfg-pull-up bpcfg-pull-down bpcfg-pull-none $bpcfg-pull-none-12ma $ 1 bsuspendglobal-pwroff bddrio-pwroff bddr0-retention bddr1-retention edpedp-hpd  bzi2c0i2c0-xfer bIi2c1i2c1-xfer b&i2c2i2c2-xfer   bOi2c3i2c3-xfer b'i2c4i2c4-xfer b,i2c5i2c5-xfer b/i2s0i2s0-bus` bhlcdclcdc-ctl@ bvsdmmcsdmmc-clk sdmmc-cmd sdmmc-cd sdmmc-bus1 sdmmc-bus4@ sdio0sdio0-bus1 sdio0-bus4@ bsdio0-cmd bsdio0-clk bsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h bbt-enable-l bt-host-wake bt-host-wake-l bbt-dev-wake-sleep bbt-dev-wake-awake bbt-dev-wake sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk bemmc-cmd bemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 bemmc-reset  bspi0spi0-clk  bspi0-cs0  bspi0-tx bspi0-rx bspi0-cs1 spi1spi1-clk  bspi1-cs0  b!spi1-rx b spi1-tx bspi2spi2-cs1 spi2-clk b"spi2-cs0 b%spi2-rx b$spi2-tx  b#uart0uart0-xfer b0uart0-cts b1uart0-rts b2uart1uart1-xfer  b3uart1-cts  uart1-rts  uart2uart2-xfer b4uart3uart3-xfer b5uart3-cts  uart3-rts  uart4uart4-xfer b6uart4-cts  uart4-rts  tsadcotp-pin b<otp-out b=pwm0pwm0-pin bRpwm1pwm1-pin bSpwm2pwm2-pin bTpwm3pwm3-pin bUgmacrgmii-pins  bBrmii-pins phy-rst bCphy-pmeb bDphy-int bEspdifspdif-tx  bgpcfg-pull-none-drv-8ma $ 1bpcfg-pull-up-drv-8ma  1pcfg-output-high @bbuttonspwr-key-l bpmicpmic-int-l bJdvs-1  bKdvs-2 bLrebootap-warm-reset-h brecovery-switchrec-mode-l tpmtpm-int-h write-protectfw-wp-ap codechp-det bint-codec bQmic-det  bheadsetts3a227e-int-l b.buck-5vdrv-5v bledspwr-led1-on bpwr-led1-blink busb-bc12usb-otg-ilim-sel busb-usb-ilim-sel busb-hosthub_usb1_pwr_en bhub_usb2_pwr_en busb_otg_pwr_en bbacklightbl_pwr_en  bbl-en blcdlcd-en btouchscreentouch-int b)touch-rst b*chosen Lserial2:115200n8memorymemorypower-button gpio-keysdefaultpower XPower $- ^t idDgpio-restart gpio-restart $- default {emmc-pwrseqmmc-pwrseq-emmcdefault ( bsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault b vcc-5vregulator-fixedAvcc_5vPdvLK@LK@  MdefaultbNvcc33-sysregulator-fixed Avcc33_sysPdv2Z2Zbvcc50-hdmiregulator-fixed Avcc50_hdmiPd N  defaultvdd-logicpwm-regulator Avdd_logic   { Pdv~psound!rockchip,rockchip-audio-max98090default VEYRON-I2S   P +P  B Yvccsysregulator-fixedAvccsysdPbvcc33-ioregulator-fixedPd Avcc33_iob+vcc5-host1-regulatorregulator-fixed  default Avcc5_host1Pdvcc5-host2-regulatorregulator-fixed  default Avcc5_host2Pdvcc5v-otg-regulatorregulator-fixed  - default Avcc5_otgPdexternal-gmac-clock fixed-clocksY@ ext_gmacb?backlight-regulatorregulator-fixed  ( defaultAbacklight_regulator  m:bpanel-regulatorregulator-fixed  MdefaultApanel_regulator bbacklightpwm-backlight ~   Mdefault B@   bpanelauo,b101ean01okay  panel-timing@    +  5  = J Vportsportendpoint b} #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymarvell,wakeup-pincap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreset-gpiosvcc33-supplyvccio-supplywakeup-sourceti,micbiasreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplyrx_delaytx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityenable-active-highvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenvactivevfront-porchvback-porchvsync-len