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ÜFGH:HT`lx„�I�J J§bŠregulatorsDCDC_REG1´vdd_armÃ×é q° qb regulator-state-mem.DCDC_REG2´vdd_gpuÃ×é 5Ðqb{regulator-state-mem.DCDC_REG3 ´vcc135_ddrÃ×regulator-state-memGDCDC_REG4´vcc_18Ã×éw@w@bregulator-state-memG_w@LDO_REG3´vdd_10Ã×éB@B@regulator-state-memG_B@LDO_REG7 ´vdd10_lcdÃ×éB@B@{SWITCH_REG1 ´vcc33_lcdÃ×b^regulator-state-mem.LDO_REG8Ã×éw@w@ ´vcc18_lcd{i2c@ff660000rockchip,rk3288-i2cùÿf ´=Îi2c5NÎdefaultÜK ÚdisabledᆠÄ2Ü pwm@ff680000rockchip,rk3288-pwmùÿhšÎdefaultÜL5_Îpwm Údisabledpwm@ff680010rockchip,rk3288-pwmùÿhšÎdefaultÜM5_ÎpwmÚokaybŽpwm@ff680020rockchip,rk3288-pwmùÿh šÎdefaultÜN5_Îpwm Údisabledpwm@ff680030rockchip,rk3288-pwmùÿh0šÎdefaultÜO5_Îpwm Údisabledsram@ff700000 mmio-sramùÿp€Šÿp€smp-sram@0rockchip,rk3066-smp-sramùsram@ff720000#rockchip,rk3288-pmu-srammmio-sramùÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdùÿsbpower-controller!rockchip,rk3288-power-controller¥òh bbpower-domain@9ù È5ÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkj$¹PQRSTUVWXpower-domain@11ù 5Ïop¹YZpower-domain@12ù 5Ðܹ[power-domain@13ù 5À¹\]reboot-modesyscon-reboot-modeÀ”ÇRBÃÓRBÃáRBà ñRBÃsyscon@ff740000rockchip,rk3288-sgrfsysconùÿtclock-controller@ff760000rockchip,rk3288-cruùÿv@ýHòÑÝjÒÞk$ #g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdùÿwb@edp-phyrockchip,rk3288-dp-phy5hÎ24m Údisabledbrio-domains"rockchip,rk3288-io-voltage-domainÚokay*I4?MI]Ik^wusbphyrockchip,rk3288-usb-phyÚokayusb-phy@320ù 5]Îphyclký… kphy-resetbCusb-phy@334ù45^Îphyclkýˆ kphy-resetbAusb-phy@348ùH5_Îphyclký‹ kphy-resetbBwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdtùÿ€5p ´OÚokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifùÿ‹ƒ5TÐ Îmclkhclk�_•tx ´6ÎdefaultÜ`@ Údisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sùÿ‰ƒ ´55RÎÎi2s_clki2s_hclk�__•txrxÎdefaultÜa”¯Úokayb�crypto@ff8a0000rockchip,rk3288-cryptoùÿŠ@ ´0 5ÇÍ}ÁÎaclkhclksclkapb_pclký® kcrypto-rstÚokayiommu@ff900800rockchip,iommuùÿ�@ ´Wiep_mmu5ÊÔ ÎaclkifaceÉ Údisablediommu@ff914000rockchip,iommu ùÿ‘@ÿ‘P ´Wisp_mmu5ÍÕ ÎaclkifaceÉÖ Údisabledrga@ff920000rockchip,rk3288-rgaùÿ’€ ´5ÈÖjÎaclkhclksclkñb ýilm kcoreaxiahbvop@ff930000rockchip,rk3288-vop ùÿ“œÿ“ ´5žÑÎaclk_vopdclk_vophclk_vopñb ýdef kaxiahbdclkÿcÚokayportb endpoint@0ù dbwendpoint@1ù ebsendpoint@2ù fbmendpoint@3ù gbpiommu@ff930300rockchip,iommuùÿ“ ´ Wvopb_mmu5ÅÑ Îaclkifaceñb ÉÚokaybcvop@ff940000rockchip,rk3288-vop ùÿ”œÿ” ´5Æ¿ÒÎaclk_vopdclk_vophclk_vopñb ý°±² kaxiahbdclkÿh Údisabledportb endpoint@0ù ibxendpoint@1ù jbtendpoint@2ù kbnendpoint@3ù lbqiommu@ff940300rockchip,iommuùÿ” ´ Wvopl_mmu5ÆÒ Îaclkifaceñb É Údisabledbhmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsiùÿ–@ ´5~d Îrefpclkñb @ Údisabledportsportendpoint@0ù mbfendpoint@1ù nbklvds@ff96c000rockchip,rk3288-lvdsùÿ–À@5g Îpclk_lvdsÎlcdcÜoñb @ Údisabledportsport@0ùendpoint@0ù pbgendpoint@1ù qbldp@ff970000rockchip,rk3288-dpùÿ—@ ´b5icÎdppclkgrldpñb ýokdp@ Údisabledportsport@0ùendpoint@0ù sbeendpoint@1ù tbjhdmi@ff980000rockchip,rk3288-dw-hdmiùÿ˜ƒ@ ´g5hmnÎiahbisfrcecñb ÚokayÎdefaultunwedgeÜu×vb�portsportendpoint@0ù wbdendpoint@1ù xbivideo-codec@ff9a0000rockchip,rk3288-vpuùÿš´   Wvepuvdpu5ÐÜ Îaclkhclkÿyñb iommu@ff9a0800rockchip,iommuùÿš ´ Wvpu_mmu5ÐÜ ÎaclkifaceÉñb byiommu@ff9c0440rockchip,iommu ùÿœ@@ÿœ€@ ´o Whevc_mmu5ÏÛ ÎaclkifaceÉ Údisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760ùÿ£$´ Wjobmmugpu5Àzñb Úokay {b5gpu-opp-tableoperating-points-v2bzopp-100000000uõá|~ðopp-200000000u ëÂ|~ðopp-300000000uá£|B@opp-400000000uׄ|Èàopp-600000000u#ÃF|Ðqos@ffaa0000sysconùÿª b\qos@ffaa0080sysconùÿª€ b]qos@ffad0000sysconùÿ­ bQqos@ffad0100sysconùÿ­ bRqos@ffad0180sysconùÿ­€ bSqos@ffad0400sysconùÿ­ bTqos@ffad0480sysconùÿ­€ bUqos@ffad0500sysconùÿ­ bPqos@ffad0800sysconùÿ­ bVqos@ffad0880sysconùÿ­€ bWqos@ffad0900sysconùÿ­ bXqos@ffae0000sysconùÿ® b[qos@ffaf0000sysconùÿ¯ bYqos@ffaf0080sysconùÿ¯€ bZefuse@ffb40000rockchip,rk3288-efuseùÿ´ 5q Îpclk_efusecpu-id@7ùcpu_leakage@17ùinterrupt-controller@ffc01000 arm,gic-400 " 7@ùÿÀÿÀ ÿÀ@ ÿÀ`  ´ bpinctrlrockchip,rk3288-pinctrl@àŠÎdefault Ü|}~gpio0@ff750000rockchip,gpio-bankùÿu ´Q5@ H X " 7| dPMIC_SLEEP_APPMIC_INT_LPOWER_BUTTON_LRECOVERY_SW_LOT_RESETAP_WARM_RESET_HI2C0_SDA_PMICI2C0_SCL_PMICnFALUTbEgpio1@ff780000rockchip,gpio-bankùÿx ´R5A H X " 7gpio2@ff790000rockchip,gpio-bankùÿy ´S5B H X " 70 dCONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_Lb‰gpio3@ff7a0000rockchip,gpio-bankùÿz ´T5C H X " 7‚ dFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bankùÿ{ ´U5D H X " 7· dUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEb.gpio5@ff7c0000rockchip,gpio-bankùÿ| ´V5E H X " 7gpio6@ff7d0000rockchip,gpio-bankùÿ} ´W5F H X " 7gpio7@ff7e0000rockchip,gpio-bankùÿ~ ´X5G H X " 7ž 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Ñserial2:115200n8memoryímemoryù€power-button gpio-keysÎdefault܆power ÝPower .E ãt îd:gpio-restart gpio-restart .E Îdefault܇ Èemmc-pwrseqmmc-pwrseq-emmc܈Îdefault ‰ bsdio-pwrseqmmc-pwrseq-simple5Š Îext_clockÎdefaultÜ‹ .b vcc-5vregulator-fixed´vcc_5vÃ×éLK@LK@ bŒvcc33-sysregulator-fixed ´vcc33_sysÃ×é2Z 2Z bvcc50-hdmiregulator-fixed ´vcc50_hdmiÃ× Œ  3J ÎdefaultÜ�vdd-logicpwm-regulator ´vdd_logic 8ŽÊ = H{ \”Ã×é~ð™p vcc33_ioregulator-fixed ´vcc33_ioÃ× bIsound!rockchip,rockchip-audio-max98090 oVEYRON-HDMI ~� ’� #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-paramspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,hdmi-codecrockchip,i2s-controller