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´<Îi2c5L¹defaultÇ@Úokayá€pmic@1brockchip,rk808ù&A´ñxin32krk808-clkout2sA A ¹defaultÇBCDE}ž¬F¸FÄFÐFÜFèFô F&3bregulatorsDCDC_REG1@Tf q°~\À–vdd_arm¥pb regulator-state-memºDCDC_REG2@Tf øP~Жvdd_gpu¥pburegulator-state-memÓëB@DCDC_REG3@T–vcc_ddrregulator-state-memÓDCDC_REG4@Tf2Z ~2Z –vcc_iobregulator-state-memÓë2Z LDO_REG1@Tfw@~w@ –vcc18_ldo1bregulator-state-memÓëw@LDO_REG2@Tf2Z ~2Z  –vcc33_mipiregulator-state-memºLDO_REG3@TfB@~B@–vdd_10regulator-state-memÓëB@LDO_REG4@Tfw@~w@ –vcc18_codecregulator-state-memÓëw@LDO_REG5@Tfw@~2Z  –vccio_sdbregulator-state-memÓë2Z LDO_REG6@TfB@~B@ –vdd10_lcdregulator-state-memÓëB@LDO_REG7@Tfw@~w@–vcc_18bregulator-state-memÓëw@LDO_REG8@Tfw@~w@ –vcc18_lcdregulator-state-memÓëw@SWITCH_REG1@T –vcc33_sdbregulator-state-memÓSWITCH_REG2@T –vcc33_lanb:regulator-state-memÓi2c@ff660000rockchip,rk3288-i2cùÿf ´=Îi2c5N¹defaultÇGÚokaypwm@ff680000rockchip,rk3288-pwmùÿh¹defaultÇH5_ÎpwmÚokaypwm@ff680010rockchip,rk3288-pwmùÿh¹defaultÇI5_Îpwm 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedbroken-cddisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizedvs-gpiosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellssdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthstdout-pathautorepeatlinux,codelabellinux,input-typedebounce-intervallinux,default-triggerreset-gpiossimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssound-daistartup-delay-usvin-supply